Lioncash
eba3a06d80
frontend: Introduce FPSCR register helper class
...
Encapsulates all of the FPSCR state.
2016-08-24 20:51:14 +01:00
MerryMage
b5a86889cd
Implement VCVT
2016-08-23 22:20:04 +01:00
MerryMage
8d1b9f32ca
Standardize indentation of switch statments
2016-08-23 12:19:27 +01:00
Lioncash
1abe881921
basic_block: Add proxy member functions for the instruction list
...
Currently basic block kind of acts like a 'dumb struct' which makes things
a little more verbose to write (as opposed to keeping it all in one place,
I guess). It's also a little wonky conceptually, considering a block is
composed of instructions (i.e. 'contains' them).
So providing accessors that make it act more like a container can make working
with algorithms a little nicer. It also makes the API a little more
defined.
Ideally, the list would be only available through a function, but
currently, the pool allocator is exposed, which seems somewhat odd,
considering the block itself should manage its overall allocations
(with placement new, and regular new), rather than putting that
sanitizing directly on the IR emitter (it should just care about emission,
not block state). However, recontaining that can be followed up with,
as it's very trivial to do.
2016-08-22 13:44:56 +01:00
MerryMage
269160ef0d
emit_x64: Clear RSB-related caches when ClearCache() is called
2016-08-18 18:18:44 +01:00
MerryMage
1a3f3ac435
emit_x64: Correct behaviour of PackedOperation for immediate argument
...
x64 MOVD_xmm does not support an immediate oparg
2016-08-18 18:17:17 +01:00
MerryMage
b2de47954b
EmitX64: Emit correct cycle count on cond failure
2016-08-18 18:16:18 +01:00
MerryMage
0ebb572e2d
Optimization: Make RSB a ring buffer instead of a stack
2016-08-15 15:48:22 +01:00
MerryMage
7d7ac0af71
Optimization: Make SVC use RSB
2016-08-15 15:02:08 +01:00
MerryMage
6c45619aa1
Optimization: Implement terminal LinkBlockFast
2016-08-15 14:33:17 +01:00
MerryMage
624e84fa09
Optimization: Tweak RSB
2016-08-15 14:08:06 +01:00
MerryMage
070298b948
Optimization: bugfix! Return Stack Buffer location hash calculation was incorrect
2016-08-15 13:21:58 +01:00
MerryMage
e164ede4dc
TranslateArm: Implement MRS, MSR (imm), MSR (reg)
2016-08-15 11:50:49 +01:00
MerryMage
d43d97b990
EmitX64/EmitPushRSB: Assert that patch location is of correct size
2016-08-13 00:52:31 +01:00
MerryMage
960d14d18e
Optimization: Implement Return Stack Buffer
2016-08-13 00:10:23 +01:00
bunnei
8e68e6fdd9
TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16.
2016-08-12 19:00:44 +01:00
bunnei
4b09c0d032
TranslateArm: Implement QADD8 and UQADD8.
2016-08-12 19:00:44 +01:00
bunnei
127fbe99cb
TranslateArm: Implement QSUB8.
2016-08-12 19:00:44 +01:00
bunnei
86fe29c6d2
TranslateArm: Implement UQSUB8.
2016-08-12 19:00:44 +01:00
MerryMage
1029fd27ce
Update documentation (2016-08-12)
2016-08-12 18:17:31 +01:00
MerryMage
df39308e03
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:57:20 +01:00
Tillmann Karras
5d26899ac9
Add simplified LogicalShiftRight64 IR opcode
2016-08-08 22:27:05 +01:00
Tillmann Karras
ccb2aa96a5
Add support for the APSR.Q flag
2016-08-08 22:27:04 +01:00
MerryMage
975f011fc0
BackendX64/RegAlloc: Do not allocate RSP for guest use
2016-08-08 16:01:07 +01:00
MerryMage
abd113f160
EmitX64: Renamed patch_jmp_locations to patch_jg_locations
2016-08-08 15:56:07 +01:00
MerryMage
52fa998e6b
EmitX64: EmitTerminalLinkBlock: Fix behaviour when setting T and E flags
2016-08-07 22:47:43 +01:00
MerryMage
04c1a0d2de
EmitX64: Switch MXCSR when switching to interpreter
2016-08-07 22:47:17 +01:00
MerryMage
a32063fa60
EmitX64: Implement block linking
2016-08-07 22:11:39 +01:00
MerryMage
a2c2db277b
VFP: Implement VMOV (all variants)
2016-08-07 19:25:12 +01:00
MerryMage
aba705f6b9
BackendX64: Merge Routines into BlockOfCode
2016-08-07 18:08:48 +01:00
MerryMage
0f412247ed
VFP: Implement VSQRT
2016-08-07 12:19:07 +01:00
MerryMage
3f1345a1a5
VFP: Implement VNMUL, VDIV
2016-08-07 10:56:12 +01:00
MerryMage
12e7f2c359
VFP: Implement VMUL
2016-08-07 10:21:14 +01:00
MerryMage
97b5fa173f
VFP: Implement VSUB
2016-08-07 01:45:52 +01:00
MerryMage
ce6b5f8210
VFP: Implement VABS
2016-08-07 01:27:18 +01:00
MerryMage
f88b1b4c2e
FPSCR: Save and restore MSCSR across supervisor call, fix MXCSR exception mask
2016-08-07 01:10:19 +01:00
Tillmann Karras
846d07d7b5
Add Sub64 opcode
2016-08-06 21:17:11 +01:00
Tillmann Karras
b9f4f1ed0f
Add carry support to MostSignificantWord
2016-08-06 21:17:11 +01:00
MerryMage
4b31ea25a7
VFP: Implement VADD.{F32,F64}
2016-08-06 20:03:15 +01:00
MerryMage
856298577d
EmitX64: Don't give MOVSX or MOVZX an immediate oparg
2016-08-06 01:03:39 +01:00
MerryMage
640ce48baa
VFP: Implement {Get,Set}ExtendedRegister{32,64}
2016-08-05 19:06:10 +01:00
MerryMage
4c0a85f3b3
EmitX64: Correct EmitPack2x32To1x64 implementation
2016-08-05 18:43:24 +01:00
MerryMage
d80dcc5367
BackendX64/EmitX64: Eliminate unnecessary MOVs in Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong, Pack2x32To1x64
2016-08-05 15:27:29 +01:00
MerryMage
b4aa01ccf4
Merge remote-tracking branch 'tilkax/master'
2016-08-05 14:14:06 +01:00
MerryMage
94e75ad32f
BackendX64/EmitX64: Reduce number of MOVs by using reg_alloc.{RegisterAddDef,UseDefOpArg,UseOpArg}
2016-08-05 14:11:27 +01:00
MerryMage
ca40015145
IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint)
2016-08-05 14:07:27 +01:00
Tillmann Karras
72c503016c
Fix Pack2x32To1x64
...
Not sure how to fix this properly.
2016-08-05 02:09:30 +01:00
Tillmann Karras
3fdc093d10
Add more IR opcodes for multiply instructions
...
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
2016-08-05 02:09:30 +01:00
Tillmann Karras
af27ef8d6c
Optionally disassemble x86_64 code using LLVM
2016-08-05 02:08:41 +01:00
Tillmann Karras
2488926341
Add IR opcode RotateRightExtended
...
to rotate through the carry flag
2016-08-03 00:47:16 +01:00
