Lioncash
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f00789e6f7
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A64: Implement SABD
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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1e10017f4b
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ir: Add opcodes for signed absolute differences
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2020-04-22 20:46:17 +01:00 |
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Tillmann Karras
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d3b44c1b5a
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decoder_detail: use structured bindings
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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f745eb28bf
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simd_two_register_misc: Handle 64-bit case for SCVTF_int_4
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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3f6c529da2
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ir: Add opcode to perform the vector conversion S64->F64
Unfortunately x86 prior to AVX-512 doesn't really give us any convenient instruction to do the work for us
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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0e61ee6bf6
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A64: Implement SHLL/SHLL2
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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43e6e98c3b
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A64: Add missing decoding for PRFM (unscaled offset)
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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f2a85d5601
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A64: Implement UHSUB
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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b33360a324
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A64: Implement SHSUB
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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44a5f8095a
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ir: Add opcodes for performing vector halving subtracts
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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4f37c0ec5a
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A64: Implement SM4EKEY
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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3bde3347a5
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A64: Implement SM4E
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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b312d28295
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ir: Add an opcode for doing an SM4 lookup table query
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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4dcc7724e0
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A64: Implement UHADD
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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f8714f7250
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A64: Implement SHADD
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2020-04-22 20:46:17 +01:00 |
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Lioncash
|
089096948a
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ir: Add opcodes for performing halving adds
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
b38dd191bd
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disassembler_arm: Remove rotation helper function in favor of Common::RotateRight
Mildly reduces the amount of duplicated behavior
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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e71612d394
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A64: Implement SSHL (scalar)
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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ef1e69a1e3
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A64: Implement SSHL (vector)
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
21974ee57e
|
backend_x64/ir: Amend generic LogicalVShift() template to also handle signed variants
Also adds IR opcodes to dispatch said variants
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2020-04-22 20:46:17 +01:00 |
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Lioncash
|
cda75e2079
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A64: Implement CMTST's scalar variant
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2020-04-22 20:46:17 +01:00 |
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Lioncash
|
bebe7235ae
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A64: Implement UZP1 and UZP2
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2020-04-22 20:46:17 +01:00 |
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Lioncash
|
26d77c6f09
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ir: Add opcodes for performing vector deinterleaving
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
d6f9ed47d9
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A64: Implement FNEG (half-precision)
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2020-04-22 20:46:17 +01:00 |
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Lioncash
|
7efbd73bac
|
A64: Implement USHL (scalar)
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
41f4717f2b
|
A64: Implement FNEG (vector)
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
ba1cc6366d
|
A64: Implement RSUBHN/RSUBHN2
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
e41640fe33
|
A64: Implement RADDHN/RADDHN2
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
b719a6b3f7
|
A64: Implement XAR
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
0b1b131ec2
|
simd_two_register_misc: Factor out common comparison code
Gets rid of a tiny bit of duplicated code.
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
ed0b84da70
|
A64: Implement CMLE (zero)'s vector variant
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
b595a68ffa
|
A64: Implement CMTST (vector)
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
48c7f8630c
|
A64: Implement ADDHN{2} and SUBHN{2}
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
3acd9c9200
|
translate: zero extend result in Vpart when storing to lower part of vector
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
4ec735f707
|
A64: Implement CMLE (zero)'s scalar variant
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
6534184df2
|
A64: Implement CMLT (zero)'s scalar single/double-precision variant
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
8863c9bb4b
|
A64: Implement SHA512H2
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
033b890e25
|
A64: Implement SHA512H
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
d1f5b084b4
|
A64: Handle S32->F32 case for SCVTF (vector)
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
38fa984b53
|
IR: Add opcode for packed word->f32 conversions
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2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
b8587d8e34
|
A64: Implement SHA512SU1
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
44d846045a
|
A64: Implement SHA512SU0
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
ca903c1585
|
A64: Implement SHA256H and SHA256H2
|
2020-04-22 20:46:16 +01:00 |
|
MerryMage
|
e4237c44eb
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A64: Implement SCVTF (vector, integer), scalar varaint
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2020-04-22 20:46:16 +01:00 |
|
MerryMage
|
bfba38d0b6
|
impl: Reorganize scalar two-register misc instructions
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
ea582b17cc
|
A64: Implement SHA256SU1
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
06c5dcaf5e
|
simd_two_register_misc: Add missing zeroing of the vector for CMGT and CMLT
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
0d50d7314b
|
A64: Implement CMGE (zero)'s vector variant
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
ab35dc0e78
|
A64: Implement MLS (by element)
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
1651e60462
|
A64: Implement MUL (by element)
|
2020-04-22 20:46:16 +01:00 |
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