MerryMage
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bd106c3ae7
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A64: Implement SIMD instruction SSRA, vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f58aba9871
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A64: Implement SIMD instruction SSHR, vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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715ae1c229
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IR: Implement VectorArithmeticShiftRight
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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653c82d8f0
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impl: Improve Vpart setter
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e858ce0b35
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A64: Implement SIMD instructions XTN, XTN2
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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132c783320
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IR: Implement VectorNarrow
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1423584f9f
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constant_pool: Allow for 128-bit constants
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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69de50a878
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emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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cbc9f361b0
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IR: Implement VectorSub
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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3f93c77ace
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A64: Implement SIMD instruction USRA, vector variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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fb9d20f27f
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A64: Implement SIMD instruction USHR, vector variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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b22c5961f9
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IR: Implement VectorLogicalShiftRight
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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7ff280827b
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A64: Implement SIMD instructions USHLL, USHLL2
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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59ace60b03
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IR: Implement VectorZeroExtend
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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d3a4e1efe2
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IR: Vector instructions now take esize argument in emitter
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1d0cd95b23
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A64: Implement SIMD instruction SHL
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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f6247125c0
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IR: Implement VectorLogicalShiftLeft{8,16,32,64}
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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15e8231f24
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opcodes: Sort vector IR opcodes alphabetically
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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d74f4e35f6
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block_of_code: Increase constant pool size
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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e69288f803
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devirtualize: MinGW uses Intanium MFP ABI
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ad428cbd7a
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callback: Properly handle calls with return pointers and simplify interface
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2020-04-22 20:46:13 +01:00 |
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FernandoS27
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15871910af
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Implemented BSL, BIC, BIT and BIF vector instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
7a87e3fc55
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devirtualize: Handle Windows ABI
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
12173a8792
|
travis: Switch to yuzu-emu's unicorn repository
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
a78e13ff19
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fuzz_arm: Use SCOPE_FAIL
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ba4a779c62
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A32/decoder/arm: bug: Correct bitstring for SRS
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
f808a0fbde
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devirtualize: Devirtualize Itanium ABI MFPs at runtime
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
afe16fa0f3
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cast_util: Add BitCast and BitCastPointee
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
4e33629b0e
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A64: Move SDIV and UDIV out of data_processing_multiply.cpp
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
35a29a9665
|
A64: Implement ZIP1
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2020-04-22 20:46:13 +01:00 |
|
FernandoS27
|
586854117b
|
Implemented UMULH and SMULH instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1a7b7b541a
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A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
8ab7d8175c
|
impl: Add AdvSIMDExpandImm
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
ea69cb4474
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A64: Implement SUB (vector), scalar variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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4c5871d5d5
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A64: Implement ADD (vector), scalar variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
2a0850c068
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A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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7b33772ac6
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A64: Implement BIC (vector, register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
ca43be4146
|
docs: Update documentation (2018-02-05)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
eb5591859c
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A64: Implement FMOV (general)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
dd88cee15a
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translate/impl: Add Vpart
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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cc9efd13c9
|
A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
81713c2b77
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A64: Implement FCCMPE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
ef906dbbfa
|
A64: Implement FCCMP
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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44c3c2312a
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a64_jitstate: Remove unnecessary FPSCR_nzcv member
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
aac5af50e2
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IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
2ee39d6b36
|
A64: Implement FMOV (register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
b02b861242
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A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
5a65313236
|
A64: Implement CCMP (immediate)
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
ab4664de61
|
A64: Implement CCMN (immediate)
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
a6c6539109
|
A64: Implement CCMP (register)
|
2020-04-22 20:46:13 +01:00 |
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