347 lines
12 KiB
C++
347 lines
12 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "common/assert.h"
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#include "frontend/arm_types.h"
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#include "frontend/decoder/arm.h"
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#include "frontend/ir/ir.h"
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#include "frontend/ir/ir_emitter.h"
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#include "translate.h"
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namespace Dynarmic {
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namespace Arm {
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namespace {
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enum class ConditionalState {
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/// We haven't met any conditional instructions yet.
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None,
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/// Current instruction is a conditional. This marks the end of this basic block.
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Break,
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/// This basic block is made up solely of conditional instructions.
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Translating,
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};
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struct ArmTranslatorVisitor final {
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explicit ArmTranslatorVisitor(LocationDescriptor descriptor) : ir(descriptor) {
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ASSERT_MSG(!descriptor.TFlag, "The processor must be in Arm mode");
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}
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IREmitter ir;
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ConditionalState cond_state = ConditionalState::None;
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bool InterpretThisInstruction() {
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ir.SetTerm(IR::Term::Interpret(ir.current_location));
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return false;
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}
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bool UnpredictableInstruction() {
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ASSERT_MSG(false, "UNPREDICTABLE");
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return false;
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}
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bool LinkToNextInstruction() {
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auto next_location = ir.current_location;
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next_location.arm_pc += 4;
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ir.SetTerm(IR::Term::LinkBlock{next_location});
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return false;
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}
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bool ConditionPassed(Cond cond) {
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ASSERT_MSG(cond_state != ConditionalState::Translating,
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"In the current impl, ConditionPassed should never be called again once a non-AL cond is hit. "
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"(i.e.: one and only one conditional instruction per block)");
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ASSERT_MSG(cond_state != ConditionalState::Break,
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"This should never happen. We requested a break but that wasn't honored.");
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ASSERT_MSG(cond != Cond::NV, "NV conditional is obsolete");
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if (cond == Cond::AL) {
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// Everything is fine with the world
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return true;
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}
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// non-AL cond
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if (!ir.block.instructions.empty()) {
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// We've already emitted instructions. Quit for now, we'll make a new block here later.
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cond_state = ConditionalState::Break;
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ir.SetTerm(IR::Term::LinkBlock{ir.current_location});
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return false;
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}
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// We've not emitted instructions yet.
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// We'll emit one instruction, and set the block-entry conditional appropriately.
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cond_state = ConditionalState::Translating;
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ir.block.cond = cond;
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return true;
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}
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u32 rotr(u32 x, int shift) {
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shift &= 31;
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if (!shift) return x;
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return (x >> shift) | (x << (32 - shift));
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}
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u32 ArmExpandImm(int rotate, Imm8 imm8) {
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return rotr(static_cast<u32>(imm8), rotate*2);
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}
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bool arm_ADC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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u32 imm32 = ArmExpandImm(rotate, imm8);
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// ADC{S}<c> <Rd>, <Rn>, #<imm>
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if (ConditionPassed(cond)) {
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auto result = ir.AddWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.GetCFlag());
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if (d == Reg::PC) {
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ASSERT(!S);
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ir.ALUWritePC(result.result);
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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ir.SetRegister(d, result.result);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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}
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}
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return true;
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};
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bool arm_ADC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_ADC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_ADD_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_ADD_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_ADD_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_AND_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_AND_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_AND_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_BIC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_BIC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_BIC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_CMN_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_CMN_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_CMN_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_CMP_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
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u32 imm32 = ArmExpandImm(rotate, imm8);
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// CMP<c> <Rn>, #<imm>
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if (ConditionPassed(cond)) {
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auto result = ir.AddWithCarry(ir.GetRegister(n), ir.Imm32(~imm32), ir.Imm1(true));
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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}
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return true;
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}
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bool arm_CMP_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_CMP_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_EOR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_EOR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_EOR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_MOV_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_MOV_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_MOV_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_MVN_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_MVN_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_MVN_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_ORR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_ORR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_ORR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_RSB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_RSB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_RSB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_RSC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_RSC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_RSC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_SBC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_SBC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_SBC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_SUB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_SUB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_SUB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_TEQ_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_TEQ_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_TEQ_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_TST_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_TST_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_TST_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_SVC(Cond cond, Imm24 imm24) {
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u32 imm32 = imm24;
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// SVC<c> #<imm24>
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if (ConditionPassed(cond)) {
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ir.CallSupervisor(ir.Imm32(imm32));
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return LinkToNextInstruction();
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}
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return true;
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}
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bool arm_UDF() {
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return InterpretThisInstruction();
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}
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bool arm_REV(Cond cond, Reg d, Reg m) {
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// REV<c> <Rd>, <Rm>
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ASSERT(d != Reg::PC && m != Reg::PC);
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if (ConditionPassed(cond)) {
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auto result = ir.ByteReverseWord(ir.GetRegister(m));
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ir.SetRegister(d, result);
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}
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return true;
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}
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bool arm_REV16(Cond cond, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_REVSH(Cond cond, Reg d, Reg m) {
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// REVSH<c> <Rd>, <Rm>
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ASSERT(d != Reg::PC && m != Reg::PC);
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if (ConditionPassed(cond)) {
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auto rev_half = ir.ByteReverseHalf(ir.LeastSignificantHalf(ir.GetRegister(m)));
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ir.SetRegister(d, ir.SignExtendHalfToWord(rev_half));
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}
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return true;
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}
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};
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} // local namespace
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IR::Block TranslateArm(LocationDescriptor descriptor, MemoryRead32FuncType memory_read_32) {
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ArmTranslatorVisitor visitor{descriptor};
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bool should_continue = true;
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while (should_continue && visitor.cond_state == ConditionalState::None) {
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const u32 arm_pc = visitor.ir.current_location.arm_pc;
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const u32 arm_instruction = (*memory_read_32)(arm_pc);
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const auto decoder = DecodeArm<ArmTranslatorVisitor>(arm_instruction);
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if (decoder) {
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should_continue = decoder->call(visitor, arm_instruction);
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} else {
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should_continue = visitor.arm_UDF();
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}
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if (visitor.cond_state == ConditionalState::Break) {
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break;
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}
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visitor.ir.current_location.arm_pc += 4;
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visitor.ir.block.cycle_count++;
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}
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if (visitor.cond_state == ConditionalState::Translating) {
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if (should_continue) {
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visitor.ir.SetTerm(IR::Term::LinkBlock{visitor.ir.current_location});
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}
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visitor.ir.block.cond_failed = { visitor.ir.current_location };
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}
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return visitor.ir.block;
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}
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} // namespace Arm
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} // namespace Dynarmic
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