162 lines
4.5 KiB
C++
162 lines
4.5 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "translate_arm.h"
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namespace Dynarmic {
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namespace Arm {
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// Parallel Add/Subtract (Modulo arithmetic) instructions
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bool ArmTranslatorVisitor::arm_SADD8(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_SADD16(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_SASX(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_SSAX(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_SSUB8(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_SSUB16(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UADD8(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UADD16(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UASX(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_USAX(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_USUB8(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_USUB16(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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// Parallel Add/Subtract (Saturating) instructions
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bool ArmTranslatorVisitor::arm_QADD8(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_QADD16(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_QASX(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_QSAX(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_QSUB8(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_QSUB16(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UQADD8(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UQADD16(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UQASX(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UQSAX(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UQSUB8(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UQSUB16(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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// Parallel Add/Subtract (Halving) instructions
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bool ArmTranslatorVisitor::arm_SHADD8(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_SHADD16(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_SHASX(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_SHSAX(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_SHSUB8(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_SHSUB16(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UHADD8(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UHADD16(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UHASX(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UHSAX(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UHSUB8(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UHSUB16(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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} // namespace Arm
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} // namespace Dynarmic
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