1abe881921
Currently basic block kind of acts like a 'dumb struct' which makes things a little more verbose to write (as opposed to keeping it all in one place, I guess). It's also a little wonky conceptually, considering a block is composed of instructions (i.e. 'contains' them). So providing accessors that make it act more like a container can make working with algorithms a little nicer. It also makes the API a little more defined. Ideally, the list would be only available through a function, but currently, the pool allocator is exposed, which seems somewhat odd, considering the block itself should manage its overall allocations (with placement new, and regular new), rather than putting that sanitizing directly on the IR emitter (it should just care about emission, not block state). However, recontaining that can be followed up with, as it's very trivial to do.
79 lines
2.7 KiB
C++
79 lines
2.7 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "common/assert.h"
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#include "frontend/ir/basic_block.h"
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#include "frontend/ir/opcodes.h"
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#include "ir_opt/passes.h"
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namespace Dynarmic {
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namespace Optimization {
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void DeadCodeElimination(IR::Block& block) {
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const auto is_side_effect_free = [](IR::Opcode op) -> bool {
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switch (op) {
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case IR::Opcode::Breakpoint:
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case IR::Opcode::SetRegister:
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case IR::Opcode::SetExtendedRegister32:
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case IR::Opcode::SetExtendedRegister64:
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case IR::Opcode::SetNFlag:
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case IR::Opcode::SetZFlag:
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case IR::Opcode::SetCFlag:
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case IR::Opcode::SetVFlag:
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case IR::Opcode::OrQFlag:
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case IR::Opcode::BXWritePC:
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case IR::Opcode::CallSupervisor:
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case IR::Opcode::PushRSB:
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case IR::Opcode::FPAbs32:
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case IR::Opcode::FPAbs64:
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case IR::Opcode::FPAdd32:
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case IR::Opcode::FPAdd64:
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case IR::Opcode::FPDiv32:
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case IR::Opcode::FPDiv64:
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case IR::Opcode::FPMul32:
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case IR::Opcode::FPMul64:
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case IR::Opcode::FPNeg32:
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case IR::Opcode::FPNeg64:
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case IR::Opcode::FPSqrt32:
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case IR::Opcode::FPSqrt64:
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case IR::Opcode::FPSub32:
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case IR::Opcode::FPSub64:
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case IR::Opcode::ClearExclusive:
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case IR::Opcode::SetExclusive:
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case IR::Opcode::WriteMemory8:
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case IR::Opcode::WriteMemory16:
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case IR::Opcode::WriteMemory32:
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case IR::Opcode::WriteMemory64:
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case IR::Opcode::ExclusiveWriteMemory8:
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case IR::Opcode::ExclusiveWriteMemory16:
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case IR::Opcode::ExclusiveWriteMemory32:
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case IR::Opcode::ExclusiveWriteMemory64:
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return false;
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default:
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ASSERT(IR::GetTypeOf(op) != IR::Type::Void);
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return true;
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}
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};
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// We iterate over the instructions in reverse order.
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// This is because removing an instruction reduces the number of uses for earlier instructions.
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if (block.empty()) {
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return;
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}
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auto iter = block.end();
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do {
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--iter;
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if (!iter->HasUses() && is_side_effect_free(iter->GetOpcode())) {
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iter->Invalidate();
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iter = block.instructions.erase(iter);
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}
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} while (iter != block.begin());
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}
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} // namespace Optimization
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} // namespace Dynarmic
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