120 lines
3.7 KiB
C++
120 lines
3.7 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "backend_x64/a64_jitstate.h"
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#include "common/bit_util.h"
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#include "frontend/A64/location_descriptor.h"
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namespace Dynarmic::BackendX64 {
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u64 A64JitState::GetUniqueHash() const {
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u64 fpcr_u64 = static_cast<u64>(fpcr & A64::LocationDescriptor::FPCR_MASK) << 37;
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u64 pc_u64 = pc & A64::LocationDescriptor::PC_MASK;
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return pc_u64 | fpcr_u64;
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}
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/**
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* Comparing MXCSR and FPCR
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* ========================
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*
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* SSE MSCSR exception masks
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* -------------------------
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* PM bit 12 Precision Mask
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* UM bit 11 Underflow Mask
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* OM bit 10 Overflow Mask
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* ZM bit 9 Divide By Zero Mask
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* DM bit 8 Denormal Mask
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* IM bit 7 Invalid Operation Mask
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*
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* A64 FPCR exception trap enables
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* -------------------------------
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* IDE bit 15 Input Denormal exception trap enable
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* IXE bit 12 Inexact exception trap enable
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* UFE bit 11 Underflow exception trap enable
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* OFE bit 10 Overflow exception trap enable
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* DZE bit 9 Division by Zero exception trap enable
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* IOE bit 8 Invalid Operation exception trap enable
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*
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* SSE MXCSR mode bits
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* -------------------
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* FZ bit 15 Flush To Zero
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* DAZ bit 6 Denormals Are Zero
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* RN bits 13-14 Round to {0 = Nearest, 1 = Negative, 2 = Positive, 3 = Zero}
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*
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* A64 FPCR mode bits
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* ------------------
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* AHP bit 26 Alternative half-precision
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* DN bit 25 Default NaN
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* FZ bit 24 Flush to Zero
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* RMode bits 22-23 Round to {0 = Nearest, 1 = Positive, 2 = Negative, 3 = Zero}
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* FZ16 bit 19 Flush to Zero for half-precision
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*/
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constexpr u32 FPCR_MASK = 0x07C89F00;
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u32 A64JitState::GetFpcr() const {
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return fpcr;
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}
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void A64JitState::SetFpcr(u32 value) {
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fpcr = value & FPCR_MASK;
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guest_MXCSR &= 0x0000003D;
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guest_MXCSR |= 0x00001f80; // Mask all exceptions
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// RMode
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const std::array<u32, 4> MXCSR_RMode {0x0, 0x4000, 0x2000, 0x6000};
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guest_MXCSR |= MXCSR_RMode[(value >> 22) & 0x3];
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if (Common::Bit<24>(value)) {
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guest_MXCSR |= (1 << 15); // SSE Flush to Zero
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guest_MXCSR |= (1 << 6); // SSE Denormals are Zero
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}
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}
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/**
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* Comparing MXCSR and FPSR
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* ========================
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*
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* SSE MXCSR exception flags
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* -------------------------
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* PE bit 5 Precision Flag
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* UE bit 4 Underflow Flag
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* OE bit 3 Overflow Flag
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* ZE bit 2 Divide By Zero Flag
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* DE bit 1 Denormal Flag // Appears to only be set when MXCSR.DAZ = 0
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* IE bit 0 Invalid Operation Flag
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*
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* A64 FPSR cumulative exception bits
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* ----------------------------------
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* QC bit 27 Cumulative saturation bit
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* IDC bit 7 Input Denormal cumulative exception bit // Only ever set when FPCR.FTZ = 1
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* IXC bit 4 Inexact cumulative exception bit
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* UFC bit 3 Underflow cumulative exception bit
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* OFC bit 2 Overflow cumulative exception bit
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* DZC bit 1 Division by Zero cumulative exception bit
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* IOC bit 0 Invalid Operation cumulative exception bit
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*/
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u32 A64JitState::GetFpsr() const {
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u32 fpsr = 0;
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fpsr |= (guest_MXCSR & 0b0000000000001); // IOC = IE
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fpsr |= (guest_MXCSR & 0b0000000111100) >> 1; // IXC, UFC, OFC, DZC = PE, UE, OE, ZE
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fpsr |= FPSCR_IDC;
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fpsr |= FPSCR_UFC;
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return fpsr;
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}
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void A64JitState::SetFpsr(u32 value) {
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guest_MXCSR &= ~0x0000003D;
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guest_MXCSR |= ( value ) & 0b0000000000001; // IE = IOC
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guest_MXCSR |= ( value << 1) & 0b0000000111100; // PE, UE, OE, ZE = IXC, UFC, OFC, DZC
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FPSCR_IDC = value & (1 << 7);
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FPSCR_UFC = value & (1 << 3);
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}
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} // namespace Dynarmic::BackendX64
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