311 lines
11 KiB
C++
311 lines
11 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <map>
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#include <unordered_map>
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#include "backend_x64/emit_x64.h"
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#include "common/x64/emitter.h"
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// TODO: More optimal use of immediates.
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// TODO: Have ARM flags in host flags and not have them use up GPR registers unless necessary.
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// TODO: Actually implement that proper instruction selector you've always wanted to sweetheart.
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using namespace Gen;
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namespace Dynarmic {
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namespace BackendX64 {
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// Mapping from opcode to Emit* member function.
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const static std::map<IR::Opcode, void (EmitX64::*)(IR::Value*)> emit_fns {
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#define OPCODE(name, type, ...) { IR::Opcode::name, &EmitX64::Emit##name },
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#include "frontend_arm/ir/opcodes.inc"
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#undef OPCODE
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};
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static IR::Inst* FindUseWithOpcode(IR::Inst* inst, IR::Opcode opcode) {
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// Gets first found use.
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auto uses = inst->GetUses();
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auto iter = std::find_if(uses.begin(), uses.end(), [opcode](const auto& use){ return use->GetOpcode() == opcode; });
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return iter == uses.end() ? nullptr : reinterpret_cast<IR::Inst*>(iter->get());
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}
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CodePtr EmitX64::Emit(Dynarmic::IR::Block block) {
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code->INT3();
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CodePtr code_ptr = code->GetCodePtr();
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// Call Emit* member function for each instruction.
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for (const auto& value : block.instructions) {
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if (inhibit_emission.count(value.get()) != 0)
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continue;
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(this->*emit_fns.at(value->GetOpcode()))(value.get());
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reg_alloc.EndOfAllocScope();
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}
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EmitReturnToDispatch();
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return code_ptr;
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}
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void EmitX64::EmitImmU1(IR::Value*) {
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ASSERT_MSG(0, "Unimplemented");
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}
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void EmitX64::EmitImmU8(IR::Value* value_) {
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auto value = reinterpret_cast<IR::ImmU8*>(value_);
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X64Reg result = reg_alloc.DefRegister(value);
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code->MOV(32, R(result), Imm32(value->value));
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}
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void EmitX64::EmitImmU32(IR::Value* value_) {
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auto value = reinterpret_cast<IR::ImmU32*>(value_);
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X64Reg result = reg_alloc.DefRegister(value);
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code->MOV(32, R(result), Imm32(value->value));
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}
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void EmitX64::EmitImmRegRef(IR::Value*) {
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return; // No need to do anything.
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}
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void EmitX64::EmitGetRegister(IR::Value* value_) {
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auto value = reinterpret_cast<IR::Inst*>(value_);
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auto regref = reinterpret_cast<IR::ImmRegRef*>(value->GetArg(0).get());
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X64Reg result = reg_alloc.DefRegister(value);
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code->MOV(32, R(result), MDisp(R15, offsetof(JitState, Reg) + static_cast<size_t>(regref->value) * sizeof(u32)));
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}
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void EmitX64::EmitSetRegister(IR::Value* value_) {
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auto value = reinterpret_cast<IR::Inst*>(value_);
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auto regref = reinterpret_cast<IR::ImmRegRef*>(value->GetArg(0).get());
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X64Reg to_store = reg_alloc.UseRegister(value->GetArg(1).get());
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code->MOV(32, MDisp(R15, offsetof(JitState, Reg) + static_cast<size_t>(regref->value) * sizeof(u32)), R(to_store));
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}
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void EmitX64::EmitGetNFlag(IR::Value* value_) {
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auto value = reinterpret_cast<IR::Inst*>(value_);
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X64Reg result = reg_alloc.DefRegister(value);
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code->MOV(32, R(result), MDisp(R15, offsetof(JitState, Cpsr)));
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code->SHR(32, R(result), Imm8(31));
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}
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void EmitX64::EmitSetNFlag(IR::Value* value_) {
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auto value = reinterpret_cast<IR::Inst*>(value_);
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X64Reg to_store = reg_alloc.UseRegister(value->GetArg(0).get());
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code->SHL(32, R(to_store), Imm8(31));
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code->AND(32, MDisp(R15, offsetof(JitState, Cpsr)), Imm32(~static_cast<u32>(1 << 31)));
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code->OR(32, MDisp(R15, offsetof(JitState, Cpsr)), R(to_store));
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}
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void EmitX64::EmitGetZFlag(IR::Value* value_) {
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auto value = reinterpret_cast<IR::Inst*>(value_);
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X64Reg result = reg_alloc.DefRegister(value);
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code->MOV(32, R(result), MDisp(R15, offsetof(JitState, Cpsr)));
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code->SHR(32, R(result), Imm8(30));
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code->AND(32, R(result), Imm32(1));
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}
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void EmitX64::EmitSetZFlag(IR::Value* value_) {
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auto value = reinterpret_cast<IR::Inst*>(value_);
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X64Reg to_store = reg_alloc.UseRegister(value->GetArg(0).get());
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code->SHL(32, R(to_store), Imm8(30));
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code->AND(32, MDisp(R15, offsetof(JitState, Cpsr)), Imm32(~static_cast<u32>(1 << 30)));
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code->OR(32, MDisp(R15, offsetof(JitState, Cpsr)), R(to_store));
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}
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void EmitX64::EmitGetCFlag(IR::Value* value_) {
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auto value = reinterpret_cast<IR::Inst*>(value_);
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X64Reg result = reg_alloc.DefRegister(value);
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code->MOV(32, R(result), MDisp(R15, offsetof(JitState, Cpsr)));
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code->SHR(32, R(result), Imm8(29));
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code->AND(32, R(result), Imm32(1));
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}
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void EmitX64::EmitSetCFlag(IR::Value* value_) {
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auto value = reinterpret_cast<IR::Inst*>(value_);
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X64Reg to_store = reg_alloc.UseRegister(value->GetArg(0).get());
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code->SHL(32, R(to_store), Imm8(29));
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code->AND(32, MDisp(R15, offsetof(JitState, Cpsr)), Imm32(~static_cast<u32>(1 << 29)));
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code->OR(32, MDisp(R15, offsetof(JitState, Cpsr)), R(to_store));
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}
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void EmitX64::EmitGetVFlag(IR::Value* value_) {
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auto value = reinterpret_cast<IR::Inst*>(value_);
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X64Reg result = reg_alloc.DefRegister(value);
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code->MOV(32, R(result), MDisp(R15, offsetof(JitState, Cpsr)));
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code->SHR(32, R(result), Imm8(28));
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code->AND(32, R(result), Imm32(1));
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}
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void EmitX64::EmitSetVFlag(IR::Value* value_) {
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auto value = reinterpret_cast<IR::Inst*>(value_);
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X64Reg to_store = reg_alloc.UseRegister(value->GetArg(0).get());
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code->SHL(32, R(to_store), Imm8(28));
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code->AND(32, MDisp(R15, offsetof(JitState, Cpsr)), Imm32(~static_cast<u32>(1 << 28)));
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code->OR(32, MDisp(R15, offsetof(JitState, Cpsr)), R(to_store));
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}
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void EmitX64::EmitGetCarryFromOp(IR::Value*) {
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ASSERT_MSG(0, "should never happen");
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}
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void EmitX64::EmitLeastSignificantByte(IR::Value* value_) {
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auto value = reinterpret_cast<IR::Inst*>(value_);
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reg_alloc.UseDefRegister(value->GetArg(0).get(), value);
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}
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void EmitX64::EmitMostSignificantBit(IR::Value* value_) {
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auto value = reinterpret_cast<IR::Inst*>(value_);
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X64Reg result = reg_alloc.UseDefRegister(value->GetArg(0).get(), value);
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code->SHL(32, R(result), Imm8(31));
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}
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void EmitX64::EmitIsZero(IR::Value* value_) {
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auto value = reinterpret_cast<IR::Inst*>(value_);
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X64Reg result = reg_alloc.UseDefRegister(value->GetArg(0).get(), value);
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code->TEST(32, R(result), R(result));
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code->SETcc(CCFlags::CC_E, R(result));
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code->MOVZX(32, 8, result, R(result));
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}
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void EmitX64::EmitLogicalShiftLeft(IR::Value* value_) {
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auto value = reinterpret_cast<IR::Inst*>(value_);
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auto carry_inst = FindUseWithOpcode(value, IR::Opcode::GetCarryFromOp);
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// TODO: Consider using BMI2 instructions like SHLX when arm-in-host flags is implemented.
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if (!carry_inst) {
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X64Reg shift = reg_alloc.UseRegister(value->GetArg(1).get(), {HostLoc::RCX});
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X64Reg result = reg_alloc.UseDefRegister(value->GetArg(0).get(), value);
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X64Reg zero = reg_alloc.ScratchRegister();
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// The 32-bit x64 SHL instruction masks the shift count by 0x1F before performing the shift.
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// ARM differs from the behaviour: It does not mask the count, so shifts above 31 result in zeros.
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code->SHL(32, R(result), R(shift));
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code->XOR(32, R(zero), R(zero));
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code->CMP(8, R(shift), Imm8(32));
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code->CMOVcc(32, result, R(zero), CC_NB);
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} else {
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inhibit_emission.insert(carry_inst);
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X64Reg shift = reg_alloc.UseRegister(value->GetArg(1).get(), {HostLoc::RCX});
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X64Reg result = reg_alloc.UseDefRegister(value->GetArg(0).get(), value);
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X64Reg carry = reg_alloc.UseDefRegister(value->GetArg(2).get(), carry_inst);
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// TODO: Optimize this.
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code->CMP(8, R(shift), Imm8(32));
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auto Rs_gt32 = code->J_CC(CC_A);
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auto Rs_eq32 = code->J_CC(CC_E);
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// if (Rs & 0xFF < 32) {
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code->BT(32, R(carry), Imm8(0)); // Set the carry flag for correct behaviour in the case when Rs & 0xFF == 0
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code->SHL(32, R(result), R(shift));
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code->SETcc(CC_C, R(carry));
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auto jmp_to_end_1 = code->J();
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// } else if (Rs & 0xFF > 32) {
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code->SetJumpTarget(Rs_gt32);
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code->XOR(32, R(result), R(result));
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code->XOR(32, R(carry), R(carry));
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auto jmp_to_end_2 = code->J();
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// } else if (Rs & 0xFF == 32) {
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code->SetJumpTarget(Rs_eq32);
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code->MOV(32, R(carry), R(result));
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code->AND(32, R(carry), Imm8(1));
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code->XOR(32, R(result), R(result));
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// }
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code->SetJumpTarget(jmp_to_end_1);
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code->SetJumpTarget(jmp_to_end_2);
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}
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}
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void EmitX64::EmitLogicalShiftRight(IR::Value* value_) {
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auto value = reinterpret_cast<IR::Inst*>(value_);
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auto carry_inst = FindUseWithOpcode(value, IR::Opcode::GetCarryFromOp);
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if (!carry_inst) {
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X64Reg shift = reg_alloc.UseRegister(value->GetArg(1).get(), {HostLoc::RCX});
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X64Reg result = reg_alloc.UseDefRegister(value->GetArg(0).get(), value);
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X64Reg zero = reg_alloc.ScratchRegister();
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// The 32-bit x64 SHR instruction masks the shift count by 0x1F before performing the shift.
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// ARM differs from the behaviour: It does not mask the count, so shifts above 31 result in zeros.
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code->SHR(32, R(result), R(shift));
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code->XOR(32, R(zero), R(zero));
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code->CMP(8, R(shift), Imm8(32));
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code->CMOVcc(32, result, R(zero), CC_NB);
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} else {
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inhibit_emission.insert(carry_inst);
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X64Reg shift = reg_alloc.UseRegister(value->GetArg(1).get(), {HostLoc::RCX});
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X64Reg result = reg_alloc.UseDefRegister(value->GetArg(0).get(), value);
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X64Reg carry = reg_alloc.UseDefRegister(value->GetArg(2).get(), carry_inst);
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// TODO: Optimize this.
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code->CMP(32, R(shift), Imm8(32));
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auto Rs_gt32 = code->J_CC(CC_A);
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auto Rs_eq32 = code->J_CC(CC_E);
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// if (Rs & 0xFF == 0) goto end;
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code->TEST(32, R(shift), R(shift));
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auto Rs_zero = code->J_CC(CC_Z);
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// if (Rs & 0xFF < 32) {
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code->SHR(32, R(result), R(shift));
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code->SETcc(CC_C, R(carry));
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auto jmp_to_end_1 = code->J();
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// } else if (Rs & 0xFF > 32) {
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code->SetJumpTarget(Rs_gt32);
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code->MOV(32, R(result), Imm32(0));
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code->MOV(8, R(carry), Imm8(0));
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auto jmp_to_end_2 = code->J();
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// } else if (Rs & 0xFF == 32) {
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code->SetJumpTarget(Rs_eq32);
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code->BT(32, R(result), Imm8(31));
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code->SETcc(CC_C, R(carry));
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code->MOV(32, R(result), Imm32(0));
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// }
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code->SetJumpTarget(jmp_to_end_1);
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code->SetJumpTarget(jmp_to_end_2);
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code->SetJumpTarget(Rs_zero);
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}
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}
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void EmitX64::EmitReturnToDispatch() {
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code->JMP(routines->RunCodeReturnAddress(), true);
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}
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} // namespace BackendX64
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} // namespace Dynarmic
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