482 lines
17 KiB
C++
482 lines
17 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <tuple>
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#include "common/assert.h"
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#include "frontend/arm_types.h"
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#include "frontend/decoder/thumb1.h"
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#include "frontend/ir_emitter.h"
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#include "frontend/translate.h"
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namespace Dynarmic {
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namespace Arm {
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struct TranslatorVisitor final {
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explicit TranslatorVisitor(LocationDescriptor descriptor) : ir(descriptor) {
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ASSERT_MSG(descriptor.TFlag, "The processor must be in Thumb mode");
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}
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IREmitter ir;
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bool TranslateThisInstruction() {
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ir.SetTerm(IR::Term::Interpret(ir.current_location));
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return false;
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}
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bool UnpredictableInstruction() {
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ASSERT_MSG(false, "UNPREDICTABLE");
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return false;
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}
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bool thumb1_LSL_imm(Imm5 imm5, Reg m, Reg d) {
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u8 shift_n = imm5;
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// LSLS <Rd>, <Rm>, #<imm5>
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auto cpsr_c = ir.GetCFlag();
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auto result = ir.LogicalShiftLeft(ir.GetRegister(m), ir.Imm8(shift_n), cpsr_c);
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ir.SetRegister(d, result.result);
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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return true;
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}
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bool thumb1_LSR_imm(Imm5 imm5, Reg m, Reg d) {
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u8 shift_n = imm5 != 0 ? imm5 : 32;
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// LSRS <Rd>, <Rm>, #<imm5>
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auto cpsr_c = ir.GetCFlag();
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auto result = ir.LogicalShiftRight(ir.GetRegister(m), ir.Imm8(shift_n), cpsr_c);
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ir.SetRegister(d, result.result);
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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return true;
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}
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bool thumb1_ASR_imm(Imm5 imm5, Reg m, Reg d) {
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u8 shift_n = imm5 != 0 ? imm5 : 32;
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// ASRS <Rd>, <Rm>, #<imm5>
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auto cpsr_c = ir.GetCFlag();
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auto result = ir.ArithmeticShiftRight(ir.GetRegister(m), ir.Imm8(shift_n), cpsr_c);
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ir.SetRegister(d, result.result);
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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return true;
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}
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bool thumb1_ADD_reg_t1(Reg m, Reg n, Reg d) {
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// ADDS <Rd>, <Rn>, <Rm>
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// Note that it is not possible to encode Rd == R15.
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auto result = ir.AddWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(0));
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ir.SetRegister(d, result.result);
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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return true;
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}
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bool thumb1_SUB_reg(Reg m, Reg n, Reg d) {
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// SUBS <Rd>, <Rn>, <Rm>
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// Note that it is not possible to encode Rd == R15.
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auto result = ir.SubWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(1));
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ir.SetRegister(d, result.result);
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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return true;
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}
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bool thumb1_ADD_imm_t1(Imm3 imm3, Reg n, Reg d) {
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u32 imm32 = imm3 & 0x7;
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// ADDS <Rd>, <Rn>, #<imm3>
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// Rd can never encode R15.
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auto result = ir.AddWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(0));
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ir.SetRegister(d, result.result);
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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return true;
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}
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bool thumb1_SUB_imm_t1(Imm3 imm3, Reg n, Reg d) {
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u32 imm32 = imm3 & 0x7;
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// SUBS <Rd>, <Rn>, #<imm3>
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// Rd can never encode R15.
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auto result = ir.SubWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(1));
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ir.SetRegister(d, result.result);
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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return true;
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}
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bool thumb1_MOV_imm(Reg d, Imm8 imm8) {
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u32 imm32 = imm8 & 0xFF;
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// MOVS <Rd>, #<imm8>
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// Rd can never encode R15.
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auto result = ir.Imm32(imm32);
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ir.SetRegister(d, result);
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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return true;
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}
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bool thumb1_CMP_imm(Reg n, Imm8 imm8) {
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u32 imm32 = imm8 & 0xFF;
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// CMP <Rn>, #<imm8>
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auto result = ir.SubWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(1));
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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return true;
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}
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bool thumb1_ADD_imm_t2(Reg d_n, Imm8 imm8) {
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u32 imm32 = imm8 & 0xFF;
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Reg d = d_n, n = d_n;
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// ADDS <Rdn>, #<imm8>
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// Rd can never encode R15.
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auto result = ir.AddWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(0));
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ir.SetRegister(d, result.result);
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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return true;
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}
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bool thumb1_SUB_imm_t2(Reg d_n, Imm8 imm8) {
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u32 imm32 = imm8 & 0xFF;
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Reg d = d_n, n = d_n;
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// SUBS <Rd>, <Rn>, #<imm3>
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// Rd can never encode R15.
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auto result = ir.SubWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(1));
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ir.SetRegister(d, result.result);
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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return true;
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}
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bool thumb1_AND_reg(Reg m, Reg d_n) {
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const Reg d = d_n, n = d_n;
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// ANDS <Rdn>, <Rm>
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// Note that it is not possible to encode Rdn == R15.
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auto result = ir.And(ir.GetRegister(n), ir.GetRegister(m));
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ir.SetRegister(d, result);
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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return true;
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}
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bool thumb1_EOR_reg(Reg m, Reg d_n) {
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const Reg d = d_n, n = d_n;
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// EORS <Rdn>, <Rm>
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// Note that it is not possible to encode Rdn == R15.
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auto result = ir.Eor(ir.GetRegister(n), ir.GetRegister(m));
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ir.SetRegister(d, result);
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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return true;
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}
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bool thumb1_LSL_reg(Reg m, Reg d_n) {
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const Reg d = d_n, n = d_n;
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// LSLS <Rdn>, <Rm>
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auto shift_n = ir.LeastSignificantByte(ir.GetRegister(m));
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auto apsr_c = ir.GetCFlag();
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auto result_carry = ir.LogicalShiftLeft(ir.GetRegister(n), shift_n, apsr_c);
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ir.SetRegister(d, result_carry.result);
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ir.SetNFlag(ir.MostSignificantBit(result_carry.result));
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ir.SetZFlag(ir.IsZero(result_carry.result));
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ir.SetCFlag(result_carry.carry);
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return true;
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}
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bool thumb1_LSR_reg(Reg m, Reg d_n) {
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const Reg d = d_n, n = d_n;
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// LSRS <Rdn>, <Rm>
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auto shift_n = ir.LeastSignificantByte(ir.GetRegister(m));
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auto cpsr_c = ir.GetCFlag();
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auto result = ir.LogicalShiftRight(ir.GetRegister(n), shift_n, cpsr_c);
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ir.SetRegister(d, result.result);
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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return true;
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}
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bool thumb1_ASR_reg(Reg m, Reg d_n) {
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const Reg d = d_n, n = d_n;
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// ASRS <Rdn>, <Rm>
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auto shift_n = ir.LeastSignificantByte(ir.GetRegister(m));
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auto cpsr_c = ir.GetCFlag();
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auto result = ir.ArithmeticShiftRight(ir.GetRegister(n), shift_n, cpsr_c);
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ir.SetRegister(d, result.result);
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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return true;
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}
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bool thumb1_ADC_reg(Reg m, Reg d_n) {
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Reg d = d_n, n = d_n;
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// ADCS <Rdn>, <Rm>
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// Note that it is not possible to encode Rd == R15.
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auto aspr_c = ir.GetCFlag();
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auto result = ir.AddWithCarry(ir.GetRegister(n), ir.GetRegister(m), aspr_c);
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ir.SetRegister(d, result.result);
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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return true;
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}
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bool thumb1_SBC_reg(Reg m, Reg d_n) {
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Reg d = d_n, n = d_n;
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// SBCS <Rdn>, <Rm>
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// Note that it is not possible to encode Rd == R15.
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auto aspr_c = ir.GetCFlag();
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auto result = ir.SubWithCarry(ir.GetRegister(n), ir.GetRegister(m), aspr_c);
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ir.SetRegister(d, result.result);
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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return true;
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}
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bool thumb1_ROR_reg(Reg m, Reg d_n) {
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Reg d = d_n, n = d_n;
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// RORS <Rdn>, <Rm>
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auto shift_n = ir.LeastSignificantByte(ir.GetRegister(m));
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auto cpsr_c = ir.GetCFlag();
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auto result = ir.RotateRight(ir.GetRegister(n), shift_n, cpsr_c);
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ir.SetRegister(d, result.result);
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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return true;
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}
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bool thumb1_TST_reg(Reg m, Reg n) {
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// TST <Rn>, <Rm>
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auto result = ir.And(ir.GetRegister(n), ir.GetRegister(m));
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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return true;
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}
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bool thumb1_RSB_imm(Reg n, Reg d) {
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// RSBS <Rd>, <Rn>, #0
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// Rd can never encode R15.
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auto result = ir.SubWithCarry(ir.Imm32(0), ir.GetRegister(n), ir.Imm1(1));
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ir.SetRegister(d, result.result);
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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return true;
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}
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bool thumb1_CMP_reg_t1(Reg m, Reg n) {
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// CMP <Rn>, <Rm>
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auto result = ir.SubWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(1));
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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return true;
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}
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bool thumb1_CMN_reg(Reg m, Reg n) {
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// CMN <Rn>, <Rm>
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auto result = ir.AddWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(0));
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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return true;
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}
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bool thumb1_ORR_reg(Reg m, Reg d_n) {
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Reg d = d_n, n = d_n;
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// ORRS <Rdn>, <Rm>
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// Rd cannot encode R15.
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auto result = ir.Or(ir.GetRegister(m), ir.GetRegister(n));
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ir.SetRegister(d, result);
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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return true;
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}
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bool thumb1_BIC_reg(Reg m, Reg d_n) {
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Reg d = d_n, n = d_n;
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// BICS <Rdn>, <Rm>
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// Rd cannot encode R15.
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auto result = ir.And(ir.GetRegister(n), ir.Not(ir.GetRegister(m)));
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ir.SetRegister(d, result);
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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return true;
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}
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bool thumb1_MVN_reg(Reg m, Reg d) {
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// MVNS <Rd>, <Rm>
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// Rd cannot encode R15.
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auto result = ir.Not(ir.GetRegister(m));
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ir.SetRegister(d, result);
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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return true;
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}
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bool thumb1_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) {
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Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo;
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Reg d = d_n, n = d_n;
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if (n == Reg::PC && m == Reg::PC) {
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return UnpredictableInstruction();
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}
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// ADD <Rdn>, <Rm>
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auto result = ir.AddWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(0));
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if (d == Reg::PC) {
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ir.ALUWritePC(result.result);
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// Return to dispatch as we can't predict what PC is going to be. Stop compilation.
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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} else {
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ir.SetRegister(d, result.result);
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return true;
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}
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}
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bool thumb1_CMP_reg_t2(bool n_hi, Reg m, Reg n_lo) {
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Reg n = n_hi ? (n_lo + 8) : n_lo;
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if (n < Reg::R8 && m < Reg::R8) {
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return UnpredictableInstruction();
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} else if (n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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// CMP <Rn>, <Rm>
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auto result = ir.SubWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(1));
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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return true;
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}
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bool thumb1_MOV_reg(bool d_hi, Reg m, Reg d_lo) {
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Reg d = d_hi ? (d_lo + 8) : d_lo;
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// MOV <Rd>, <Rm>
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auto result = ir.GetRegister(m);
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if (d == Reg::PC) {
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ir.ALUWritePC(result);
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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} else {
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ir.SetRegister(d, result);
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return true;
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}
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}
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bool thumb1_LDR_literal(Reg t, Imm8 imm8) {
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u32 imm32 = imm8 << 2;
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// LDR <Rt>, <label>
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// Rt cannot encode R15.
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u32 address = ir.AlignPC(4) + imm32;
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auto data = ir.ReadMemory32(ir.Imm32(address));
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ir.SetRegister(t, data);
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return true;
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}
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bool thumb1_STR_reg(Reg m, Reg n, Reg t) {
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// STR <Rt>, [<Rn>, <Rm>]
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// Rt cannot encode R15.
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auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
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auto data = ir.GetRegister(t);
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ir.WriteMemory32(address, data);
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return true;
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}
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bool thumb1_STRH_reg(Reg m, Reg n, Reg t) {
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// STRH <Rt>, [<Rn>, <Rm>]
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// Rt cannot encode R15.
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auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
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auto data = ir.LeastSignificantHalf(ir.GetRegister(t));
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ir.WriteMemory16(address, data);
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return true;
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}
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bool thumb1_STRB_reg(Reg m, Reg n, Reg t) {
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// STRB <Rt>, [<Rn>, <Rm>]
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// Rt cannot encode R15.
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auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
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auto data = ir.LeastSignificantByte(ir.GetRegister(t));
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ir.WriteMemory8(address, data);
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return true;
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}
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bool thumb1_LDR_imm_t1(Imm5 imm5, Reg n, Reg t) {
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u32 imm32 = imm5 << 2;
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// LDR <Rt>, [<Rn>, #<imm>}
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// Rt cannot encode R15.
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auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
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auto data = ir.ReadMemory32(address);
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ir.SetRegister(t, data);
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return true;
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}
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bool thumb1_UDF() {
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return TranslateThisInstruction();
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}
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};
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enum class ThumbInstSize {
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Thumb16, Thumb32
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};
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static std::tuple<u32, ThumbInstSize> ReadThumbInstruction(u32 arm_pc, MemoryRead32FuncType memory_read_32) {
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u32 first_part = (*memory_read_32)(arm_pc & 0xFFFFFFFC);
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if ((arm_pc & 0x2) != 0)
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first_part >>= 16;
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first_part &= 0xFFFF;
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|
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if ((first_part & 0xF800) <= 0xE800) {
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// 16-bit thumb instruction
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return std::make_tuple(first_part, ThumbInstSize::Thumb16);
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}
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|
|
|
// 32-bit thumb instruction
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// These always start with 0b11101, 0b11110 or 0b11111.
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|
|
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u32 second_part = (*memory_read_32)((arm_pc+2) & 0xFFFFFFFC);
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if (((arm_pc+2) & 0x2) != 0)
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second_part >>= 16;
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|
second_part &= 0xFFFF;
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|
|
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return std::make_tuple(static_cast<u32>((first_part << 16) | second_part), ThumbInstSize::Thumb32);
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}
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|
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IR::Block TranslateThumb(LocationDescriptor descriptor, MemoryRead32FuncType memory_read_32) {
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|
TranslatorVisitor visitor{descriptor};
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|
|
|
bool should_continue = true;
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|
while (should_continue) {
|
|
const u32 arm_pc = visitor.ir.current_location.arm_pc;
|
|
|
|
u32 thumb_instruction;
|
|
ThumbInstSize inst_size;
|
|
std::tie(thumb_instruction, inst_size) = ReadThumbInstruction(arm_pc, memory_read_32);
|
|
|
|
if (inst_size == ThumbInstSize::Thumb16) {
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|
auto decoder = DecodeThumb16<TranslatorVisitor>(static_cast<u16>(thumb_instruction));
|
|
if (decoder) {
|
|
should_continue = decoder->call(visitor, static_cast<u16>(thumb_instruction));
|
|
} else {
|
|
should_continue = visitor.thumb1_UDF();
|
|
}
|
|
} else {
|
|
/*auto decoder = DecodeThumb2<TranslatorVisitor>(thumb_instruction);
|
|
if (decoder) {
|
|
should_continue = decoder->call(visitor, thumb_instruction);
|
|
} else {
|
|
should_continue = visitor.thumb2_UDF();
|
|
}*/
|
|
should_continue = visitor.TranslateThisInstruction();
|
|
}
|
|
|
|
visitor.ir.current_location.arm_pc += (inst_size == ThumbInstSize::Thumb16) ? 2 : 4;
|
|
visitor.ir.block.cycle_count++;
|
|
}
|
|
|
|
return visitor.ir.block;
|
|
}
|
|
|
|
} // namespace Arm
|
|
} // namepsace Dynarmic
|