464 lines
17 KiB
C++
464 lines
17 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <algorithm>
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#include <map>
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#include "backend_x64/reg_alloc.h"
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#include "common/assert.h"
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#include "common/x64/emitter.h"
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namespace Dynarmic {
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namespace BackendX64 {
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static Gen::OpArg ImmediateToOpArg(const IR::Value& imm) {
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switch (imm.GetType()) {
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case IR::Type::U1:
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return Gen::Imm32(imm.GetU1());
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break;
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case IR::Type::U8:
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return Gen::Imm32(imm.GetU8());
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break;
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case IR::Type::U32:
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return Gen::Imm32(imm.GetU32());
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break;
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default:
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ASSERT_MSG(false, "This should never happen.");
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}
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}
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static Gen::X64Reg HostLocToX64(HostLoc loc) {
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DEBUG_ASSERT(HostLocIsRegister(loc));
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// HostLoc is ordered such that the numbers line up.
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return static_cast<Gen::X64Reg>(loc);
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}
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static Gen::OpArg SpillToOpArg(HostLoc loc) {
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static_assert(std::is_same<decltype(JitState{}.Spill[0]), u64&>::value, "Spill must be u64");
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DEBUG_ASSERT(HostLocIsSpill(loc));
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size_t i = static_cast<size_t>(loc) - static_cast<size_t>(HostLoc::FirstSpill);
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return Gen::MDisp(Gen::R15, static_cast<int>(offsetof(JitState, Spill) + i * sizeof(u64)));
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}
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Gen::X64Reg RegAlloc::DefRegister(IR::Inst* def_inst, HostLocList desired_locations) {
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DEBUG_ASSERT(std::all_of(desired_locations.begin(), desired_locations.end(), HostLocIsRegister));
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DEBUG_ASSERT_MSG(!ValueLocations(def_inst), "def_inst has already been defined");
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HostLoc location = SelectARegister(desired_locations);
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if (IsRegisterOccupied(location)) {
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SpillRegister(location);
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}
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LocInfo(location).is_being_used = true;
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LocInfo(location).def = def_inst;
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DEBUG_ASSERT(LocInfo(location).IsDef());
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return HostLocToX64(location);
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}
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void RegAlloc::RegisterAddDef(IR::Inst* def_inst, const IR::Value& use_inst) {
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DEBUG_ASSERT_MSG(!ValueLocations(def_inst), "def_inst has already been defined");
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if (use_inst.IsImmediate()) {
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LoadImmediateIntoRegister(use_inst, DefRegister(def_inst, any_gpr));
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return;
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}
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DEBUG_ASSERT_MSG(ValueLocations(use_inst.GetInst()), "use_inst must already be defined");
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HostLoc location = *ValueLocation(use_inst.GetInst());
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LocInfo(location).values.emplace_back(def_inst);
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DecrementRemainingUses(use_inst.GetInst());
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DEBUG_ASSERT(LocInfo(location).IsIdle());
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}
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Gen::X64Reg RegAlloc::UseDefRegister(IR::Value use_value, IR::Inst* def_inst, HostLocList desired_locations) {
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if (!use_value.IsImmediate()) {
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return UseDefRegister(use_value.GetInst(), def_inst, desired_locations);
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}
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return LoadImmediateIntoRegister(use_value, DefRegister(def_inst, desired_locations));
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}
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Gen::X64Reg RegAlloc::UseDefRegister(IR::Inst* use_inst, IR::Inst* def_inst, HostLocList desired_locations) {
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DEBUG_ASSERT(std::all_of(desired_locations.begin(), desired_locations.end(), HostLocIsRegister));
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DEBUG_ASSERT_MSG(ValueLocation(def_inst), "def_inst has already been defined");
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DEBUG_ASSERT_MSG(!ValueLocation(use_inst), "use_inst has not been defined");
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if (IsLastUse(use_inst)) {
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HostLoc current_location = *ValueLocation(use_inst);
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auto& loc_info = LocInfo(current_location);
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if (!loc_info.IsIdle()) {
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loc_info.is_being_used = true;
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loc_info.def = def_inst;
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DEBUG_ASSERT(loc_info.IsUseDef());
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return HostLocToX64(current_location);
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}
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}
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Gen::X64Reg use_reg = UseRegister(use_inst, any_gpr);
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Gen::X64Reg def_reg = DefRegister(def_inst, desired_locations);
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code->MOV(64, Gen::R(def_reg), Gen::R(use_reg));
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return def_reg;
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}
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std::tuple<Gen::OpArg, Gen::X64Reg> RegAlloc::UseDefOpArg(IR::Value use_value, IR::Inst* def_inst, HostLocList desired_locations) {
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DEBUG_ASSERT(std::all_of(desired_locations.begin(), desired_locations.end(), HostLocIsRegister));
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DEBUG_ASSERT_MSG(ValueLocation(def_inst), "def_inst has already been defined");
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DEBUG_ASSERT_MSG(!ValueLocation(use_inst), "use_inst has not been defined");
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if (!use_value.IsImmediate()) {
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IR::Inst* use_inst = use_value.GetInst();
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if (IsLastUse(use_inst)) {
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HostLoc current_location = *ValueLocation(use_inst);
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auto& loc_info = LocInfo(current_location);
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if (!loc_info.IsIdle()) {
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loc_info.is_being_used = true;
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loc_info.def = def_inst;
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DEBUG_ASSERT(loc_info.IsUseDef());
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return std::make_tuple(Gen::R(HostLocToX64(current_location)), HostLocToX64(current_location));
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}
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}
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}
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Gen::OpArg use_oparg = UseOpArg(use_value, any_gpr);
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Gen::X64Reg def_reg = DefRegister(def_inst, desired_locations);
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return std::make_tuple(use_oparg, def_reg);
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}
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Gen::X64Reg RegAlloc::UseRegister(IR::Value use_value, HostLocList desired_locations) {
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if (!use_value.IsImmediate()) {
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return UseRegister(use_value.GetInst(), desired_locations);
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}
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return LoadImmediateIntoRegister(use_value, ScratchRegister(desired_locations));
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}
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Gen::X64Reg RegAlloc::UseRegister(IR::Inst* use_inst, HostLocList desired_locations) {
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HostLoc current_location;
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bool was_being_used;
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std::tie(current_location, was_being_used) = UseHostLoc(use_inst, desired_locations);
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if (HostLocIsRegister(current_location)) {
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return HostLocToX64(current_location);
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} else if (HostLocIsSpill(current_location)) {
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HostLoc new_location = SelectARegister(desired_locations);
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if (IsRegisterOccupied(new_location)) {
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SpillRegister(new_location);
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}
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EmitMove(new_location, current_location);
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if (!was_being_used) {
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LocInfo(new_location) = LocInfo(current_location);
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LocInfo(current_location) = {};
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DEBUG_ASSERT(LocInfo(new_location).IsUse());
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} else {
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LocInfo(new_location).is_being_used = true;
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DEBUG_ASSERT(LocInfo(new_location).IsScratch());
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}
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return HostLocToX64(new_location);
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}
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ASSERT_MSG(false, "Unknown current_location type");
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return Gen::INVALID_REG;
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}
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Gen::OpArg RegAlloc::UseOpArg(IR::Value use_value, HostLocList desired_locations) {
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if (use_value.IsImmediate()) {
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return ImmediateToOpArg(use_value);
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}
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IR::Inst* use_inst = use_value.GetInst();
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HostLoc current_location;
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bool was_being_used;
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std::tie(current_location, was_being_used) = UseHostLoc(use_inst, desired_locations);
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if (HostLocIsRegister(current_location)) {
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return Gen::R(HostLocToX64(current_location));
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} else if (HostLocIsSpill(current_location)) {
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return SpillToOpArg(current_location);
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}
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ASSERT_MSG(false, "Unknown current_location type");
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return Gen::R(Gen::INVALID_REG);
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}
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Gen::X64Reg RegAlloc::UseScratchRegister(IR::Value use_value, HostLocList desired_locations) {
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if (!use_value.IsImmediate()) {
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return UseScratchRegister(use_value.GetInst(), desired_locations);
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}
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return LoadImmediateIntoRegister(use_value, ScratchRegister(desired_locations));
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}
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Gen::X64Reg RegAlloc::UseScratchRegister(IR::Inst* use_inst, HostLocList desired_locations) {
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DEBUG_ASSERT(std::all_of(desired_locations.begin(), desired_locations.end(), HostLocIsRegister));
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DEBUG_ASSERT_MSG(ValueLocation(use_inst), "use_inst has not been defined");
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ASSERT_MSG(use_inst->use_count != 0, "use_inst ran out of uses. (Use-d an IR::Inst* too many times)");
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HostLoc current_location = *ValueLocation(use_inst);
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HostLoc new_location = SelectARegister(desired_locations);
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if (IsRegisterOccupied(new_location)) {
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SpillRegister(new_location);
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}
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if (HostLocIsSpill(current_location)) {
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EmitMove(new_location, current_location);
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LocInfo(new_location).is_being_used = true;
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DecrementRemainingUses(use_inst);
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DEBUG_ASSERT(LocInfo(new_location).IsScratch());
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return HostLocToX64(new_location);
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} else if (HostLocIsRegister(current_location)) {
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ASSERT(LocInfo(current_location).IsIdle());
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if (current_location != new_location) {
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EmitMove(new_location, current_location);
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}
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LocInfo(new_location).is_being_used = true;
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LocInfo(new_location).values.clear();
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DecrementRemainingUses(use_inst);
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DEBUG_ASSERT(LocInfo(new_location).IsScratch());
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return HostLocToX64(new_location);
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}
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ASSERT_MSG(0, "Invalid current_location");
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return Gen::INVALID_REG;
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}
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Gen::X64Reg RegAlloc::ScratchRegister(HostLocList desired_locations) {
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DEBUG_ASSERT(std::all_of(desired_locations.begin(), desired_locations.end(), HostLocIsRegister));
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HostLoc location = SelectARegister(desired_locations);
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if (IsRegisterOccupied(location)) {
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SpillRegister(location);
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}
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// Update state
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LocInfo(location).is_being_used = true;
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DEBUG_ASSERT(LocInfo(location).IsScratch());
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return HostLocToX64(location);
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}
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void RegAlloc::HostCall(IR::Inst* result_def, IR::Value arg0_use, IR::Value arg1_use, IR::Value arg2_use, IR::Value arg3_use) {
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constexpr HostLoc AbiReturn = HostLoc::RAX;
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#ifdef _WIN32
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constexpr std::array<HostLoc, 4> AbiArgs = { HostLoc::RCX, HostLoc::RDX, HostLoc::R8, HostLoc::R9 };
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/// Caller-saved registers other than AbiReturn or AbiArgs
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constexpr std::array<HostLoc, 2> OtherCallerSave = { HostLoc::R10, HostLoc::R11 };
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#else
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constexpr std::array<HostLoc, 4> AbiArgs = { HostLoc::RDI, HostLoc::RSI, HostLoc::RDX, HostLoc::RCX };
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/// Caller-saved registers other than AbiReturn or AbiArgs
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constexpr std::array<HostLoc, 4> OtherCallerSave = { HostLoc::R8, HostLoc::R9, HostLoc::R10, HostLoc::R11 };
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#endif
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const std::array<IR::Value*, 4> args = {&arg0_use, &arg1_use, &arg2_use, &arg3_use};
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// TODO: This works but almost certainly leads to suboptimal generated code.
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for (HostLoc caller_save : OtherCallerSave) {
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ScratchRegister({caller_save});
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}
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if (result_def) {
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DefRegister(result_def, {AbiReturn});
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} else {
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ScratchRegister({AbiReturn});
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}
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for (size_t i = 0; i < AbiArgs.size(); i++) {
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if (!args[i]->IsEmpty()) {
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UseScratchRegister(*args[i], {AbiArgs[i]});
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} else {
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ScratchRegister({AbiArgs[i]});
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}
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}
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ScratchRegister({HostLoc::RSP});
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code->MOV(64, Gen::R(Gen::RSP), Gen::MDisp(Gen::R15, offsetof(JitState, save_host_RSP)));
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}
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HostLoc RegAlloc::SelectARegister(HostLocList desired_locations) const {
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std::vector<HostLoc> candidates = desired_locations;
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// Find all locations that have not been allocated..
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auto allocated_locs = std::partition(candidates.begin(), candidates.end(), [this](auto loc){
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return !this->IsRegisterAllocated(loc);
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});
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candidates.erase(allocated_locs, candidates.end());
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ASSERT_MSG(!candidates.empty(), "All candidate registers have already been allocated");
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// Selects the best location out of the available locations.
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// TODO: Actually do LRU or something. Currently we just try to pick something without a value if possible.
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std::partition(candidates.begin(), candidates.end(), [this](auto loc){
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return !this->IsRegisterOccupied(loc);
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});
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return candidates.front();
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}
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boost::optional<HostLoc> RegAlloc::ValueLocation(IR::Inst* value) const {
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for (size_t i = 0; i < HostLocCount; i++)
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for (IR::Inst* v : hostloc_info[i].values)
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if (v == value)
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return {static_cast<HostLoc>(i)};
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return {};
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}
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bool RegAlloc::IsRegisterOccupied(HostLoc loc) const {
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return !GetLocInfo(loc).values.empty() || GetLocInfo(loc).def;
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}
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bool RegAlloc::IsRegisterAllocated(HostLoc loc) const {
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return GetLocInfo(loc).is_being_used;
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}
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bool RegAlloc::IsLastUse(IR::Inst* inst) const {
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if (inst->use_count > 1)
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return false;
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return GetLocInfo(*ValueLocation(inst)).values.size() == 1;
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}
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void RegAlloc::SpillRegister(HostLoc loc) {
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ASSERT_MSG(HostLocIsRegister(loc), "Only registers can be spilled");
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ASSERT_MSG(IsRegisterOccupied(loc), "There is no need to spill unoccupied registers");
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ASSERT_MSG(!IsRegisterAllocated(loc), "Registers that have been allocated must not be spilt");
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HostLoc new_loc = FindFreeSpill();
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EmitMove(new_loc, loc);
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LocInfo(new_loc) = LocInfo(loc);
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LocInfo(loc) = {};
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}
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HostLoc RegAlloc::FindFreeSpill() const {
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for (size_t i = 0; i < SpillCount; i++)
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if (!IsRegisterOccupied(HostLocSpill(i)))
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return HostLocSpill(i);
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ASSERT_MSG(0, "All spill locations are full");
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}
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void RegAlloc::EndOfAllocScope() {
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for (auto& iter : hostloc_info) {
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iter.is_being_used = false;
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if (iter.def) {
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iter.values.clear();
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iter.values.emplace_back(iter.def);
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iter.def = nullptr;
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} else if (!iter.values.empty()) {
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auto to_erase = std::remove_if(iter.values.begin(), iter.values.end(),
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[](const auto& inst){ return inst->use_count <= 0; });
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iter.values.erase(to_erase, iter.values.end());
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}
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}
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}
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void RegAlloc::DecrementRemainingUses(IR::Inst* value) {
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ASSERT_MSG(value->use_count > 0, "value doesn't have any remaining uses");
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value->use_count--;
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}
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void RegAlloc::AssertNoMoreUses() {
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ASSERT(std::all_of(hostloc_info.begin(), hostloc_info.end(), [](const auto& i){ return i.values.empty(); }));
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}
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void RegAlloc::Reset() {
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hostloc_info.fill({});
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}
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void RegAlloc::EmitMove(HostLoc to, HostLoc from) {
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if (HostLocIsXMM(to) && HostLocIsSpill(from)) {
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code->MOVSD(HostLocToX64(to), SpillToOpArg(from));
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} else if (HostLocIsSpill(to) && HostLocIsXMM(from)) {
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code->MOVSD(HostLocToX64(to), SpillToOpArg(from));
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} else if (HostLocIsXMM(to) && HostLocIsXMM(from)) {
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code->MOVAPS(HostLocToX64(to), Gen::R(HostLocToX64(from)));
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} else if (HostLocIsGPR(to) && HostLocIsSpill(from)) {
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code->MOV(64, Gen::R(HostLocToX64(to)), SpillToOpArg(from));
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} else if (HostLocIsSpill(to) && HostLocIsGPR(from)) {
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code->MOV(64, SpillToOpArg(to), Gen::R(HostLocToX64(from)));
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} else if (HostLocIsGPR(to) && HostLocIsGPR(from)){
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code->MOV(64, Gen::R(HostLocToX64(to)), Gen::R(HostLocToX64(from)));
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} else {
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ASSERT_MSG(false, "Invalid RegAlloc::EmitMove");
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}
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}
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void RegAlloc::EmitExchange(HostLoc a, HostLoc b) {
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if (HostLocIsGPR(a) && HostLocIsGPR(b)) {
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code->XCHG(64, Gen::R(HostLocToX64(a)), Gen::R(HostLocToX64(b)));
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} else if (HostLocIsXMM(a) && HostLocIsXMM(b)) {
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ASSERT_MSG(false, "Exchange is unnecessary for XMM registers");
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} else {
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ASSERT_MSG(false, "Invalid RegAlloc::EmitExchange");
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}
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}
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std::tuple<HostLoc, bool> RegAlloc::UseHostLoc(IR::Inst* use_inst, HostLocList desired_locations) {
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DEBUG_ASSERT(std::all_of(desired_locations.begin(), desired_locations.end(), HostLocIsRegister));
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DEBUG_ASSERT_MSG(ValueLocation(use_inst), "use_inst has not been defined");
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HostLoc current_location = *ValueLocation(use_inst);
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auto iter = std::find(desired_locations.begin(), desired_locations.end(), current_location);
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if (iter != desired_locations.end()) {
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if (LocInfo(current_location).IsDef()) {
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HostLoc new_location = SelectARegister(desired_locations);
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if (IsRegisterOccupied(new_location)) {
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SpillRegister(new_location);
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}
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EmitMove(new_location, current_location);
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LocInfo(new_location).is_being_used = true;
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LocInfo(new_location).values.emplace_back(use_inst);
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DecrementRemainingUses(use_inst);
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DEBUG_ASSERT(LocInfo(new_location).IsUse());
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return std::make_tuple(new_location, false);
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} else {
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bool was_being_used = LocInfo(current_location).is_being_used;
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ASSERT(LocInfo(current_location).IsUse() || LocInfo(current_location).IsIdle());
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LocInfo(current_location).is_being_used = true;
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DecrementRemainingUses(use_inst);
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DEBUG_ASSERT(LocInfo(new_location).IsUse());
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return std::make_tuple(current_location, was_being_used);
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}
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}
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if (HostLocIsSpill(current_location)) {
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bool was_being_used = LocInfo(current_location).is_being_used;
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LocInfo(current_location).is_being_used = true;
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DecrementRemainingUses(use_inst);
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DEBUG_ASSERT(LocInfo(current_location).IsUse());
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return std::make_tuple(current_location, was_being_used);
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} else if (HostLocIsRegister(current_location)) {
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HostLoc new_location = SelectARegister(desired_locations);
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ASSERT(LocInfo(current_location).IsIdle());
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EmitExchange(new_location, current_location);
|
|
std::swap(LocInfo(new_location), LocInfo(current_location));
|
|
LocInfo(new_location).is_being_used = true;
|
|
DecrementRemainingUses(use_inst);
|
|
DEBUG_ASSERT(LocInfo(new_location).IsUse());
|
|
return std::make_tuple(new_location, false);
|
|
}
|
|
|
|
ASSERT_MSG(0, "Invalid current_location");
|
|
return std::make_tuple(static_cast<HostLoc>(-1), false);
|
|
}
|
|
|
|
Gen::X64Reg RegAlloc::LoadImmediateIntoRegister(IR::Value imm, Gen::X64Reg reg) {
|
|
ASSERT_MSG(imm.IsImmediate(), "imm is not an immediate");
|
|
code->MOV(32, Gen::R(reg), ImmediateToOpArg(imm));
|
|
return reg;
|
|
}
|
|
|
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} // namespace BackendX64
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} // namespace Dynarmic
|