307 lines
16 KiB
C++
307 lines
16 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#pragma once
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#include "frontend/ir/ir_emitter.h"
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namespace Dynarmic {
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namespace Arm {
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enum class ConditionalState {
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/// We haven't met any conditional instructions yet.
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None,
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/// Current instruction is a conditional. This marks the end of this basic block.
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Break,
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/// This basic block is made up solely of conditional instructions.
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Translating,
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};
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struct ArmTranslatorVisitor final {
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explicit ArmTranslatorVisitor(LocationDescriptor descriptor) : ir(descriptor) {
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ASSERT_MSG(!descriptor.TFlag(), "The processor must be in Arm mode");
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}
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IREmitter ir;
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ConditionalState cond_state = ConditionalState::None;
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bool ConditionPassed(Cond cond);
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bool InterpretThisInstruction();
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bool UnpredictableInstruction();
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bool LinkToNextInstruction();
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static u32 rotr(u32 x, int shift) {
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shift &= 31;
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if (!shift) return x;
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return (x >> shift) | (x << (32 - shift));
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}
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static u32 ArmExpandImm(int rotate, Imm8 imm8) {
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return rotr(static_cast<u32>(imm8), rotate*2);
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}
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struct ImmAndCarry {
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u32 imm32;
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IR::Value carry;
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};
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ImmAndCarry ArmExpandImm_C(int rotate, u32 imm8, IR::Value carry_in) {
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u32 imm32 = imm8;
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auto carry_out = carry_in;
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if (rotate) {
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imm32 = rotr(imm8, rotate * 2);
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carry_out = ir.Imm1(imm32 >> 31 == 1);
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}
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return {imm32, carry_out};
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}
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IREmitter::ResultAndCarry EmitImmShift(IR::Value value, ShiftType type, Imm5 imm5, IR::Value carry_in);
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IREmitter::ResultAndCarry EmitRegShift(IR::Value value, ShiftType type, IR::Value amount, IR::Value carry_in);
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IR::Value SignZeroExtendRor(Reg m, SignExtendRotation rotate);
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// Branch instructions
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bool arm_B(Cond cond, Imm24 imm24);
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bool arm_BL(Cond cond, Imm24 imm24);
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bool arm_BLX_imm(Cond cond, Imm24 imm24);
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bool arm_BLX_reg(Cond cond, Reg m);
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bool arm_BX(Cond cond, Reg m);
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bool arm_BXJ(Cond cond, Reg m);
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// Data processing instructions
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bool arm_ADC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
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bool arm_ADC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_ADC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
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bool arm_ADD_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
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bool arm_ADD_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_ADD_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
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bool arm_AND_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
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bool arm_AND_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_AND_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
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bool arm_BIC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
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bool arm_BIC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_BIC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
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bool arm_CMN_imm(Cond cond, Reg n, int rotate, Imm8 imm8);
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bool arm_CMN_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_CMN_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m);
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bool arm_CMP_imm(Cond cond, Reg n, int rotate, Imm8 imm8);
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bool arm_CMP_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_CMP_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m);
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bool arm_EOR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
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bool arm_EOR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_EOR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
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bool arm_MOV_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8);
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bool arm_MOV_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_MOV_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m);
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bool arm_MVN_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8);
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bool arm_MVN_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_MVN_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m);
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bool arm_ORR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
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bool arm_ORR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_ORR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
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bool arm_RSB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
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bool arm_RSB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_RSB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
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bool arm_RSC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
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bool arm_RSC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_RSC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
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bool arm_SBC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
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bool arm_SBC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_SBC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
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bool arm_SUB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
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bool arm_SUB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_SUB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
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bool arm_TEQ_imm(Cond cond, Reg n, int rotate, Imm8 imm8);
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bool arm_TEQ_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_TEQ_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m);
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bool arm_TST_imm(Cond cond, Reg n, int rotate, Imm8 imm8);
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bool arm_TST_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_TST_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m);
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// Exception generating instructions
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bool arm_BKPT(Cond cond, Imm12 imm12, Imm4 imm4);
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bool arm_SVC(Cond cond, Imm24 imm24);
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bool arm_UDF();
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// Extension instructions
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bool arm_SXTAB(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m);
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bool arm_SXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m);
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bool arm_SXTAH(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m);
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bool arm_SXTB(Cond cond, Reg d, SignExtendRotation rotate, Reg m);
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bool arm_SXTB16(Cond cond, Reg d, SignExtendRotation rotate, Reg m);
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bool arm_SXTH(Cond cond, Reg d, SignExtendRotation rotate, Reg m);
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bool arm_UXTAB(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m);
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bool arm_UXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m);
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bool arm_UXTAH(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m);
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bool arm_UXTB(Cond cond, Reg d, SignExtendRotation rotate, Reg m);
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bool arm_UXTB16(Cond cond, Reg d, SignExtendRotation rotate, Reg m);
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bool arm_UXTH(Cond cond, Reg d, SignExtendRotation rotate, Reg m);
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// Load/Store instructions
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bool arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm12 imm12);
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bool arm_LDR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_LDRB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm12 imm12);
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bool arm_LDRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_LDRBT();
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bool arm_LDRD_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b);
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bool arm_LDRD_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m);
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bool arm_LDRH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b);
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bool arm_LDRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m);
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bool arm_LDRHT();
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bool arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b);
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bool arm_LDRSB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m);
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bool arm_LDRSBT();
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bool arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b);
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bool arm_LDRSH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m);
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bool arm_LDRSHT();
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bool arm_LDRT();
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bool arm_STR_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm12 imm12);
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bool arm_STR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_STRB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm12 imm12);
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bool arm_STRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
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bool arm_STRBT();
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bool arm_STRD_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b);
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bool arm_STRD_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m);
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bool arm_STRH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b);
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bool arm_STRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m);
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bool arm_STRHT();
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bool arm_STRT();
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// Load/Store multiple instructions
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bool arm_LDM(Cond cond, bool P, bool U, bool W, Reg n, RegList list);
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bool arm_LDM_usr();
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bool arm_LDM_eret();
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bool arm_STM(Cond cond, bool P, bool U, bool W, Reg n, RegList list);
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bool arm_STM_usr();
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// Miscellaneous instructions
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bool arm_CLZ(Cond cond, Reg d, Reg m) { return InterpretThisInstruction(); }
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bool arm_NOP() { return InterpretThisInstruction(); }
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bool arm_SEL(Cond cond, Reg n, Reg d, Reg m) { return InterpretThisInstruction(); }
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// Unsigned sum of absolute difference functions
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bool arm_USAD8(Cond cond, Reg d, Reg m, Reg n) { return InterpretThisInstruction(); }
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bool arm_USADA8(Cond cond, Reg d, Reg a, Reg m, Reg n) { return InterpretThisInstruction(); }
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// Packing instructions
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bool arm_PKHBT(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m) { return InterpretThisInstruction(); }
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bool arm_PKHTB(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m) { return InterpretThisInstruction(); }
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// Reversal instructions
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bool arm_REV(Cond cond, Reg d, Reg m);
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bool arm_REV16(Cond cond, Reg d, Reg m);
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bool arm_REVSH(Cond cond, Reg d, Reg m);
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// Saturation instructions
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bool arm_SSAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) { return InterpretThisInstruction(); }
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bool arm_SSAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n) { return InterpretThisInstruction(); }
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bool arm_USAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) { return InterpretThisInstruction(); }
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bool arm_USAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n) { return InterpretThisInstruction(); }
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// Multiply (Normal) instructions
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bool arm_MLA(Cond cond, bool S, Reg d, Reg a, Reg m, Reg n);
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bool arm_MUL(Cond cond, bool S, Reg d, Reg m, Reg n);
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// Multiply (Long) instructions
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bool arm_SMLAL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n);
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bool arm_SMULL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n);
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bool arm_UMAAL(Cond cond, Reg dHi, Reg dLo, Reg m, Reg n);
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bool arm_UMLAL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n);
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bool arm_UMULL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n);
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// Multiply (Halfword) instructions
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bool arm_SMLALxy(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, bool N, Reg n);
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bool arm_SMLAxy(Cond cond, Reg d, Reg a, Reg m, bool M, bool N, Reg n);
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bool arm_SMULxy(Cond cond, Reg d, Reg m, bool M, bool N, Reg n);
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// Multiply (word by halfword) instructions
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bool arm_SMLAWy(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n);
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bool arm_SMULWy(Cond cond, Reg d, Reg m, bool M, Reg n);
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// Multiply (Most significant word) instructions
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bool arm_SMMLA(Cond cond, Reg d, Reg a, Reg m, bool R, Reg n);
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bool arm_SMMLS(Cond cond, Reg d, Reg a, Reg m, bool R, Reg n);
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bool arm_SMMUL(Cond cond, Reg d, Reg m, bool R, Reg n);
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// Multiply (Dual) instructions
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bool arm_SMLAD(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n);
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bool arm_SMLALD(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, Reg n);
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bool arm_SMLSD(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n);
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bool arm_SMLSLD(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, Reg n);
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bool arm_SMUAD(Cond cond, Reg d, Reg m, bool M, Reg n);
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bool arm_SMUSD(Cond cond, Reg d, Reg m, bool M, Reg n);
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// Parallel Add/Subtract (Modulo arithmetic) instructions
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bool arm_SADD8(Cond cond, Reg n, Reg d, Reg m);
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bool arm_SADD16(Cond cond, Reg n, Reg d, Reg m);
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bool arm_SASX(Cond cond, Reg n, Reg d, Reg m);
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bool arm_SSAX(Cond cond, Reg n, Reg d, Reg m);
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bool arm_SSUB8(Cond cond, Reg n, Reg d, Reg m);
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bool arm_SSUB16(Cond cond, Reg n, Reg d, Reg m);
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bool arm_UADD8(Cond cond, Reg n, Reg d, Reg m);
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bool arm_UADD16(Cond cond, Reg n, Reg d, Reg m);
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bool arm_UASX(Cond cond, Reg n, Reg d, Reg m);
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bool arm_USAX(Cond cond, Reg n, Reg d, Reg m);
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bool arm_USUB8(Cond cond, Reg n, Reg d, Reg m);
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bool arm_USUB16(Cond cond, Reg n, Reg d, Reg m);
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// Parallel Add/Subtract (Saturating) instructions
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bool arm_QADD8(Cond cond, Reg n, Reg d, Reg m);
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bool arm_QADD16(Cond cond, Reg n, Reg d, Reg m);
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bool arm_QASX(Cond cond, Reg n, Reg d, Reg m);
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bool arm_QSAX(Cond cond, Reg n, Reg d, Reg m);
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bool arm_QSUB8(Cond cond, Reg n, Reg d, Reg m);
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bool arm_QSUB16(Cond cond, Reg n, Reg d, Reg m);
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bool arm_UQADD8(Cond cond, Reg n, Reg d, Reg m);
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bool arm_UQADD16(Cond cond, Reg n, Reg d, Reg m);
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bool arm_UQASX(Cond cond, Reg n, Reg d, Reg m);
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bool arm_UQSAX(Cond cond, Reg n, Reg d, Reg m);
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bool arm_UQSUB8(Cond cond, Reg n, Reg d, Reg m);
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bool arm_UQSUB16(Cond cond, Reg n, Reg d, Reg m);
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// Parallel Add/Subtract (Halving) instructions
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bool arm_SHADD8(Cond cond, Reg n, Reg d, Reg m);
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bool arm_SHADD16(Cond cond, Reg n, Reg d, Reg m);
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bool arm_SHASX(Cond cond, Reg n, Reg d, Reg m);
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bool arm_SHSAX(Cond cond, Reg n, Reg d, Reg m);
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bool arm_SHSUB8(Cond cond, Reg n, Reg d, Reg m);
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bool arm_SHSUB16(Cond cond, Reg n, Reg d, Reg m);
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bool arm_UHADD8(Cond cond, Reg n, Reg d, Reg m);
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bool arm_UHADD16(Cond cond, Reg n, Reg d, Reg m);
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bool arm_UHASX(Cond cond, Reg n, Reg d, Reg m);
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bool arm_UHSAX(Cond cond, Reg n, Reg d, Reg m);
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bool arm_UHSUB8(Cond cond, Reg n, Reg d, Reg m);
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bool arm_UHSUB16(Cond cond, Reg n, Reg d, Reg m);
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// Saturated Add/Subtract instructions
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bool arm_QADD(Cond cond, Reg n, Reg d, Reg m) { return InterpretThisInstruction(); }
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bool arm_QSUB(Cond cond, Reg n, Reg d, Reg m) { return InterpretThisInstruction(); }
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bool arm_QDADD(Cond cond, Reg n, Reg d, Reg m) { return InterpretThisInstruction(); }
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bool arm_QDSUB(Cond cond, Reg n, Reg d, Reg m) { return InterpretThisInstruction(); }
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// Synchronization Primitive instructions
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bool arm_CLREX() { return InterpretThisInstruction(); }
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bool arm_LDREX(Cond cond, Reg n, Reg d) { return InterpretThisInstruction(); }
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bool arm_LDREXB(Cond cond, Reg n, Reg d) { return InterpretThisInstruction(); }
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bool arm_LDREXD(Cond cond, Reg n, Reg d) { return InterpretThisInstruction(); }
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bool arm_LDREXH(Cond cond, Reg n, Reg d) { return InterpretThisInstruction(); }
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bool arm_STREX(Cond cond, Reg n, Reg d, Reg m) { return InterpretThisInstruction(); }
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bool arm_STREXB(Cond cond, Reg n, Reg d, Reg m) { return InterpretThisInstruction(); }
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bool arm_STREXD(Cond cond, Reg n, Reg d, Reg m) { return InterpretThisInstruction(); }
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bool arm_STREXH(Cond cond, Reg n, Reg d, Reg m) { return InterpretThisInstruction(); }
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bool arm_SWP(Cond cond, Reg n, Reg d, Reg m) { return InterpretThisInstruction(); }
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bool arm_SWPB(Cond cond, Reg n, Reg d, Reg m) { return InterpretThisInstruction(); }
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// Status register access instructions
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bool arm_CPS() { return InterpretThisInstruction(); }
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bool arm_MRS() { return InterpretThisInstruction(); }
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bool arm_MSR() { return InterpretThisInstruction(); }
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bool arm_RFE() { return InterpretThisInstruction(); }
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bool arm_SETEND(bool E) { return InterpretThisInstruction(); }
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bool arm_SRS() { return InterpretThisInstruction(); }
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};
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} // namespace Arm
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} // namespace Dynarmic
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