MerryMage dca3b2f079 Implement VMRS and VMSR		2016-08-26 22:47:54 +01:00
..
branch.cpp	translate_arm/branch: Read-after-write in arm_BLX_reg	2016-08-22 15:53:56 +01:00
data_processing.cpp	translate_arm/data_processing: Rd == R15 is unpredictable for rsr instructions	2016-08-18 18:23:05 +01:00
exception_generating.cpp	Optimization: Make SVC use RSB	2016-08-15 15:02:08 +01:00
extension.cpp	Standardize indentation of switch statments	2016-08-23 12:19:27 +01:00
load_store.cpp	ir_emitter: Should be in the IR namespace, not the Arm namespace	2016-08-25 17:36:42 +01:00
multiply.cpp	TranlateArm: implement remaining multiplies	2016-08-19 01:08:38 +01:00
parallel.cpp	translate_arm/parallel: Detect UNPREDICTABLE instructions	2016-08-19 00:59:07 +01:00
reversal.cpp	Implement more instructions	2016-08-03 00:47:17 +01:00
status_register_access.cpp	TranslateArm: Implement MRS, MSR (imm), MSR (reg)	2016-08-15 11:50:49 +01:00
synchronization.cpp	TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB	2016-08-09 22:57:20 +01:00
translate_arm.h	Implement VMRS and VMSR	2016-08-26 22:47:54 +01:00
vfp2.cpp	Implement VMRS and VMSR	2016-08-26 22:47:54 +01:00