235 lines
7.5 KiB
C++
235 lines
7.5 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "translate_arm.h"
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namespace Dynarmic {
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namespace Arm {
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static IR::Value GetAddressingMode(IREmitter& ir, bool P, bool U, bool W, Reg n, IR::Value index) {
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IR::Value address;
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if (P) {
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// Pre-indexed addressing
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if (n == Reg::PC && index.IsImmediate()) {
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address = U ? ir.Imm32(ir.AlignPC(4) + index.GetU32()) : ir.Imm32(ir.AlignPC(4) - index.GetU32());
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} else {
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address = U ? ir.Add(ir.GetRegister(n), index) : ir.Sub(ir.GetRegister(n), index);
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}
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// Wrote calculated address back to the base register
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if (W) {
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ir.SetRegister(n, address);
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}
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} else {
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// Post-indexed addressing
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address = (n == Reg::PC) ? ir.Imm32(ir.AlignPC(4)) : ir.GetRegister(n);
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if (U) {
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ir.SetRegister(n, ir.Add(ir.GetRegister(n), index));
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} else {
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ir.SetRegister(n, ir.Sub(ir.GetRegister(n), index));
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}
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// TODO(bunnei): Handle W=1 mode, which in this scenario does an unprivileged (User mode) access.
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}
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return address;
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}
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bool ArmTranslatorVisitor::arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm12 imm12) {
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if (ConditionPassed(cond)) {
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const auto data = ir.ReadMemory32(GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm12)));
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if (d == Reg::PC) {
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ir.BXWritePC(data);
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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ir.SetRegister(d, data);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_LDR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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if (ConditionPassed(cond)) {
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const auto shifted = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag());
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const auto data = ir.ReadMemory32(GetAddressingMode(ir, P, U, W, n, shifted.result));
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if (d == Reg::PC) {
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ir.BXWritePC(data);
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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ir.SetRegister(d, data);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_LDRB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm12 imm12) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDRBT() {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDRD_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDRD_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDRH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDRHT() {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDRSB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDRSBT() {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDRSH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDRSHT() {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDRT() {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_STR_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm12 imm12) {
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if (ConditionPassed(cond)) {
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const auto address = GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm12));
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ir.WriteMemory32(address, ir.GetRegister(d));
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_STR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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if (ConditionPassed(cond)) {
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const auto shifted = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag());
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const auto address = GetAddressingMode(ir, P, U, W, n, shifted.result);
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ir.WriteMemory32(address, ir.GetRegister(d));
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_STRB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm12 imm12) {
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if (ConditionPassed(cond)) {
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const auto address = GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm12));
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const auto value = (d == Reg::PC) ? ir.Imm8(ir.PC() - 8) : ir.GetRegister(d);
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ir.WriteMemory8(address, value);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_STRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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if (ConditionPassed(cond)) {
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const auto shifted = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag());
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const auto address = GetAddressingMode(ir, P, U, W, n, shifted.result);
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const auto value = (d == Reg::PC) ? ir.Imm8(ir.PC() - 8) : ir.GetRegister(d);
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ir.WriteMemory8(address, value);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_STRBT() {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_STRD_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_STRD_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_STRH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm4 imm8a, Imm4 imm8b) {
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if (ConditionPassed(cond)) {
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const auto address = GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm8a << 4 | imm8b));
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const auto value = (d == Reg::PC) ? ir.Imm32(ir.PC() - 8) : ir.GetRegister(d);
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ir.WriteMemory16(address, value);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_STRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Reg m) {
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if (ConditionPassed(cond)) {
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const auto address = GetAddressingMode(ir, P, U, W, n, ir.GetRegister(m));
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const auto value = (d == Reg::PC) ? ir.Imm32(ir.PC() - 8) : ir.GetRegister(d);
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ir.WriteMemory16(address, value);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_STRHT() {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_STRT() {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDM(Cond cond, bool P, bool U, bool W, Reg n, RegList list) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDM_usr() {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_LDM_eret() {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_STM(Cond cond, bool P, bool U, bool W, Reg n, RegList list) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_STM_usr() {
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return InterpretThisInstruction();
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}
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} // namespace Arm
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} // namespace Dynarmic
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