201 lines
8.2 KiB
C++
201 lines
8.2 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <algorithm>
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#include <cstring>
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#include <string>
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#include <vector>
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#include <catch.hpp>
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#include "common/llvm_disassemble.h"
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#include "common/scope_exit.h"
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#include "frontend/A64/location_descriptor.h"
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#include "frontend/A64/translate/translate.h"
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#include "frontend/ir/basic_block.h"
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#include "frontend/ir/opcodes.h"
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#include "inst_gen.h"
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#include "rand_int.h"
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#include "testenv.h"
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#include "unicorn_emu/unicorn.h"
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// Needs to be declaerd before <fmt/ostream.h>
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static std::ostream& operator<<(std::ostream& o, const Dynarmic::A64::Vector& vec) {
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return o << fmt::format("{:016x}'{:016x}", vec[1], vec[0]);
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}
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#include <fmt/format.h>
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#include <fmt/ostream.h>
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using namespace Dynarmic;
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static Vector RandomVector() {
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return {RandInt<u64>(0, ~u64(0)), RandInt<u64>(0, ~u64(0))};
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}
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static u32 GenRandomInst(u64 pc, bool is_last_inst) {
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static const std::vector<InstructionGenerator> instruction_generators = []{
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const std::vector<std::tuple<const char*, const char*>> list {
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#define INST(fn, name, bitstring) {#fn, bitstring},
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#include "frontend/A64/decoder/a64.inc"
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#undef INST
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};
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std::vector<InstructionGenerator> result;
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// List of instructions not to test
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const std::vector<std::string> do_not_test {
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// Unallocated encodings are invalid.
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"UnallocatedEncoding",
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// Unimplemented in QEMU
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"STLLR",
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// Unimplemented in QEMU
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"LDLAR",
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// Dynarmic and QEMU currently differ on how the exclusive monitor's address range works.
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"STXR", "STLXR", "STXP", "STLXP", "LDXR", "LDAXR", "LDXP", "LDAXP",
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};
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for (const auto& [fn, bitstring] : list) {
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if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
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InstructionGenerator::AddInvalidInstruction(bitstring);
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continue;
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}
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result.emplace_back(InstructionGenerator{bitstring});
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}
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// Manually added exceptions:
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// FMOV_float_imm for half-precision floats (QEMU doesn't have half-precision support yet).
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InstructionGenerator::AddInvalidInstruction("00011110111iiiiiiii10000000ddddd");
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return result;
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}();
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const A64::LocationDescriptor location{pc, {}};
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restart:
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const size_t index = RandInt<size_t>(0, instruction_generators.size() - 1);
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const u32 instruction = instruction_generators[index].Generate();
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IR::Block block{location};
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bool should_continue = A64::TranslateSingleInstruction(block, location, instruction);
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if (!should_continue && !is_last_inst)
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goto restart;
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if (auto terminal = block.GetTerminal(); boost::get<IR::Term::Interpret>(&terminal))
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goto restart;
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for (const auto& ir_inst : block)
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if (ir_inst.GetOpcode() == IR::Opcode::A64ExceptionRaised || ir_inst.GetOpcode() == IR::Opcode::A64CallSupervisor || ir_inst.GetOpcode() == IR::Opcode::A64DataCacheOperationRaised)
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goto restart;
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return instruction;
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}
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static void RunTestInstance(const std::array<u64, 31>& regs, const std::array<Vector, 32>& vecs, const size_t instructions_offset, const std::vector<u32>& instructions, const u32 pstate) {
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static TestEnv jit_env;
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static TestEnv uni_env;
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std::copy(instructions.begin(), instructions.end(), jit_env.code_mem.begin() + instructions_offset);
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std::copy(instructions.begin(), instructions.end(), uni_env.code_mem.begin() + instructions_offset);
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jit_env.code_mem[instructions.size() + instructions_offset] = 0x14000000; // B .
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uni_env.code_mem[instructions.size() + instructions_offset] = 0x14000000; // B .
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jit_env.modified_memory.clear();
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uni_env.modified_memory.clear();
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static Dynarmic::A64::Jit jit{Dynarmic::A64::UserConfig{&jit_env}};
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static Unicorn uni{uni_env};
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jit.SetRegisters(regs);
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jit.SetVectors(vecs);
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jit.SetPC(instructions_offset * 4);
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jit.SetSP(0x08000000);
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jit.SetPstate(pstate);
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jit.ClearCache();
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uni.SetRegisters(regs);
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uni.SetVectors(vecs);
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uni.SetPC(instructions_offset * 4);
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uni.SetSP(0x08000000);
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uni.SetPstate(pstate);
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uni.ClearPageCache();
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jit_env.ticks_left = instructions.size();
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jit.Run();
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uni_env.ticks_left = instructions.size();
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uni.Run();
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SCOPE_FAIL {
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fmt::print("Instruction Listing:\n");
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for (u32 instruction : instructions)
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fmt::print("{:08x} {}\n", instruction, Common::DisassembleAArch64(instruction));
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fmt::print("\n");
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fmt::print("Initial register listing:\n");
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for (size_t i = 0; i < regs.size(); ++i)
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fmt::print("{:3s}: {:016x}\n", static_cast<A64::Reg>(i), regs[i]);
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for (size_t i = 0; i < vecs.size(); ++i)
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fmt::print("{:3s}: {}\n", static_cast<A64::Vec>(i), vecs[i]);
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fmt::print("sp : 08000000\n");
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fmt::print("pc : {:016x}\n", instructions_offset * 4);
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fmt::print("p : {:08x}\n", pstate);
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fmt::print("\n");
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fmt::print("Final register listing:\n");
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fmt::print(" unicorn dynarmic\n");
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for (size_t i = 0; i < regs.size(); ++i)
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fmt::print("{:3s}: {:016x} {:016x} {}\n", static_cast<A64::Reg>(i), uni.GetRegisters()[i], jit.GetRegisters()[i], uni.GetRegisters()[i] != jit.GetRegisters()[i] ? "*" : "");
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for (size_t i = 0; i < vecs.size(); ++i)
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fmt::print("{:3s}: {} {} {}\n", static_cast<A64::Vec>(i), uni.GetVectors()[i], jit.GetVectors()[i], uni.GetVectors()[i] != jit.GetVectors()[i] ? "*" : "");
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fmt::print("sp : {:016x} {:016x} {}\n", uni.GetSP(), jit.GetSP(), uni.GetSP() != jit.GetSP() ? "*" : "");
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fmt::print("pc : {:016x} {:016x} {}\n", uni.GetPC(), jit.GetPC(), uni.GetPC() != jit.GetPC() ? "*" : "");
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fmt::print("p : {:08x} {:08x} {}\n", uni.GetPstate(), jit.GetPstate(), (uni.GetPstate() & 0xF0000000) != (jit.GetPstate() & 0xF0000000) ? "*" : "");
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fmt::print("\n");
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fmt::print("Modified memory:\n");
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fmt::print(" uni dyn\n");
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auto uni_iter = uni_env.modified_memory.begin();
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auto jit_iter = jit_env.modified_memory.begin();
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while (uni_iter != uni_env.modified_memory.end() || jit_iter != jit_env.modified_memory.end()) {
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if (uni_iter == uni_env.modified_memory.end() || (jit_iter != jit_env.modified_memory.end() && uni_iter->first > jit_iter->first)) {
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fmt::print("{:016x}: {:02x} *\n", jit_iter->first, jit_iter->second);
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jit_iter++;
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} else if (jit_iter == jit_env.modified_memory.end() || jit_iter->first > uni_iter->first) {
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fmt::print("{:016x}: {:02x} *\n", uni_iter->first, uni_iter->second);
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uni_iter++;
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} else if (uni_iter->first == jit_iter->first) {
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fmt::print("{:016x}: {:02x} {:02x} {}\n", uni_iter->first, uni_iter->second, jit_iter->second, uni_iter->second != jit_iter->second ? "*" : "");
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uni_iter++;
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jit_iter++;
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}
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}
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fmt::print("\n");
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fmt::print("x86_64:\n");
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fmt::print("{}\n", jit.Disassemble());
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};
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REQUIRE(uni.GetPC() == jit.GetPC());
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REQUIRE(uni.GetRegisters() == jit.GetRegisters());
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REQUIRE(uni.GetVectors() == jit.GetVectors());
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REQUIRE(uni.GetSP() == jit.GetSP());
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REQUIRE((uni.GetPstate() & 0xF0000000) == (jit.GetPstate() & 0xF0000000));
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REQUIRE(uni_env.modified_memory == jit_env.modified_memory);
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}
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TEST_CASE("A64: Single random instruction", "[a64]") {
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std::array<u64, 31> regs;
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std::array<Vector, 32> vecs;
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std::vector<u32> instructions(1);
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for (size_t iteration = 0; iteration < 100000; ++iteration) {
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std::generate(regs.begin(), regs.end(), []{ return RandInt<u64>(0, ~u64(0)); });
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std::generate(vecs.begin(), vecs.end(), RandomVector);
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instructions[0] = GenRandomInst(0, true);
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u32 pstate = RandInt<u32>(0, 0xF) << 28;
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INFO("Instruction: 0x" << std::hex << instructions[0]);
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RunTestInstance(regs, vecs, 100, instructions, pstate);
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}
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}
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