From 00af6eeab96171732ab9e22756196bece191df73 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Mon, 2 Apr 2018 20:10:22 -0400 Subject: [PATCH] A64: Implement SADDW/SADDW2 --- src/frontend/A64/decoder/a64.inc | 2 +- src/frontend/A64/translate/impl/impl.h | 2 +- .../A64/translate/impl/simd_three_different.cpp | 16 ++++++++++++++++ 3 files changed, 18 insertions(+), 2 deletions(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index e2955317..fae18f1c 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -676,7 +676,7 @@ INST(NOT, "NOT", "0Q101 // Data Processing - FP and SIMD - SIMD three different //INST(SADDL, "SADDL, SADDL2", "0Q001110zz1mmmmm000000nnnnnddddd") -//INST(SADDW, "SADDW, SADDW2", "0Q001110zz1mmmmm000100nnnnnddddd") +INST(SADDW, "SADDW, SADDW2", "0Q001110zz1mmmmm000100nnnnnddddd") //INST(SSUBL, "SSUBL, SSUBL2", "0Q001110zz1mmmmm001000nnnnnddddd") //INST(SSUBW, "SSUBW, SSUBW2", "0Q001110zz1mmmmm001100nnnnnddddd") //INST(ADDHN, "ADDHN, ADDHN2", "0Q001110zz1mmmmm010000nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/impl.h b/src/frontend/A64/translate/impl/impl.h index a57200e7..2cdbc1f2 100644 --- a/src/frontend/A64/translate/impl/impl.h +++ b/src/frontend/A64/translate/impl/impl.h @@ -803,7 +803,7 @@ struct TranslatorVisitor final { // Data Processing - FP and SIMD - SIMD three different bool SADDL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); - bool SADDW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd); + bool SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd); bool SSUBL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); bool SSUBW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd); bool ADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd); diff --git a/src/frontend/A64/translate/impl/simd_three_different.cpp b/src/frontend/A64/translate/impl/simd_three_different.cpp index 182a7331..e8503079 100644 --- a/src/frontend/A64/translate/impl/simd_three_different.cpp +++ b/src/frontend/A64/translate/impl/simd_three_different.cpp @@ -8,6 +8,22 @@ namespace Dynarmic::A64 { +bool TranslatorVisitor::SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { + if (size == 0b11) { + return ReservedValue(); + } + + const size_t esize = 8 << size.ZeroExtend(); + const size_t part = Q ? 1 : 0; + + const IR::U128 operand1 = V(128, Vn); + const IR::U128 operand2 = ir.VectorSignExtend(esize, Vpart(64, Vm, part)); + const IR::U128 result = ir.VectorAdd(esize * 2, operand1, operand2); + + V(128, Vd, result); + return true; +} + bool TranslatorVisitor::UADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { if (size == 0b11) { return ReservedValue();