diff --git a/src/frontend/A32/decoder/asimd.h b/src/frontend/A32/decoder/asimd.h
index 8df54f9f..61a26e51 100644
--- a/src/frontend/A32/decoder/asimd.h
+++ b/src/frontend/A32/decoder/asimd.h
@@ -8,6 +8,7 @@
 #include <algorithm>
 #include <functional>
 #include <optional>
+#include <set>
 #include <vector>
 
 #include "common/bit_util.h"
@@ -35,6 +36,15 @@ std::vector<ASIMDMatcher<V>> GetASIMDDecodeTable() {
         return Common::BitCount(matcher1.GetMask()) > Common::BitCount(matcher2.GetMask());
     });
 
+    // Exceptions to the above rule of thumb.
+    const std::set<std::string> comes_first{
+        "VBIC, VMOV, VMVN, VORR (immediate)"
+    };
+
+    std::stable_partition(table.begin(), table.end(), [&](const auto& matcher) {
+        return comes_first.count(matcher.GetName()) > 0;
+    });
+
     return table;
 }
 
diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
index cdfa9c02..a6ed0be9 100644
--- a/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
+++ b/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
@@ -3,6 +3,7 @@
  * SPDX-License-Identifier: 0BSD
  */
 
+#include "common/assert.h"
 #include "common/bit_util.h"
 
 #include "frontend/A32/translate/impl/translate_arm.h"
@@ -53,7 +54,7 @@ bool ShiftRight(ArmTranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd,
 
     // Technically just a related encoding (One register and modified immediate instructions)
     if (!L && Common::Bits<3, 5>(imm6) == 0) {
-        return v.UndefinedInstruction();
+        ASSERT_FALSE();
     }
 
     const auto [esize, shift_amount] = ElementSizeAndShiftAmount(true, L, imm6);
@@ -106,7 +107,7 @@ bool ArmTranslatorVisitor::asimd_VSRI(bool D, size_t imm6, size_t Vd, bool L, bo
 
     // Technically just a related encoding (One register and modified immediate instructions)
     if (!L && Common::Bits<3, 5>(imm6) == 0) {
-        return UndefinedInstruction();
+        ASSERT_FALSE();
     }
 
     const auto [esize, shift_amount] = ElementSizeAndShiftAmount(true, L, imm6);
@@ -160,7 +161,7 @@ bool ArmTranslatorVisitor::asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bo
 
     // Technically just a related encoding (One register and modified immediate instructions)
     if (!L && Common::Bits<3, 5>(imm6) == 0) {
-        return UndefinedInstruction();
+        ASSERT_FALSE();
     }
 
     const auto [esize, shift_amount] = ElementSizeAndShiftAmount(false, L, imm6);