diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 550cf9ba..fee1e88e 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -7,7 +7,6 @@ set(SRCS backend_x64/jitstate.cpp backend_x64/reg_alloc.cpp common/memory_pool.cpp - common/string_util.cpp frontend/arm_types.cpp frontend/disassembler/disassembler_arm.cpp frontend/disassembler/disassembler_thumb.cpp diff --git a/src/backend_x64/interface_x64.cpp b/src/backend_x64/interface_x64.cpp index 16228cb1..a485a5ba 100644 --- a/src/backend_x64/interface_x64.cpp +++ b/src/backend_x64/interface_x64.cpp @@ -6,6 +6,8 @@ #include +#include + #ifdef DYNARMIC_USE_LLVM #include #include @@ -18,7 +20,6 @@ #include "common/bit_util.h" #include "common/common_types.h" #include "common/scope_exit.h" -#include "common/string_util.h" #include "dynarmic/dynarmic.h" #include "frontend/arm_types.h" #include "frontend/translate/translate.h" @@ -54,7 +55,7 @@ struct Jit::Impl { std::string Disassemble(const Arm::LocationDescriptor& descriptor) { auto block = GetBasicBlock(descriptor); - std::string result = Common::StringFromFormat("address: %p\nsize: %zu bytes\n", block.code_ptr, block.size); + std::string result = fmt::format("address: {}\nsize: {} bytes\n", block.code_ptr, block.size); #ifdef DYNARMIC_USE_LLVM CodePtr end = block.code_ptr + block.size; @@ -71,11 +72,11 @@ struct Jit::Impl { size_t inst_size = LLVMDisasmInstruction(llvm_ctx, const_cast(pos), remaining, (u64)pos, buffer, sizeof(buffer)); ASSERT(inst_size); for (CodePtr i = pos; i < pos + inst_size; i++) - result.append(Common::StringFromFormat("%02x ", *i)); + result += fmt::format("{:02x} ", *i); for (size_t i = inst_size; i < 10; i++) - result.append(" "); - result.append(buffer); - result.append("\n"); + result += " "; + result += buffer; + result += '\n'; pos += inst_size; remaining -= inst_size; diff --git a/src/common/string_util.cpp b/src/common/string_util.cpp deleted file mode 100644 index 1e8fe464..00000000 --- a/src/common/string_util.cpp +++ /dev/null @@ -1,36 +0,0 @@ -/* This file is part of the dynarmic project. - * Copyright (c) 2016 MerryMage - * This software may be used and distributed according to the terms of the GNU - * General Public License version 2 or any later version. - */ - -#include -#include -#include - -#include "common/string_util.h" - -namespace Dynarmic { -namespace Common { - -std::string StringFromFormat(const char* format, ...) { - va_list args; - - va_start(args, format); - int size = std::vsnprintf(nullptr, 0, format, args); - va_end(args); - - std::string str; - str.resize(size+1); - - va_start(args, format); - std::vsnprintf(&str[0], str.size(), format, args); - va_end(args); - - str.resize(size); - - return str; -} - -} // namespace Common -} // namespace Dynarmic diff --git a/src/common/string_util.h b/src/common/string_util.h index 70713c5e..ceabe3c8 100644 --- a/src/common/string_util.h +++ b/src/common/string_util.h @@ -6,22 +6,9 @@ #pragma once -#include - namespace Dynarmic { namespace Common { -#ifdef __MINGW32__ -[[gnu::format(gnu_printf, 1, 2)]] -#elif !defined(_MSC_VER) -[[gnu::format(printf, 1, 2)]] -#endif -std::string StringFromFormat( -#ifdef _MSC_VER - _Printf_format_string_ -#endif - const char* format, ...); - template constexpr char SignToChar(T value) { return value >= 0 ? '+' : '-'; diff --git a/src/frontend/arm_types.cpp b/src/frontend/arm_types.cpp index 7e856aa2..140d4fc6 100644 --- a/src/frontend/arm_types.cpp +++ b/src/frontend/arm_types.cpp @@ -4,7 +4,9 @@ * General Public License version 2 or any later version. */ -#include "common/string_util.h" +#include + +#include "common/bit_util.h" #include "frontend/arm_types.h" namespace Dynarmic { diff --git a/src/frontend/arm_types.h b/src/frontend/arm_types.h index 348441c5..e37c542b 100644 --- a/src/frontend/arm_types.h +++ b/src/frontend/arm_types.h @@ -6,12 +6,11 @@ #pragma once -#include +#include #include -#include +#include #include "common/assert.h" -#include "common/bit_util.h" #include "common/common_types.h" #include "frontend/arm/FPSCR.h" diff --git a/src/frontend/disassembler/disassembler_arm.cpp b/src/frontend/disassembler/disassembler_arm.cpp index 2b342db9..e19da7f0 100644 --- a/src/frontend/disassembler/disassembler_arm.cpp +++ b/src/frontend/disassembler/disassembler_arm.cpp @@ -7,6 +7,8 @@ #include #include +#include + #include "common/bit_util.h" #include "common/string_util.h" #include "frontend/arm_types.h" @@ -32,16 +34,16 @@ public: switch (shift) { case ShiftType::LSL: if (imm5 == 0) return ""; - return Common::StringFromFormat(", lsl #%hhu", imm5); + return fmt::format(", lsl #{}", imm5); case ShiftType::LSR: if (imm5 == 0) return ", lsr #32"; - return Common::StringFromFormat(", lsr #%hhu", imm5); + return fmt::format(", lsr #{}", imm5); case ShiftType::ASR: if (imm5 == 0) return ", asr #32"; - return Common::StringFromFormat(", asr #%hhu", imm5); + return fmt::format(", asr #{}", imm5); case ShiftType::ROR: if (imm5 == 0) return ", rrx"; - return Common::StringFromFormat(", ror #%hhu", imm5); + return fmt::format(", ror #{}", imm5); } ASSERT(false); return ""; @@ -50,13 +52,13 @@ public: std::string RsrStr(Reg s, ShiftType shift, Reg m) { switch (shift){ case ShiftType::LSL: - return Common::StringFromFormat("%s, lsl %s", RegToString(m), RegToString(s)); + return fmt::format("{}, lsl {}", RegToString(m), RegToString(s)); case ShiftType::LSR: - return Common::StringFromFormat("%s, lsr %s", RegToString(m), RegToString(s)); + return fmt::format("{}, lsr {}", RegToString(m), RegToString(s)); case ShiftType::ASR: - return Common::StringFromFormat("%s, asr %s", RegToString(m), RegToString(s)); + return fmt::format("{}, asr {}", RegToString(m), RegToString(s)); case ShiftType::ROR: - return Common::StringFromFormat("%s, ror %s", RegToString(m), RegToString(s)); + return fmt::format("{}, ror {}", RegToString(m), RegToString(s)); } ASSERT(false); return ""; @@ -67,11 +69,11 @@ public: case SignExtendRotation::ROR_0: return RegToString(m); case SignExtendRotation::ROR_8: - return Common::StringFromFormat("%s, ror #8", RegToString(m)); + return fmt::format("{}, ror #8", RegToString(m)); case SignExtendRotation::ROR_16: - return Common::StringFromFormat("%s, ror #16", RegToString(m)); + return fmt::format("{}, ror #16", RegToString(m)); case SignExtendRotation::ROR_24: - return Common::StringFromFormat("%s, ror #24", RegToString(m)); + return fmt::format("{}, ror #24", RegToString(m)); } ASSERT(false); return ""; @@ -84,7 +86,7 @@ public: } else { reg_num = (base << 1) + (bit ? 1 : 0); } - return Common::StringFromFormat("%c%zu", dp_operation ? 'd' : 's', reg_num); + return fmt::format("{}{}", dp_operation ? 'd' : 's', reg_num); } std::string FPNextRegStr(bool dp_operation, size_t base, bool bit) { @@ -94,30 +96,30 @@ public: } else { reg_num = (base << 1) + (bit ? 1 : 0); } - return Common::StringFromFormat("%c%zu", dp_operation ? 'd' : 's', reg_num + 1); + return fmt::format("{}{}", dp_operation ? 'd' : 's', reg_num + 1); } // Branch instructions std::string arm_B(Cond cond, Imm24 imm24) { s32 offset = Common::SignExtend<26, s32>(imm24 << 2) + 8; - return Common::StringFromFormat("b%s %c#%i", CondToString(cond), Common::SignToChar(offset), abs(offset)); + return fmt::format("b{} {}#{}", CondToString(cond), Common::SignToChar(offset), abs(offset)); } std::string arm_BL(Cond cond, Imm24 imm24) { s32 offset = Common::SignExtend<26, s32>(imm24 << 2) + 8; - return Common::StringFromFormat("bl%s %c#%i", CondToString(cond), Common::SignToChar(offset), abs(offset)); + return fmt::format("bl{} {}#{}", CondToString(cond), Common::SignToChar(offset), abs(offset)); } std::string arm_BLX_imm(bool H, Imm24 imm24) { s32 offset = Common::SignExtend<26, s32>(imm24 << 2) + 8 + (H ? 2 : 0); - return Common::StringFromFormat("blx %c#%i", Common::SignToChar(offset), abs(offset)); + return fmt::format("blx {}#{}", Common::SignToChar(offset), abs(offset)); } std::string arm_BLX_reg(Cond cond, Reg m) { - return Common::StringFromFormat("blx%s %s", CondToString(cond), RegToString(m)); + return fmt::format("blx{} {}", CondToString(cond), RegToString(m)); } std::string arm_BX(Cond cond, Reg m) { - return Common::StringFromFormat("bx%s %s", CondToString(cond), RegToString(m)); + return fmt::format("bx{} {}", CondToString(cond), RegToString(m)); } std::string arm_BXJ(Cond cond, Reg m) { - return Common::StringFromFormat("bxj%s %s", CondToString(cond), RegToString(m)); + return fmt::format("bxj{} {}", CondToString(cond), RegToString(m)); } // Coprocessor instructions @@ -131,197 +133,197 @@ public: // Data processing instructions std::string arm_ADC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("adc%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); + return fmt::format("adc{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_ADC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("adc%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); + return fmt::format("adc{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5)); } std::string arm_ADC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("adc%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); + return fmt::format("adc{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m)); } std::string arm_ADD_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("add%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); + return fmt::format("add{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_ADD_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("add%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); + return fmt::format("add{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5)); } std::string arm_ADD_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("add%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); + return fmt::format("add{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m)); } std::string arm_AND_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("and%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); + return fmt::format("and{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_AND_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("and%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); + return fmt::format("and{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5)); } std::string arm_AND_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("and%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); + return fmt::format("and{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m)); } std::string arm_BIC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("bic%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); + return fmt::format("bic{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_BIC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("bic%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); + return fmt::format("bic{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5)); } std::string arm_BIC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("bic%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); + return fmt::format("bic{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m)); } std::string arm_CMN_imm(Cond cond, Reg n, int rotate, Imm8 imm8) { - return Common::StringFromFormat("cmn%s %s, #%i", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8)); + return fmt::format("cmn{} {}, #{}", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_CMN_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("cmn%s %s, %s%s", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); + return fmt::format("cmn{} {}, {}{}", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5)); } std::string arm_CMN_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("cmn%s %s, %s", CondToString(cond), RegToString(n), RsrStr(s, shift, m).c_str()); + return fmt::format("cmn{} {}, {}", CondToString(cond), RegToString(n), RsrStr(s, shift, m)); } std::string arm_CMP_imm(Cond cond, Reg n, int rotate, Imm8 imm8) { - return Common::StringFromFormat("cmp%s %s, #%i", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8)); + return fmt::format("cmp{} {}, #{}", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_CMP_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("cmp%s %s, %s%s", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); + return fmt::format("cmp{} {}, {}{}", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5)); } std::string arm_CMP_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("cmp%s %s, %s", CondToString(cond), RegToString(n), RsrStr(s, shift, m).c_str()); + return fmt::format("cmp{} {}, {}", CondToString(cond), RegToString(n), RsrStr(s, shift, m)); } std::string arm_EOR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("eor%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); + return fmt::format("eor{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_EOR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("eor%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); + return fmt::format("eor{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5)); } std::string arm_EOR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("eor%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); + return fmt::format("eor{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m)); } std::string arm_MOV_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("mov%s%s %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), ArmExpandImm(rotate, imm8)); + return fmt::format("mov{}{} {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), ArmExpandImm(rotate, imm8)); } std::string arm_MOV_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("mov%s%s %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(m), ShiftStr(shift, imm5).c_str()); + return fmt::format("mov{}{} {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(m), ShiftStr(shift, imm5)); } std::string arm_MOV_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("mov%s%s %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RsrStr(s, shift, m).c_str()); + return fmt::format("mov{}{} {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RsrStr(s, shift, m)); } std::string arm_MVN_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("mvn%s%s %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), ArmExpandImm(rotate, imm8)); + return fmt::format("mvn{}{} {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), ArmExpandImm(rotate, imm8)); } std::string arm_MVN_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("mvn%s%s %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(m), ShiftStr(shift, imm5).c_str()); + return fmt::format("mvn{}{} {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(m), ShiftStr(shift, imm5)); } std::string arm_MVN_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("mvn%s%s %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RsrStr(s, shift, m).c_str()); + return fmt::format("mvn{}{} {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RsrStr(s, shift, m)); } std::string arm_ORR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("orr%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); + return fmt::format("orr{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_ORR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("orr%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); + return fmt::format("orr{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5)); } std::string arm_ORR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("orr%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); + return fmt::format("orr{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m)); } std::string arm_RSB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("rsb%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); + return fmt::format("rsb{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_RSB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("rsb%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); + return fmt::format("rsb{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5)); } std::string arm_RSB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("rsb%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); + return fmt::format("rsb{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m)); } std::string arm_RSC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("rsc%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); + return fmt::format("rsc{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_RSC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("rsc%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); + return fmt::format("rsc{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5)); } std::string arm_RSC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("rsc%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); + return fmt::format("rsc{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m)); } std::string arm_SBC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("sbc%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); + return fmt::format("sbc{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_SBC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("sbc%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); + return fmt::format("sbc{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5)); } std::string arm_SBC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("sbc%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); + return fmt::format("sbc{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m)); } std::string arm_SUB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("sub%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); + return fmt::format("sub{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_SUB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("sub%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); + return fmt::format("sub{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5)); } std::string arm_SUB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("sub%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); + return fmt::format("sub{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m)); } std::string arm_TEQ_imm(Cond cond, Reg n, int rotate, Imm8 imm8) { - return Common::StringFromFormat("teq%s %s, #%i", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8)); + return fmt::format("teq{} {}, #{}", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_TEQ_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("teq%s %s, %s%s", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); + return fmt::format("teq{} {}, {}{}", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5)); } std::string arm_TEQ_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("teq%s %s, %s", CondToString(cond), RegToString(n), RsrStr(s, shift, m).c_str()); + return fmt::format("teq{} {}, {}", CondToString(cond), RegToString(n), RsrStr(s, shift, m)); } std::string arm_TST_imm(Cond cond, Reg n, int rotate, Imm8 imm8) { - return Common::StringFromFormat("tst%s %s, #%i", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8)); + return fmt::format("tst{} {}, #{}", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_TST_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("tst%s %s, %s%s", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); + return fmt::format("tst{} {}, {}{}", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5)); } std::string arm_TST_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("tst%s %s, %s", CondToString(cond), RegToString(n), RsrStr(s, shift, m).c_str()); + return fmt::format("tst{} {}, {}", CondToString(cond), RegToString(n), RsrStr(s, shift, m)); } // Exception generation instructions std::string arm_BKPT(Cond cond, Imm12 imm12, Imm4 imm4) { - return Common::StringFromFormat("bkpt #%hu", imm12 << 4 | imm4); + return fmt::format("bkpt #{}", imm12 << 4 | imm4); } std::string arm_SVC(Cond cond, Imm24 imm24) { - return Common::StringFromFormat("svc%s #%u", CondToString(cond), imm24); + return fmt::format("svc{} #{}", CondToString(cond), imm24); } std::string arm_UDF() { - return Common::StringFromFormat("udf"); + return fmt::format("udf"); } // Extension functions std::string arm_SXTAB(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) { - return Common::StringFromFormat("sxtab%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate).c_str()); + return fmt::format("sxtab{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate)); } std::string arm_SXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) { - return Common::StringFromFormat("sxtab16%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate).c_str()); + return fmt::format("sxtab16{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate)); } std::string arm_SXTAH(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) { - return Common::StringFromFormat("sxtah%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate).c_str()); + return fmt::format("sxtah{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate)); } std::string arm_SXTB(Cond cond, Reg d, SignExtendRotation rotate, Reg m) { - return Common::StringFromFormat("sxtb%s %s, %s", CondToString(cond), RegToString(d), RorStr(m, rotate).c_str()); + return fmt::format("sxtb{} {}, {}", CondToString(cond), RegToString(d), RorStr(m, rotate)); } std::string arm_SXTB16(Cond cond, Reg d, SignExtendRotation rotate, Reg m) { - return Common::StringFromFormat("sxtb16%s %s, %s", CondToString(cond), RegToString(d), RorStr(m, rotate).c_str()); + return fmt::format("sxtb16{} {}, {}", CondToString(cond), RegToString(d), RorStr(m, rotate)); } std::string arm_SXTH(Cond cond, Reg d, SignExtendRotation rotate, Reg m) { - return Common::StringFromFormat("sxth%s %s, %s", CondToString(cond), RegToString(d), RorStr(m, rotate).c_str()); + return fmt::format("sxth{} {}, {}", CondToString(cond), RegToString(d), RorStr(m, rotate)); } std::string arm_UXTAB(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) { - return Common::StringFromFormat("uxtab%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate).c_str()); + return fmt::format("uxtab{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate)); } std::string arm_UXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) { - return Common::StringFromFormat("uxtab16%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate).c_str()); + return fmt::format("uxtab16{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate)); } std::string arm_UXTAH(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) { - return Common::StringFromFormat("uxtah%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate).c_str()); + return fmt::format("uxtah{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate)); } std::string arm_UXTB(Cond cond, Reg d, SignExtendRotation rotate, Reg m) { - return Common::StringFromFormat("uxtb%s %s, %s", CondToString(cond), RegToString(d), RorStr(m, rotate).c_str()); + return fmt::format("uxtb{} {}, {}", CondToString(cond), RegToString(d), RorStr(m, rotate)); } std::string arm_UXTB16(Cond cond, Reg d, SignExtendRotation rotate, Reg m) { - return Common::StringFromFormat("uxtb16%s %s, %s", CondToString(cond), RegToString(d), RorStr(m, rotate).c_str()); + return fmt::format("uxtb16{} {}, {}", CondToString(cond), RegToString(d), RorStr(m, rotate)); } std::string arm_UXTH(Cond cond, Reg d, SignExtendRotation rotate, Reg m) { - return Common::StringFromFormat("uxth%s %s, %s", CondToString(cond), RegToString(d), RorStr(m, rotate).c_str()); + return fmt::format("uxth{} {}, {}", CondToString(cond), RegToString(d), RorStr(m, rotate)); } // Hint instructions @@ -338,16 +340,16 @@ public: } std::string arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm12 imm12) { if (P) { - return Common::StringFromFormat("ldr%s %s, [%s, #%c%u]%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? "!" : ""); + return fmt::format("ldr{} {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? "!" : ""); } else { - return Common::StringFromFormat("ldr%s %s, [%s], #%c%u%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? " (err: W == 1!!!)" : ""); + return fmt::format("ldr{} {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? " (err: W == 1!!!)" : ""); } } std::string arm_LDR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm5 imm5, ShiftType shift, Reg m) { if (P) { - return Common::StringFromFormat("ldr%s %s, [%s, %c%s%s]%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5).c_str(), W ? "!" : ""); + return fmt::format("ldr{} {}, [{}, {}{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5), W ? "!" : ""); } else { - return Common::StringFromFormat("ldr%s %s, [%s], %c%s%s%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5).c_str(), W ? " (err: W == 1!!!)" : ""); + return fmt::format("ldr{} {}, [{}], {}{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5), W ? " (err: W == 1!!!)" : ""); } } std::string arm_LDRB_lit(Cond cond, bool U, Reg t, Imm12 imm12) { @@ -356,16 +358,16 @@ public: } std::string arm_LDRB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm12 imm12) { if (P) { - return Common::StringFromFormat("ldrb%s %s, [%s, #%c%u]%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? "!" : ""); + return fmt::format("ldrb{} {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? "!" : ""); } else { - return Common::StringFromFormat("ldrb%s %s, [%s], #%c%u%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? " (err: W == 1!!!)" : ""); + return fmt::format("ldrb{} {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? " (err: W == 1!!!)" : ""); } } std::string arm_LDRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm5 imm5, ShiftType shift, Reg m) { if (P) { - return Common::StringFromFormat("ldrb%s %s, [%s, %c%s%s]%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5).c_str(), W ? "!" : ""); + return fmt::format("ldrb{} {}, [{}, {}{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5), W ? "!" : ""); } else { - return Common::StringFromFormat("ldrb%s %s, [%s], %c%s%s%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5).c_str(), W ? " (err: W == 1!!!)" : ""); + return fmt::format("ldrb{} {}, [{}], {}{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5), W ? " (err: W == 1!!!)" : ""); } } std::string arm_LDRBT() { return "ice"; } @@ -376,16 +378,16 @@ public: std::string arm_LDRD_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm4 imm8a, Imm4 imm8b) { u32 imm32 = (imm8a << 4) | imm8b; if (P) { - return Common::StringFromFormat("ldrd%s %s, %s, [%s, #%c%u]%s", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', imm32, W ? "!" : ""); + return fmt::format("ldrd{} {}, {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', imm32, W ? "!" : ""); } else { - return Common::StringFromFormat("ldrd%s %s, %s, [%s], #%c%u%s", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : ""); + return fmt::format("ldrd{} {}, {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : ""); } } std::string arm_LDRD_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) { if (P) { - return Common::StringFromFormat("ldrd%s %s, %s, [%s, %c%s]%s", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : ""); + return fmt::format("ldrd{} {}, {}, [{}, {}{}]{}", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : ""); } else { - return Common::StringFromFormat("ldrd%s %s, %s, [%s], %c%s%s", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : ""); + return fmt::format("ldrd{} {}, {}, [{}], {}{}{}", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : ""); } } std::string arm_LDRH_lit(Cond cond, bool P, bool U, bool W, Reg t, Imm4 imm8a, Imm4 imm8b) { @@ -394,16 +396,16 @@ public: std::string arm_LDRH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm4 imm8a, Imm4 imm8b) { u32 imm32 = (imm8a << 4) | imm8b; if (P) { - return Common::StringFromFormat("ldrh%s %s, [%s, #%c%u]%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? "!" : ""); + return fmt::format("ldrh{} {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? "!" : ""); } else { - return Common::StringFromFormat("ldrh%s %s, [%s], #%c%u%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : ""); + return fmt::format("ldrh{} {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : ""); } } std::string arm_LDRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) { if (P) { - return Common::StringFromFormat("ldrd%s %s, [%s, %c%s]%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : ""); + return fmt::format("ldrd{} {}, [{}, {}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : ""); } else { - return Common::StringFromFormat("ldrd%s %s, [%s], %c%s%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : ""); + return fmt::format("ldrd{} {}, [{}], {}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : ""); } } std::string arm_LDRHT() { return "ice"; } @@ -414,16 +416,16 @@ public: std::string arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm4 imm8a, Imm4 imm8b) { u32 imm32 = (imm8a << 4) | imm8b; if (P) { - return Common::StringFromFormat("ldrsb%s %s, [%s, #%c%u]%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? "!" : ""); + return fmt::format("ldrsb{} {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? "!" : ""); } else { - return Common::StringFromFormat("ldrsb%s %s, [%s], #%c%u%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : ""); + return fmt::format("ldrsb{} {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : ""); } } std::string arm_LDRSB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) { if (P) { - return Common::StringFromFormat("ldrsb%s %s, [%s, %c%s]%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : ""); + return fmt::format("ldrsb{} {}, [{}, {}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : ""); } else { - return Common::StringFromFormat("ldrsb%s %s, [%s], %c%s%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : ""); + return fmt::format("ldrsb{} {}, [{}], {}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : ""); } } std::string arm_LDRSBT() { return "ice"; } @@ -434,77 +436,77 @@ public: std::string arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm4 imm8a, Imm4 imm8b) { u32 imm32 = (imm8a << 4) | imm8b; if (P) { - return Common::StringFromFormat("ldrsh%s %s, [%s, #%c%u]%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? "!" : ""); + return fmt::format("ldrsh{} {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? "!" : ""); } else { - return Common::StringFromFormat("ldrsh%s %s, [%s], #%c%u%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : ""); + return fmt::format("ldrsh{} {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : ""); } } std::string arm_LDRSH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) { if (P) { - return Common::StringFromFormat("ldrsh%s %s, [%s, %c%s]%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : ""); + return fmt::format("ldrsh{} {}, [{}, {}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : ""); } else { - return Common::StringFromFormat("ldrsh%s %s, [%s], %c%s%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : ""); + return fmt::format("ldrsh{} {}, [{}], {}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : ""); } } std::string arm_LDRSHT() { return "ice"; } std::string arm_LDRT() { return "ice"; } std::string arm_STR_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm12 imm12) { if (P) { - return Common::StringFromFormat("str%s %s, [%s, #%c%u]%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? "!" : ""); + return fmt::format("str{} {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? "!" : ""); } else { - return Common::StringFromFormat("str%s %s, [%s], #%c%u%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? " (err: W == 1!!!)" : ""); + return fmt::format("str{} {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? " (err: W == 1!!!)" : ""); } } std::string arm_STR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm5 imm5, ShiftType shift, Reg m) { if (P) { - return Common::StringFromFormat("str%s %s, [%s, %c%s%s]%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5).c_str(), W ? "!" : ""); + return fmt::format("str{} {}, [{}, {}{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5), W ? "!" : ""); } else { - return Common::StringFromFormat("str%s %s, [%s], %c%s%s%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5).c_str(), W ? " (err: W == 1!!!)" : ""); + return fmt::format("str{} {}, [{}], {}{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5), W ? " (err: W == 1!!!)" : ""); } } std::string arm_STRB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm12 imm12) { if (P) { - return Common::StringFromFormat("strb%s %s, [%s, #%c%u]%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? "!" : ""); + return fmt::format("strb{} {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? "!" : ""); } else { - return Common::StringFromFormat("strb%s %s, [%s], #%c%u%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? " (err: W == 1!!!)" : ""); + return fmt::format("strb{} {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? " (err: W == 1!!!)" : ""); } } std::string arm_STRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm5 imm5, ShiftType shift, Reg m) { if (P) { - return Common::StringFromFormat("strb%s %s, [%s, %c%s%s]%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5).c_str(), W ? "!" : ""); + return fmt::format("strb{} {}, [{}, {}{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5), W ? "!" : ""); } else { - return Common::StringFromFormat("strb%s %s, [%s], %c%s%s%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5).c_str(), W ? " (err: W == 1!!!)" : ""); + return fmt::format("strb{} {}, [{}], {}{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5), W ? " (err: W == 1!!!)" : ""); } } std::string arm_STRBT() { return "ice"; } std::string arm_STRD_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm4 imm8a, Imm4 imm8b) { u32 imm32 = (imm8a << 4) | imm8b; if (P) { - return Common::StringFromFormat("strd%s %s, %s, [%s, #%c%u]%s", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', imm32, W ? "!" : ""); + return fmt::format("strd{} {}, {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', imm32, W ? "!" : ""); } else { - return Common::StringFromFormat("strd%s %s, %s, [%s], #%c%u%s", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : ""); + return fmt::format("strd{} {}, {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : ""); } } std::string arm_STRD_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) { if (P) { - return Common::StringFromFormat("strd%s %s, %s, [%s, %c%s]%s", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : ""); + return fmt::format("strd{} {}, {}, [{}, {}{}]{}", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : ""); } else { - return Common::StringFromFormat("strd%s %s, %s, [%s], %c%s%s", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : ""); + return fmt::format("strd{} {}, {}, [{}], {}{}{}", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : ""); } } std::string arm_STRH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm4 imm8a, Imm4 imm8b) { u32 imm32 = (imm8a << 4) | imm8b; if (P) { - return Common::StringFromFormat("strh%s %s, [%s, #%c%u]%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? "!" : ""); + return fmt::format("strh{} {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? "!" : ""); } else { - return Common::StringFromFormat("strh%s %s, [%s], #%c%u%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : ""); + return fmt::format("strh{} {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : ""); } } std::string arm_STRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) { if (P) { - return Common::StringFromFormat("strd%s %s, [%s, %c%s]%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : ""); + return fmt::format("strd{} {}, [{}, {}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : ""); } else { - return Common::StringFromFormat("strd%s %s, [%s], %c%s%s", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : ""); + return fmt::format("strd{} {}, [{}], {}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : ""); } } std::string arm_STRHT() { return "ice"; } @@ -512,158 +514,158 @@ public: // Load/Store multiple instructions std::string arm_LDM(Cond cond, bool W, Reg n, RegList list) { - return Common::StringFromFormat("ldm%s %s%s, {%s}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list).c_str()); + return fmt::format("ldm{} {}{}, {{{}}}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list)); } std::string arm_LDMDA(Cond cond, bool W, Reg n, RegList list) { - return Common::StringFromFormat("ldmda%s %s%s, {%s}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list).c_str()); + return fmt::format("ldmda{} {}{}, {{{}}}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list)); } std::string arm_LDMDB(Cond cond, bool W, Reg n, RegList list) { - return Common::StringFromFormat("ldmdb%s %s%s, {%s}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list).c_str()); + return fmt::format("ldmdb{} {}{}, {{{}}}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list)); } std::string arm_LDMIB(Cond cond, bool W, Reg n, RegList list) { - return Common::StringFromFormat("ldmib%s %s%s, {%s}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list).c_str()); + return fmt::format("ldmib{} {}{}, {{{}}}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list)); } std::string arm_LDM_usr() { return "ice"; } std::string arm_LDM_eret() { return "ice"; } std::string arm_STM(Cond cond, bool W, Reg n, RegList list) { - return Common::StringFromFormat("stm%s %s%s, {%s}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list).c_str()); + return fmt::format("stm{} {}{}, {{{}}}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list)); } std::string arm_STMDA(Cond cond, bool W, Reg n, RegList list) { - return Common::StringFromFormat("stmda%s %s%s, {%s}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list).c_str()); + return fmt::format("stmda{} {}{}, {{{}}}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list)); } std::string arm_STMDB(Cond cond, bool W, Reg n, RegList list) { - return Common::StringFromFormat("stmdb%s %s%s, {%s}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list).c_str()); + return fmt::format("stmdb{} {}{}, {{{}}}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list)); } std::string arm_STMIB(Cond cond, bool W, Reg n, RegList list) { - return Common::StringFromFormat("stmib%s %s%s, {%s}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list).c_str()); + return fmt::format("stmib{} {}{}, {{{}}}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list)); } std::string arm_STM_usr() { return "ice"; } // Miscellaneous instructions std::string arm_CLZ(Cond cond, Reg d, Reg m) { - return Common::StringFromFormat("clz%s %s, %s", CondToString(cond), RegToString(d), RegToString(m)); + return fmt::format("clz{} {}, {}", CondToString(cond), RegToString(d), RegToString(m)); } std::string arm_NOP() { return "nop"; } std::string arm_SEL(Cond cond, Reg n, Reg d, Reg m) { - return Common::StringFromFormat("sel%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("sel{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); } // Unsigned sum of absolute difference functions std::string arm_USAD8(Cond cond, Reg d, Reg m, Reg n) { - return Common::StringFromFormat("usad8%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("usad8{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); } std::string arm_USADA8(Cond cond, Reg d, Reg a, Reg m, Reg n) { - return Common::StringFromFormat("usad8a%s %s, %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a)); + return fmt::format("usad8a{} {}, {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a)); } // Packing instructions std::string arm_PKHBT(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m) { - return Common::StringFromFormat("pkhbt%s %s, %s, %s%s", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), ShiftStr(ShiftType::LSL, imm5).c_str()); + return fmt::format("pkhbt{} {}, {}, {}{}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), ShiftStr(ShiftType::LSL, imm5)); } std::string arm_PKHTB(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m) { - return Common::StringFromFormat("pkhtb%s %s, %s, %s%s", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), ShiftStr(ShiftType::ASR, imm5).c_str()); + return fmt::format("pkhtb{} {}, {}, {}{}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), ShiftStr(ShiftType::ASR, imm5)); } // Reversal instructions std::string arm_REV(Cond cond, Reg d, Reg m) { - return Common::StringFromFormat("rev%s %s, %s", CondToString(cond), RegToString(d), RegToString(m)); + return fmt::format("rev{} {}, {}", CondToString(cond), RegToString(d), RegToString(m)); } std::string arm_REV16(Cond cond, Reg d, Reg m) { - return Common::StringFromFormat("rev16%s %s, %s", CondToString(cond), RegToString(d), RegToString(m)); + return fmt::format("rev16{} {}, {}", CondToString(cond), RegToString(d), RegToString(m)); } std::string arm_REVSH(Cond cond, Reg d, Reg m) { - return Common::StringFromFormat("revsh%s %s, %s", CondToString(cond), RegToString(d), RegToString(m)); + return fmt::format("revsh{} {}, {}", CondToString(cond), RegToString(d), RegToString(m)); } // Saturation instructions std::string arm_SSAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) { - return Common::StringFromFormat("ssat%s %s, #%u, %s%s", CondToString(cond), RegToString(d), sat_imm + 1, RegToString(n), ShiftStr(ShiftType(sh << 1), imm5).c_str()); + return fmt::format("ssat{} {}, #{}, {}{}", CondToString(cond), RegToString(d), sat_imm + 1, RegToString(n), ShiftStr(ShiftType(sh << 1), imm5)); } std::string arm_SSAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n) { - return Common::StringFromFormat("ssat16%s %s, #%u, %s", CondToString(cond), RegToString(d), sat_imm + 1, RegToString(n)); + return fmt::format("ssat16{} {}, #{}, {}", CondToString(cond), RegToString(d), sat_imm + 1, RegToString(n)); } std::string arm_USAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) { - return Common::StringFromFormat("usat%s %s, #%u, %s%s", CondToString(cond), RegToString(d), sat_imm, RegToString(n), ShiftStr(ShiftType(sh << 1), imm5).c_str()); + return fmt::format("usat{} {}, #{}, {}{}", CondToString(cond), RegToString(d), sat_imm, RegToString(n), ShiftStr(ShiftType(sh << 1), imm5)); } std::string arm_USAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n) { - return Common::StringFromFormat("usat16%s %s, #%u, %s", CondToString(cond), RegToString(d), sat_imm, RegToString(n)); + return fmt::format("usat16{} {}, #{}, {}", CondToString(cond), RegToString(d), sat_imm, RegToString(n)); } // Multiply (Normal) instructions std::string arm_MLA(Cond cond, bool S, Reg d, Reg a, Reg m, Reg n) { - return Common::StringFromFormat("mla%s%s %s, %s, %s, %s", S ? "s" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a)); + return fmt::format("mla{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a)); } std::string arm_MUL(Cond cond, bool S, Reg d, Reg m, Reg n) { - return Common::StringFromFormat("mul%s%s %s, %s, %s", S ? "s" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("mul{}{} {}, {}, {}", S ? "s" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); } // Multiply (Long) instructions std::string arm_SMLAL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) { - return Common::StringFromFormat("smlal%s%s %s, %s, %s, %s", S ? "s" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m)); + return fmt::format("smlal{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m)); } std::string arm_SMULL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) { - return Common::StringFromFormat("smull%s%s %s, %s, %s, %s", S ? "s" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m)); + return fmt::format("smull{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m)); } std::string arm_UMAAL(Cond cond, Reg dHi, Reg dLo, Reg m, Reg n) { - return Common::StringFromFormat("umaal%s %s, %s, %s, %s", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m)); + return fmt::format("umaal{} {}, {}, {}, {}", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m)); } std::string arm_UMLAL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) { - return Common::StringFromFormat("umlal%s%s %s, %s, %s, %s", S ? "s" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m)); + return fmt::format("umlal{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m)); } std::string arm_UMULL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) { - return Common::StringFromFormat("umull%s%s %s, %s, %s, %s", S ? "s" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m)); + return fmt::format("umull{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m)); } // Multiply (Halfword) instructions std::string arm_SMLALxy(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, bool N, Reg n) { - return Common::StringFromFormat("smlal%c%c%s %s, %s, %s, %s", N ? 't' : 'b', M ? 't' : 'b', CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m)); + return fmt::format("smlal{}{}{} {}, {}, {}, {}", N ? 't' : 'b', M ? 't' : 'b', CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m)); } std::string arm_SMLAxy(Cond cond, Reg d, Reg a, Reg m, bool M, bool N, Reg n) { - return Common::StringFromFormat("smla%c%c%s %s, %s, %s, %s", N ? 't' : 'b', M ? 't' : 'b', CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a)); + return fmt::format("smla{}{}{} {}, {}, {}, {}", N ? 't' : 'b', M ? 't' : 'b', CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a)); } std::string arm_SMULxy(Cond cond, Reg d, Reg m, bool M, bool N, Reg n) { - return Common::StringFromFormat("smul%c%c%s %s, %s, %s", N ? 't' : 'b', M ? 't' : 'b', CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("smul{}{}{} {}, {}, {}", N ? 't' : 'b', M ? 't' : 'b', CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); } // Multiply (word by halfword) instructions std::string arm_SMLAWy(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n) { - return Common::StringFromFormat("smlaw%c%s %s, %s, %s, %s", M ? 't' : 'b', CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a)); + return fmt::format("smlaw{}{} {}, {}, {}, {}", M ? 't' : 'b', CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a)); } std::string arm_SMULWy(Cond cond, Reg d, Reg m, bool M, Reg n) { - return Common::StringFromFormat("smulw%c%s %s, %s, %s", M ? 't' : 'b', CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("smulw{}{} {}, {}, {}", M ? 't' : 'b', CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); } // Multiply (Most significant word) instructions std::string arm_SMMLA(Cond cond, Reg d, Reg a, Reg m, bool R, Reg n) { - return Common::StringFromFormat("smmla%s%s %s, %s, %s, %s", R ? "r" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a)); + return fmt::format("smmla{}{} {}, {}, {}, {}", R ? "r" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a)); } std::string arm_SMMLS(Cond cond, Reg d, Reg a, Reg m, bool R, Reg n) { - return Common::StringFromFormat("smmls%s%s %s, %s, %s, %s", R ? "r" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a)); + return fmt::format("smmls{}{} {}, {}, {}, {}", R ? "r" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a)); } std::string arm_SMMUL(Cond cond, Reg d, Reg m, bool R, Reg n) { - return Common::StringFromFormat("smmul%s%s %s, %s, %s", R ? "r" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("smmul{}{} {}, {}, {}", R ? "r" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); } // Multiply (Dual) instructions std::string arm_SMLAD(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n) { - return Common::StringFromFormat("smlad%s%s %s, %s, %s, %s", M ? "x" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a)); + return fmt::format("smlad{}{} {}, {}, {}, {}", M ? "x" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a)); } std::string arm_SMLALD(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, Reg n) { - return Common::StringFromFormat("smlald%s%s %s, %s, %s, %s", M ? "x" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m)); + return fmt::format("smlald{}{} {}, {}, {}, {}", M ? "x" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m)); } std::string arm_SMLSD(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n) { - return Common::StringFromFormat("smlsd%s%s %s, %s, %s, %s", M ? "x" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a)); + return fmt::format("smlsd{}{} {}, {}, {}, {}", M ? "x" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a)); } std::string arm_SMLSLD(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, Reg n) { - return Common::StringFromFormat("smlsld%s%s %s, %s, %s, %s", M ? "x" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m)); + return fmt::format("smlsld{}{} {}, {}, {}, {}", M ? "x" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m)); } std::string arm_SMUAD(Cond cond, Reg d, Reg m, bool M, Reg n) { - return Common::StringFromFormat("smuad%s%s %s, %s, %s", M ? "x" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("smuad{}{} {}, {}, {}", M ? "x" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); } std::string arm_SMUSD(Cond cond, Reg d, Reg m, bool M, Reg n) { - return Common::StringFromFormat("smusd%s%s %s, %s, %s", M ? "x" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("smusd{}{} {}, {}, {}", M ? "x" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); } // Parallel Add/Subtract (Modulo arithmetic) instructions @@ -682,32 +684,32 @@ public: // Parallel Add/Subtract (Saturating) instructions std::string arm_QADD8(Cond cond, Reg n, Reg d, Reg m) { - return Common::StringFromFormat("qadd8%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("qadd8{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); } std::string arm_QADD16(Cond cond, Reg n, Reg d, Reg m) { - return Common::StringFromFormat("qadd16%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("qadd16{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); } std::string arm_QASX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; } std::string arm_QSAX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; } std::string arm_QSUB8(Cond cond, Reg n, Reg d, Reg m) { - return Common::StringFromFormat("qsub8%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("qsub8{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); } std::string arm_QSUB16(Cond cond, Reg n, Reg d, Reg m) { - return Common::StringFromFormat("qsub16%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("qsub16{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); } std::string arm_UQADD8(Cond cond, Reg n, Reg d, Reg m) { - return Common::StringFromFormat("uqadd8%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("uqadd8{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); } std::string arm_UQADD16(Cond cond, Reg n, Reg d, Reg m) { - return Common::StringFromFormat("uqadd16%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("uqadd16{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); } std::string arm_UQASX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; } std::string arm_UQSAX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; } std::string arm_UQSUB8(Cond cond, Reg n, Reg d, Reg m) { - return Common::StringFromFormat("uqsub8%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("uqsub8{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); } std::string arm_UQSUB16(Cond cond, Reg n, Reg d, Reg m) { - return Common::StringFromFormat("uqsub16%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("uqsub16{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m)); } // Parallel Add/Subtract (Halving) instructions @@ -735,50 +737,50 @@ public: return "clrex"; } std::string arm_LDREX(Cond cond, Reg n, Reg d) { - return Common::StringFromFormat("ldrex%s %s, [%s]", CondToString(cond), RegToString(d), RegToString(n)); + return fmt::format("ldrex{} {}, [{}]", CondToString(cond), RegToString(d), RegToString(n)); } std::string arm_LDREXB(Cond cond, Reg n, Reg d) { - return Common::StringFromFormat("ldrexb%s %s, [%s]", CondToString(cond), RegToString(d), RegToString(n)); + return fmt::format("ldrexb{} {}, [{}]", CondToString(cond), RegToString(d), RegToString(n)); } std::string arm_LDREXD(Cond cond, Reg n, Reg d) { - return Common::StringFromFormat("ldrexd%s %s, %s, [%s]", CondToString(cond), RegToString(d), RegToString(d+1), RegToString(n)); + return fmt::format("ldrexd{} {}, {}, [{}]", CondToString(cond), RegToString(d), RegToString(d+1), RegToString(n)); } std::string arm_LDREXH(Cond cond, Reg n, Reg d) { - return Common::StringFromFormat("ldrexh%s %s, [%s]", CondToString(cond), RegToString(d), RegToString(n)); + return fmt::format("ldrexh{} {}, [{}]", CondToString(cond), RegToString(d), RegToString(n)); } std::string arm_STREX(Cond cond, Reg n, Reg d, Reg m) { - return Common::StringFromFormat("strex%s %s, %s, [%s]", CondToString(cond), RegToString(d), RegToString(m), RegToString(n)); + return fmt::format("strex{} {}, {}, [{}]", CondToString(cond), RegToString(d), RegToString(m), RegToString(n)); } std::string arm_STREXB(Cond cond, Reg n, Reg d, Reg m) { - return Common::StringFromFormat("strexb%s %s, %s, [%s]", CondToString(cond), RegToString(d), RegToString(m), RegToString(n)); + return fmt::format("strexb{} {}, {}, [{}]", CondToString(cond), RegToString(d), RegToString(m), RegToString(n)); } std::string arm_STREXD(Cond cond, Reg n, Reg d, Reg m) { - return Common::StringFromFormat("strexd%s %s, %s, %s, [%s]", CondToString(cond), RegToString(d), RegToString(m), RegToString(m+1), RegToString(n)); + return fmt::format("strexd{} {}, {}, {}, [{}]", CondToString(cond), RegToString(d), RegToString(m), RegToString(m+1), RegToString(n)); } std::string arm_STREXH(Cond cond, Reg n, Reg d, Reg m) { - return Common::StringFromFormat("strexh%s %s, %s, [%s]", CondToString(cond), RegToString(d), RegToString(m), RegToString(n)); + return fmt::format("strexh{} {}, {}, [{}]", CondToString(cond), RegToString(d), RegToString(m), RegToString(n)); } std::string arm_SWP(Cond cond, Reg n, Reg t, Reg t2) { - return Common::StringFromFormat("swp%s %s, %s, [%s]", CondToString(cond), RegToString(t), RegToString(t2), RegToString(n)); + return fmt::format("swp{} {}, {}, [{}]", CondToString(cond), RegToString(t), RegToString(t2), RegToString(n)); } std::string arm_SWPB(Cond cond, Reg n, Reg t, Reg t2) { - return Common::StringFromFormat("swpb%s %s, %s, [%s]", CondToString(cond), RegToString(t), RegToString(t2), RegToString(n)); + return fmt::format("swpb{} {}, {}, [{}]", CondToString(cond), RegToString(t), RegToString(t2), RegToString(n)); } // Status register access instructions std::string arm_CPS() { return "ice"; } std::string arm_MRS(Cond cond, Reg d) { - return Common::StringFromFormat("mrs%s %s, apsr", CondToString(cond), RegToString(d)); + return fmt::format("mrs{} {}, apsr", CondToString(cond), RegToString(d)); } std::string arm_MSR_imm(Cond cond, int mask, int rotate, Imm8 imm8) { bool write_nzcvq = Common::Bit<1>(mask); bool write_g = Common::Bit<0>(mask); - return Common::StringFromFormat("msr%s apsr_%s%s, #%u", CondToString(cond), write_nzcvq ? "nzcvq" : "", write_g ? "g" : "", ArmExpandImm(rotate, imm8)); + return fmt::format("msr{} apsr_{}{}, #{}", CondToString(cond), write_nzcvq ? "nzcvq" : "", write_g ? "g" : "", ArmExpandImm(rotate, imm8)); } std::string arm_MSR_reg(Cond cond, int mask, Reg n) { bool write_nzcvq = Common::Bit<1>(mask); bool write_g = Common::Bit<0>(mask); - return Common::StringFromFormat("msr%s apsr_%s%s, %s", CondToString(cond), write_nzcvq ? "nzcvq" : "", write_g ? "g" : "", RegToString(n)); + return fmt::format("msr{} apsr_{}{}, {}", CondToString(cond), write_nzcvq ? "nzcvq" : "", write_g ? "g" : "", RegToString(n)); } std::string arm_RFE() { return "ice"; } std::string arm_SETEND(bool E) { @@ -788,149 +790,149 @@ public: // Floating point arithmetic instructions std::string vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { - return Common::StringFromFormat("vadd%s.%s %s, %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vn, N).c_str(), FPRegStr(sz, Vm, M).c_str()); + return fmt::format("vadd{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); } std::string vfp2_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { - return Common::StringFromFormat("vsub%s.%s %s, %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vn, N).c_str(), FPRegStr(sz, Vm, M).c_str()); + return fmt::format("vsub{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); } std::string vfp2_VMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { - return Common::StringFromFormat("vmul%s.%s %s, %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vn, N).c_str(), FPRegStr(sz, Vm, M).c_str()); + return fmt::format("vmul{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); } std::string vfp2_VMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { - return Common::StringFromFormat("vmla%s.%s %s, %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vn, N).c_str(), FPRegStr(sz, Vm, M).c_str()); + return fmt::format("vmla{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); } std::string vfp2_VMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { - return Common::StringFromFormat("vmls%s.%s %s, %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vn, N).c_str(), FPRegStr(sz, Vm, M).c_str()); + return fmt::format("vmls{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); } std::string vfp2_VNMUL(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { - return Common::StringFromFormat("vnmul%s.%s %s, %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vn, N).c_str(), FPRegStr(sz, Vm, M).c_str()); + return fmt::format("vnmul{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); } std::string vfp2_VNMLA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { - return Common::StringFromFormat("vnmla%s.%s %s, %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vn, N).c_str(), FPRegStr(sz, Vm, M).c_str()); + return fmt::format("vnmla{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); } std::string vfp2_VNMLS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { - return Common::StringFromFormat("vnmls%s.%s %s, %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vn, N).c_str(), FPRegStr(sz, Vm, M).c_str()); + return fmt::format("vnmls{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); } std::string vfp2_VDIV(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) { - return Common::StringFromFormat("vdiv%s.%s %s, %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vn, N).c_str(), FPRegStr(sz, Vm, M).c_str()); + return fmt::format("vdiv{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M)); } std::string vfp2_VMOV_u32_f64(Cond cond, size_t Vd, Reg t, bool D){ - return Common::StringFromFormat("vmov%s.32 %s, %s", CondToString(cond), FPRegStr(true, Vd, D).c_str(), RegToString(t)); + return fmt::format("vmov{}.32 {}, {}", CondToString(cond), FPRegStr(true, Vd, D), RegToString(t)); } std::string vfp2_VMOV_f64_u32(Cond cond, size_t Vn, Reg t, bool N){ - return Common::StringFromFormat("vmov%s.32 %s, %s", CondToString(cond), RegToString(t), FPRegStr(true, Vn, N).c_str()); + return fmt::format("vmov{}.32 {}, {}", CondToString(cond), RegToString(t), FPRegStr(true, Vn, N)); } std::string vfp2_VMOV_u32_f32(Cond cond, size_t Vn, Reg t, bool N){ - return Common::StringFromFormat("vmov%s.32 %s, %s", CondToString(cond), FPRegStr(false, Vn, N).c_str(), RegToString(t)); + return fmt::format("vmov{}.32 {}, {}", CondToString(cond), FPRegStr(false, Vn, N), RegToString(t)); } std::string vfp2_VMOV_f32_u32(Cond cond, size_t Vn, Reg t, bool N){ - return Common::StringFromFormat("vmov%s.32 %s, %s", CondToString(cond), RegToString(t), FPRegStr(false, Vn, N).c_str()); + return fmt::format("vmov{}.32 {}, {}", CondToString(cond), RegToString(t), FPRegStr(false, Vn, N)); } std::string vfp2_VMOV_2u32_2f32(Cond cond, Reg t2, Reg t, bool M, size_t Vm){ - return Common::StringFromFormat("vmov%s %s, %s, %s, %s", CondToString(cond), FPRegStr(false, Vm, M).c_str(), FPNextRegStr(false, Vm, M).c_str(), RegToString(t), RegToString(t2)); + return fmt::format("vmov{} {}, {}, {}, {}", CondToString(cond), FPRegStr(false, Vm, M), FPNextRegStr(false, Vm, M), RegToString(t), RegToString(t2)); } std::string vfp2_VMOV_2f32_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm){ - return Common::StringFromFormat("vmov%s %s, %s, %s, %s", CondToString(cond), RegToString(t), RegToString(t2), FPRegStr(false, Vm, M).c_str(), FPNextRegStr(false, Vm, M).c_str()); + return fmt::format("vmov{} {}, {}, {}, {}", CondToString(cond), RegToString(t), RegToString(t2), FPRegStr(false, Vm, M), FPNextRegStr(false, Vm, M)); } std::string vfp2_VMOV_2u32_f64(Cond cond, Reg t2, Reg t, bool M, size_t Vm){ - return Common::StringFromFormat("vmov%s %s, %s, %s", CondToString(cond), FPRegStr(true, Vm, M).c_str(), RegToString(t), RegToString(t2)); + return fmt::format("vmov{} {}, {}, {}", CondToString(cond), FPRegStr(true, Vm, M), RegToString(t), RegToString(t2)); } std::string vfp2_VMOV_f64_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm){ - return Common::StringFromFormat("vmov%s %s, %s, %s", CondToString(cond), RegToString(t), RegToString(t2), FPRegStr(true, Vm, M).c_str()); + return fmt::format("vmov{} {}, {}, {}", CondToString(cond), RegToString(t), RegToString(t2), FPRegStr(true, Vm, M)); } std::string vfp2_VMOV_reg(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm){ - return Common::StringFromFormat("vmov%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str()); + return fmt::format("vmov{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M)); } std::string vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { - return Common::StringFromFormat("vadd%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str()); + return fmt::format("vadd{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M)); } std::string vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { - return Common::StringFromFormat("vneg%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str()); + return fmt::format("vneg{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M)); } std::string vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { - return Common::StringFromFormat("vsqrt%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str()); + return fmt::format("vsqrt{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M)); } std::string vfp2_VCVT_f_to_f(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { - return Common::StringFromFormat("vcvt%s.%s.%s %s, %s", CondToString(cond), !sz ? "f64" : "f32", sz ? "f64" : "f32", FPRegStr(!sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str()); + return fmt::format("vcvt{}.{}.{} {}, {}", CondToString(cond), !sz ? "f64" : "f32", sz ? "f64" : "f32", FPRegStr(!sz, Vd, D), FPRegStr(sz, Vm, M)); } std::string vfp2_VCVT_to_float(Cond cond, bool D, size_t Vd, bool sz, bool is_signed, bool M, size_t Vm) { - return Common::StringFromFormat("vcvt%s.%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", is_signed ? "s32" : "u32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(false, Vm, M).c_str()); + return fmt::format("vcvt{}.{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", is_signed ? "s32" : "u32", FPRegStr(sz, Vd, D), FPRegStr(false, Vm, M)); } std::string vfp2_VCVT_to_u32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm) { - return Common::StringFromFormat("vcvt%s%s.u32.%s %s, %s", round_towards_zero ? "" : "r", CondToString(cond), sz ? "f64" : "f32", FPRegStr(false, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str()); + return fmt::format("vcvt{}{}.u32.{} {}, {}", round_towards_zero ? "" : "r", CondToString(cond), sz ? "f64" : "f32", FPRegStr(false, Vd, D), FPRegStr(sz, Vm, M)); } std::string vfp2_VCVT_to_s32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm) { - return Common::StringFromFormat("vcvt%s%s.s32.%s %s, %s", round_towards_zero ? "" : "r", CondToString(cond), sz ? "f64" : "f32", FPRegStr(false, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str()); + return fmt::format("vcvt{}{}.s32.{} {}, {}", round_towards_zero ? "" : "r", CondToString(cond), sz ? "f64" : "f32", FPRegStr(false, Vd, D), FPRegStr(sz, Vm, M)); } std::string vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) { - return Common::StringFromFormat("vpop%s %s(+%u)", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), imm8 >> (sz ? 1 : 0)); + return fmt::format("vpop{} {}(+{})", CondToString(cond), FPRegStr(sz, Vd, D), imm8 >> (sz ? 1 : 0)); } std::string vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) { - return Common::StringFromFormat("vpush%s %s(+%u)", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), imm8 >> (sz ? 1 : 0)); + return fmt::format("vpush{} {}(+{})", CondToString(cond), FPRegStr(sz, Vd, D), imm8 >> (sz ? 1 : 0)); } std::string vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8) { u32 imm32 = imm8 << 2; - return Common::StringFromFormat("vldr%s %s, [%s, #%c%u]", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), RegToString(n), U ? '+' : '-', imm32); + return fmt::format("vldr{} {}, [{}, #{}{}]", CondToString(cond), FPRegStr(sz, Vd, D), RegToString(n), U ? '+' : '-', imm32); } std::string vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8) { u32 imm32 = imm8 << 2; - return Common::StringFromFormat("vstr%s %s, [%s, #%c%u]", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), RegToString(n), U ? '+' : '-', imm32); + return fmt::format("vstr{} {}, [{}, #{}{}]", CondToString(cond), FPRegStr(sz, Vd, D), RegToString(n), U ? '+' : '-', imm32); } std::string vfp2_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8) { const char* mode = ""; if (!p && u) mode = "ia"; if (p && !u) mode = "db"; - return Common::StringFromFormat("vstm%s%s.f64 %s%s, %s(+%u)", mode, CondToString(cond), RegToString(n), w ? "!" : "", FPRegStr(true, Vd, D).c_str(), imm8); + return fmt::format("vstm{}{}.f64 {}{}, {}(+{})", mode, CondToString(cond), RegToString(n), w ? "!" : "", FPRegStr(true, Vd, D), imm8); } std::string vfp2_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8) { const char* mode = ""; if (!p && u) mode = "ia"; if (p && !u) mode = "db"; - return Common::StringFromFormat("vstm%s%s.f32 %s%s, %s(+%u)", mode, CondToString(cond), RegToString(n), w ? "!" : "", FPRegStr(false, Vd, D).c_str(), imm8); + return fmt::format("vstm{}{}.f32 {}{}, {}(+{})", mode, CondToString(cond), RegToString(n), w ? "!" : "", FPRegStr(false, Vd, D), imm8); } std::string vfp2_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8) { const char* mode = ""; if (!p && u) mode = "ia"; if (p && !u) mode = "db"; - return Common::StringFromFormat("vldm%s%s.f64 %s%s, %s(+%u)", mode, CondToString(cond), RegToString(n), w ? "!" : "", FPRegStr(true, Vd, D).c_str(), imm8); + return fmt::format("vldm{}{}.f64 {}{}, {}(+{})", mode, CondToString(cond), RegToString(n), w ? "!" : "", FPRegStr(true, Vd, D), imm8); } std::string vfp2_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8) { const char* mode = ""; if (!p && u) mode = "ia"; if (p && !u) mode = "db"; - return Common::StringFromFormat("vldm%s%s.f32 %s%s, %s(+%u)", mode, CondToString(cond), RegToString(n), w ? "!" : "", FPRegStr(false, Vd, D).c_str(), imm8); + return fmt::format("vldm{}{}.f32 {}{}, {}(+{})", mode, CondToString(cond), RegToString(n), w ? "!" : "", FPRegStr(false, Vd, D), imm8); } }; @@ -942,7 +944,7 @@ std::string DisassembleArm(u32 instruction) { } else if (auto decoder = DecodeArm(instruction)) { return decoder->call(visitor, instruction); } else { - return Common::StringFromFormat("UNKNOWN: %x", instruction); + return fmt::format("UNKNOWN: {:x}", instruction); } } diff --git a/src/frontend/disassembler/disassembler_thumb.cpp b/src/frontend/disassembler/disassembler_thumb.cpp index d9938b06..9b107f32 100644 --- a/src/frontend/disassembler/disassembler_thumb.cpp +++ b/src/frontend/disassembler/disassembler_thumb.cpp @@ -7,6 +7,8 @@ #include #include +#include + #include "common/bit_util.h" #include "common/string_util.h" #include "frontend/arm_types.h" @@ -18,236 +20,236 @@ namespace Arm { class DisassemblerVisitor { public: std::string thumb16_LSL_imm(Imm5 imm5, Reg m, Reg d) { - return Common::StringFromFormat("lsls %s, %s, #%u", RegToString(d), RegToString(m), imm5); + return fmt::format("lsls {}, {}, #{}", RegToString(d), RegToString(m), imm5); } std::string thumb16_LSR_imm(Imm5 imm5, Reg m, Reg d) { - return Common::StringFromFormat("lsrs %s, %s, #%u", RegToString(d), RegToString(m), imm5 != 0 ? imm5 : 32); + return fmt::format("lsrs {}, {}, #{}", RegToString(d), RegToString(m), imm5 != 0 ? imm5 : 32); } std::string thumb16_ASR_imm(Imm5 imm5, Reg m, Reg d) { - return Common::StringFromFormat("asrs %s, %s, #%u", RegToString(d), RegToString(m), imm5 != 0 ? imm5 : 32); + return fmt::format("asrs {}, {}, #{}", RegToString(d), RegToString(m), imm5 != 0 ? imm5 : 32); } std::string thumb16_ADD_reg_t1(Reg m, Reg n, Reg d) { - return Common::StringFromFormat("adds %s, %s, %s", RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("adds {}, {}, {}", RegToString(d), RegToString(n), RegToString(m)); } std::string thumb16_SUB_reg(Reg m, Reg n, Reg d) { - return Common::StringFromFormat("subs %s, %s, %s", RegToString(d), RegToString(n), RegToString(m)); + return fmt::format("subs {}, {}, {}", RegToString(d), RegToString(n), RegToString(m)); } std::string thumb16_ADD_imm_t1(Imm3 imm3, Reg n, Reg d) { - return Common::StringFromFormat("adds %s, %s, #%u", RegToString(d), RegToString(n), imm3); + return fmt::format("adds {}, {}, #{}", RegToString(d), RegToString(n), imm3); } std::string thumb16_SUB_imm_t1(Imm3 imm3, Reg n, Reg d) { - return Common::StringFromFormat("subs %s, %s, #%u", RegToString(d), RegToString(n), imm3); + return fmt::format("subs {}, {}, #{}", RegToString(d), RegToString(n), imm3); } std::string thumb16_MOV_imm(Reg d, Imm8 imm8) { - return Common::StringFromFormat("movs %s, #%u", RegToString(d), imm8); + return fmt::format("movs {}, #{}", RegToString(d), imm8); } std::string thumb16_CMP_imm(Reg n, Imm8 imm8) { - return Common::StringFromFormat("cmp %s, #%u", RegToString(n), imm8); + return fmt::format("cmp {}, #{}", RegToString(n), imm8); } std::string thumb16_ADD_imm_t2(Reg d_n, Imm8 imm8) { - return Common::StringFromFormat("adds %s, #%u", RegToString(d_n), imm8); + return fmt::format("adds {}, #{}", RegToString(d_n), imm8); } std::string thumb16_SUB_imm_t2(Reg d_n, Imm8 imm8) { - return Common::StringFromFormat("subs %s, #%u", RegToString(d_n), imm8); + return fmt::format("subs {}, #{}", RegToString(d_n), imm8); } std::string thumb16_AND_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("ands %s, %s", RegToString(d_n), RegToString(m)); + return fmt::format("ands {}, {}", RegToString(d_n), RegToString(m)); } std::string thumb16_EOR_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("eors %s, %s", RegToString(d_n), RegToString(m)); + return fmt::format("eors {}, {}", RegToString(d_n), RegToString(m)); } std::string thumb16_LSL_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("lsls %s, %s", RegToString(d_n), RegToString(m)); + return fmt::format("lsls {}, {}", RegToString(d_n), RegToString(m)); } std::string thumb16_LSR_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("lsrs %s, %s", RegToString(d_n), RegToString(m)); + return fmt::format("lsrs {}, {}", RegToString(d_n), RegToString(m)); } std::string thumb16_ASR_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("asrs %s, %s", RegToString(d_n), RegToString(m)); + return fmt::format("asrs {}, {}", RegToString(d_n), RegToString(m)); } std::string thumb16_ADC_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("adcs %s, %s", RegToString(d_n), RegToString(m)); + return fmt::format("adcs {}, {}", RegToString(d_n), RegToString(m)); } std::string thumb16_SBC_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("sbcs %s, %s", RegToString(d_n), RegToString(m)); + return fmt::format("sbcs {}, {}", RegToString(d_n), RegToString(m)); } std::string thumb16_ROR_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("rors %s, %s", RegToString(d_n), RegToString(m)); + return fmt::format("rors {}, {}", RegToString(d_n), RegToString(m)); } std::string thumb16_TST_reg(Reg m, Reg n) { - return Common::StringFromFormat("tst %s, %s", RegToString(n), RegToString(m)); + return fmt::format("tst {}, {}", RegToString(n), RegToString(m)); } std::string thumb16_RSB_imm(Reg n, Reg d) { // Pre-UAL syntax: NEGS , - return Common::StringFromFormat("rsbs %s, %s, #0", RegToString(d), RegToString(n)); + return fmt::format("rsbs {}, {}, #0", RegToString(d), RegToString(n)); } std::string thumb16_CMP_reg_t1(Reg m, Reg n) { - return Common::StringFromFormat("cmp %s, %s", RegToString(n), RegToString(m)); + return fmt::format("cmp {}, {}", RegToString(n), RegToString(m)); } std::string thumb16_CMN_reg(Reg m, Reg n) { - return Common::StringFromFormat("cmn %s, %s", RegToString(n), RegToString(m)); + return fmt::format("cmn {}, {}", RegToString(n), RegToString(m)); } std::string thumb16_ORR_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("orrs %s, %s", RegToString(d_n), RegToString(m)); + return fmt::format("orrs {}, {}", RegToString(d_n), RegToString(m)); } std::string thumb16_BIC_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("bics %s, %s", RegToString(d_n), RegToString(m)); + return fmt::format("bics {}, {}", RegToString(d_n), RegToString(m)); } std::string thumb16_MVN_reg(Reg m, Reg d) { - return Common::StringFromFormat("mvns %s, %s", RegToString(d), RegToString(m)); + return fmt::format("mvns {}, {}", RegToString(d), RegToString(m)); } std::string thumb16_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) { Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo; - return Common::StringFromFormat("add %s, %s", RegToString(d_n), RegToString(m)); + return fmt::format("add {}, {}", RegToString(d_n), RegToString(m)); } std::string thumb16_CMP_reg_t2(bool n_hi, Reg m, Reg n_lo) { Reg n = n_hi ? (n_lo + 8) : n_lo; - return Common::StringFromFormat("cmp %s, %s", RegToString(n), RegToString(m)); + return fmt::format("cmp {}, {}", RegToString(n), RegToString(m)); } std::string thumb16_MOV_reg(bool d_hi, Reg m, Reg d_lo) { Reg d = d_hi ? (d_lo + 8) : d_lo; - return Common::StringFromFormat("mov %s, %s", RegToString(d), RegToString(m)); + return fmt::format("mov {}, {}", RegToString(d), RegToString(m)); } std::string thumb16_LDR_literal(Reg t, Imm8 imm8) { u32 imm32 = imm8 << 2; - return Common::StringFromFormat("ldr %s, [pc, #%u]", RegToString(t), imm32); + return fmt::format("ldr {}, [pc, #{}]", RegToString(t), imm32); } std::string thumb16_STR_reg(Reg m, Reg n, Reg t) { - return Common::StringFromFormat("str %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); + return fmt::format("str {}, [{}, {}]", RegToString(t), RegToString(n), RegToString(m)); } std::string thumb16_STRH_reg(Reg m, Reg n, Reg t) { - return Common::StringFromFormat("strh %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); + return fmt::format("strh {}, [{}, {}]", RegToString(t), RegToString(n), RegToString(m)); } std::string thumb16_STRB_reg(Reg m, Reg n, Reg t) { - return Common::StringFromFormat("strb %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); + return fmt::format("strb {}, [{}, {}]", RegToString(t), RegToString(n), RegToString(m)); } std::string thumb16_LDRSB_reg(Reg m, Reg n, Reg t) { - return Common::StringFromFormat("ldrsb %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); + return fmt::format("ldrsb {}, [{}, {}]", RegToString(t), RegToString(n), RegToString(m)); } std::string thumb16_LDR_reg(Reg m, Reg n, Reg t) { - return Common::StringFromFormat("ldr %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); + return fmt::format("ldr {}, [{}, {}]", RegToString(t), RegToString(n), RegToString(m)); } std::string thumb16_LDRH_reg(Reg m, Reg n, Reg t) { - return Common::StringFromFormat("ldrh %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); + return fmt::format("ldrh {}, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); } std::string thumb16_LDRB_reg(Reg m, Reg n, Reg t) { - return Common::StringFromFormat("ldrb %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); + return fmt::format("ldrb {}, [{}, {}]", RegToString(t), RegToString(n), RegToString(m)); } std::string thumb16_LDRSH_reg(Reg m, Reg n, Reg t) { - return Common::StringFromFormat("ldrsh %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); + return fmt::format("ldrsh {}, [{}, {}]", RegToString(t), RegToString(n), RegToString(m)); } std::string thumb16_STR_imm_t1(Imm5 imm5, Reg n, Reg t) { u32 imm32 = imm5 << 2; - return Common::StringFromFormat("str %s, [%s, #%u]", RegToString(t), RegToString(n), imm32); + return fmt::format("str {}, [{}, #{}]", RegToString(t), RegToString(n), imm32); } std::string thumb16_LDR_imm_t1(Imm5 imm5, Reg n, Reg t) { u32 imm32 = imm5 << 2; - return Common::StringFromFormat("ldr %s, [%s, #%u]", RegToString(t), RegToString(n), imm32); + return fmt::format("ldr {}, [{}, #{}]", RegToString(t), RegToString(n), imm32); } std::string thumb16_STRB_imm(Imm5 imm5, Reg n, Reg t) { u32 imm32 = imm5; - return Common::StringFromFormat("strb %s, [%s, #%u]", RegToString(t), RegToString(n), imm32); + return fmt::format("strb {}, [{}, #{}]", RegToString(t), RegToString(n), imm32); } std::string thumb16_LDRB_imm(Imm5 imm5, Reg n, Reg t) { u32 imm32 = imm5; - return Common::StringFromFormat("ldrb %s, [%s, #%u]", RegToString(t), RegToString(n), imm32); + return fmt::format("ldrb {}, [{}, #{}]", RegToString(t), RegToString(n), imm32); } std::string thumb16_STRH_imm(Imm5 imm5, Reg n, Reg t) { u32 imm32 = imm5 << 1; - return Common::StringFromFormat("strh %s, [%s, #%u]", RegToString(t), RegToString(n), imm32); + return fmt::format("strh {}, [{}, #{}]", RegToString(t), RegToString(n), imm32); } std::string thumb16_LDRH_imm(Imm5 imm5, Reg n, Reg t) { u32 imm32 = imm5 << 1; - return Common::StringFromFormat("ldrh %s, [%s, #%u]", RegToString(t), RegToString(n), imm32); + return fmt::format("ldrh {}, [{}, #{}]", RegToString(t), RegToString(n), imm32); } std::string thumb16_STR_imm_t2(Reg t, Imm5 imm5) { u32 imm32 = imm5 << 2; - return Common::StringFromFormat("str %s, [sp, #%u]", RegToString(t), imm32); + return fmt::format("str {}, [sp, #{}]", RegToString(t), imm32); } std::string thumb16_LDR_imm_t2(Reg t, Imm5 imm5) { u32 imm32 = imm5 << 2; - return Common::StringFromFormat("ldr %s, [sp, #%u]", RegToString(t), imm32); + return fmt::format("ldr {}, [sp, #{}]", RegToString(t), imm32); } std::string thumb16_ADR(Reg d, Imm8 imm8) { u32 imm32 = imm8 << 2; - return Common::StringFromFormat("adr %s, +#%u", RegToString(d), imm32); + return fmt::format("adr {}, +#{}", RegToString(d), imm32); } std::string thumb16_ADD_sp_t1(Reg d, Imm8 imm8) { u32 imm32 = imm8 << 2; - return Common::StringFromFormat("add %s, sp, #%u", RegToString(d), imm32); + return fmt::format("add {}, sp, #{}", RegToString(d), imm32); } std::string thumb16_ADD_sp_t2(Imm7 imm7) { u32 imm32 = imm7 << 2; - return Common::StringFromFormat("add sp, sp, #%u", imm32); + return fmt::format("add sp, sp, #{}", imm32); } std::string thumb16_SUB_sp(Imm7 imm7) { u32 imm32 = imm7 << 2; - return Common::StringFromFormat("sub sp, sp, #%u", imm32); + return fmt::format("sub sp, sp, #{}", imm32); } std::string thumb16_SXTH(Reg m, Reg d) { - return Common::StringFromFormat("sxth %s, %s", RegToString(d), RegToString(m)); + return fmt::format("sxth {}, {}", RegToString(d), RegToString(m)); } std::string thumb16_SXTB(Reg m, Reg d) { - return Common::StringFromFormat("sxtb %s, %s", RegToString(d), RegToString(m)); + return fmt::format("sxtb {}, {}", RegToString(d), RegToString(m)); } std::string thumb16_UXTH(Reg m, Reg d) { - return Common::StringFromFormat("uxth %s, %s", RegToString(d), RegToString(m)); + return fmt::format("uxth {}, {}", RegToString(d), RegToString(m)); } std::string thumb16_UXTB(Reg m, Reg d) { - return Common::StringFromFormat("uxtb %s, %s", RegToString(d), RegToString(m)); + return fmt::format("uxtb {}, {}", RegToString(d), RegToString(m)); } std::string thumb16_PUSH(bool M, RegList reg_list) { @@ -261,61 +263,61 @@ public: } std::string thumb16_SETEND(bool E) { - return Common::StringFromFormat("setend %s", E ? "BE" : "LE"); + return fmt::format("setend {}", E ? "BE" : "LE"); } std::string thumb16_REV(Reg m, Reg d) { - return Common::StringFromFormat("rev %s, %s", RegToString(d), RegToString(m)); + return fmt::format("rev {}, {}", RegToString(d), RegToString(m)); } std::string thumb16_REV16(Reg m, Reg d) { - return Common::StringFromFormat("rev16 %s, %s", RegToString(d), RegToString(m)); + return fmt::format("rev16 {}, {}", RegToString(d), RegToString(m)); } std::string thumb16_REVSH(Reg m, Reg d) { - return Common::StringFromFormat("revsh %s, %s", RegToString(d), RegToString(m)); + return fmt::format("revsh {}, {}", RegToString(d), RegToString(m)); } std::string thumb16_STMIA(Reg n, RegList reg_list) { - return Common::StringFromFormat("stm %s!, %s", RegToString(n), RegListToString(reg_list).c_str()); + return fmt::format("stm {}!, {}", RegToString(n), RegListToString(reg_list)); } std::string thumb16_LDMIA(Reg n, RegList reg_list) { - bool write_back = !Dynarmic::Common::Bit(static_cast(n), reg_list); - return Common::StringFromFormat("ldm %s%s, %s", RegToString(n), write_back ? "!" : "", RegListToString(reg_list).c_str()); + bool write_back = !Common::Bit(static_cast(n), reg_list); + return fmt::format("ldm {}{}, {}", RegToString(n), write_back ? "!" : "", RegListToString(reg_list)); } std::string thumb16_BX(Reg m) { - return Common::StringFromFormat("bx %s", RegToString(m)); + return fmt::format("bx {}", RegToString(m)); } std::string thumb16_BLX_reg(Reg m) { - return Common::StringFromFormat("blx %s", RegToString(m)); + return fmt::format("blx {}", RegToString(m)); } std::string thumb16_UDF() { - return Common::StringFromFormat("udf"); + return fmt::format("udf"); } std::string thumb16_SVC(Imm8 imm8) { - return Common::StringFromFormat("svc #%u", imm8); + return fmt::format("svc #{}", imm8); } std::string thumb16_B_t1(Cond cond, Imm8 imm8) { s32 imm32 = Common::SignExtend<9, s32>(imm8 << 1) + 4; - return Common::StringFromFormat("b%s %c#%u", CondToString(cond), Common::SignToChar(imm32), abs(imm32)); + return fmt::format("b{} {}#{}", CondToString(cond), Common::SignToChar(imm32), abs(imm32)); } std::string thumb16_B_t2(Imm11 imm11) { s32 imm32 = Common::SignExtend<12, s32>(imm11 << 1) + 4; - return Common::StringFromFormat("b %c#%u", Common::SignToChar(imm32), abs(imm32)); + return fmt::format("b {}#{}", Common::SignToChar(imm32), abs(imm32)); } }; std::string DisassembleThumb16(u16 instruction) { DisassemblerVisitor visitor; auto decoder = DecodeThumb16(instruction); - return !decoder ? Common::StringFromFormat("UNKNOWN: %x", instruction) : decoder->call(visitor, instruction); + return !decoder ? fmt::format("UNKNOWN: {:x}", instruction) : decoder->call(visitor, instruction); } } // namespace Arm diff --git a/src/frontend/ir/basic_block.cpp b/src/frontend/ir/basic_block.cpp index 63f857e5..78bfe1bc 100644 --- a/src/frontend/ir/basic_block.cpp +++ b/src/frontend/ir/basic_block.cpp @@ -9,8 +9,9 @@ #include #include +#include + #include "common/assert.h" -#include "common/string_util.h" #include "frontend/ir/basic_block.h" #include "frontend/ir/opcodes.h" @@ -91,40 +92,40 @@ const size_t& Block::CycleCount() const { } static std::string LocDescToString(const Arm::LocationDescriptor& loc) { - return Common::StringFromFormat("{%u,%s,%s,%u}", - loc.PC(), - loc.TFlag() ? "T" : "!T", - loc.EFlag() ? "E" : "!E", - loc.FPSCR().Value()); + return fmt::format("{{{},{},{},{}}}", + loc.PC(), + loc.TFlag() ? "T" : "!T", + loc.EFlag() ? "E" : "!E", + loc.FPSCR().Value()); } static std::string TerminalToString(const Terminal& terminal_variant) { switch (terminal_variant.which()) { case 1: { auto terminal = boost::get(terminal_variant); - return Common::StringFromFormat("Interpret{%s}", LocDescToString(terminal.next).c_str()); + return fmt::format("Interpret{{{}}}", LocDescToString(terminal.next)); } case 2: { - return Common::StringFromFormat("ReturnToDispatch{}"); + return "ReturnToDispatch{}"; } case 3: { auto terminal = boost::get(terminal_variant); - return Common::StringFromFormat("LinkBlock{%s}", LocDescToString(terminal.next).c_str()); + return fmt::format("LinkBlock{{{}}}", LocDescToString(terminal.next)); } case 4: { auto terminal = boost::get(terminal_variant); - return Common::StringFromFormat("LinkBlockFast{%s}", LocDescToString(terminal.next).c_str()); + return fmt::format("LinkBlockFast{{{}}}", LocDescToString(terminal.next)); } case 5: { - return Common::StringFromFormat("PopRSBHint{}"); + return "PopRSBHint{}"; } case 6: { auto terminal = boost::get(terminal_variant); - return Common::StringFromFormat("If{%s, %s, %s}", CondToString(terminal.if_), TerminalToString(terminal.then_).c_str(), TerminalToString(terminal.else_).c_str()); + return fmt::format("If{{{}, {}, {}}}", CondToString(terminal.if_), TerminalToString(terminal.then_), TerminalToString(terminal.else_)); } case 7: { auto terminal = boost::get(terminal_variant); - return Common::StringFromFormat("CheckHalt{%s}", TerminalToString(terminal.else_).c_str()); + return fmt::format("CheckHalt{{{}}}", TerminalToString(terminal.else_)); } default: return ""; @@ -134,13 +135,13 @@ static std::string TerminalToString(const Terminal& terminal_variant) { std::string DumpBlock(const IR::Block& block) { std::string ret; - ret += Common::StringFromFormat("Block: location=%s\n", LocDescToString(block.Location()).c_str()); - ret += Common::StringFromFormat("cycles=%zu", block.CycleCount()); - ret += Common::StringFromFormat(", entry_cond=%s", Arm::CondToString(block.GetCondition(), true)); + ret += fmt::format("Block: location={}\n", LocDescToString(block.Location())); + ret += fmt::format("cycles={}", block.CycleCount()); + ret += fmt::format(", entry_cond={}", Arm::CondToString(block.GetCondition(), true)); if (block.GetCondition() != Arm::Cond::AL) { - ret += Common::StringFromFormat(", cond_fail=%s", LocDescToString(block.ConditionFailedLocation()).c_str()); + ret += fmt::format(", cond_fail={}", LocDescToString(block.ConditionFailedLocation())); } - ret += "\n"; + ret += '\n'; std::map inst_to_index; size_t index = 0; @@ -149,15 +150,15 @@ std::string DumpBlock(const IR::Block& block) { if (arg.IsEmpty()) { return ""; } else if (!arg.IsImmediate()) { - return Common::StringFromFormat("%%%zu", inst_to_index.at(arg.GetInst())); + return fmt::format("%{}", inst_to_index.at(arg.GetInst())); } switch (arg.GetType()) { case Type::U1: - return Common::StringFromFormat("#%s", arg.GetU1() ? "1" : "0"); + return fmt::format("#{}", arg.GetU1() ? '1' : '0'); case Type::U8: - return Common::StringFromFormat("#%u", arg.GetU8()); + return fmt::format("#{}", arg.GetU8()); case Type::U32: - return Common::StringFromFormat("#%#x", arg.GetU32()); + return fmt::format("#{:#x}", arg.GetU32()); case Type::RegRef: return Arm::RegToString(arg.GetRegRef()); case Type::ExtRegRef: @@ -171,7 +172,7 @@ std::string DumpBlock(const IR::Block& block) { const Opcode op = inst.GetOpcode(); if (GetTypeOf(op) != Type::Void) { - ret += Common::StringFromFormat("%%%-5zu = ", index); + ret += fmt::format("%{:<5} = ", index); } else { ret += " "; // '%00000 = ' -> 1 + 5 + 3 = 9 spaces } @@ -188,15 +189,15 @@ std::string DumpBlock(const IR::Block& block) { Type actual_type = arg.GetType(); Type expected_type = GetArgTypeOf(op, arg_index); if (!AreTypesCompatible(actual_type, expected_type)) { - ret += Common::StringFromFormat("", GetNameOf(actual_type), GetNameOf(expected_type)); + ret += fmt::format("", GetNameOf(actual_type), GetNameOf(expected_type)); } } - ret += "\n"; + ret += '\n'; inst_to_index[&inst] = index++; } - ret += "terminal = " + TerminalToString(block.GetTerminal()) + "\n"; + ret += "terminal = " + TerminalToString(block.GetTerminal()) + '\n'; return ret; }