From 033e8b9b1e8586c6d3dae125fac7802b8fbbd7d2 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sun, 5 Feb 2017 20:49:41 +0000 Subject: [PATCH] vfp: Rename variables a, b, c to more sensible names --- src/frontend/translate/translate_arm/vfp2.cpp | 146 +++++++++--------- 1 file changed, 73 insertions(+), 73 deletions(-) diff --git a/src/frontend/translate/translate_arm/vfp2.cpp b/src/frontend/translate/translate_arm/vfp2.cpp index ea7ce5c0..6b9aad1b 100644 --- a/src/frontend/translate/translate_arm/vfp2.cpp +++ b/src/frontend/translate/translate_arm/vfp2.cpp @@ -26,11 +26,11 @@ bool ArmTranslatorVisitor::vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bo ExtReg m = ToExtReg(sz, Vm, M); // VADD.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m> if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(n); - auto b = ir.GetExtendedRegister(m); + auto reg_n = ir.GetExtendedRegister(n); + auto reg_m = ir.GetExtendedRegister(m); auto result = sz - ? ir.FPAdd64(a, b, true) - : ir.FPAdd32(a, b, true); + ? ir.FPAdd64(reg_n, reg_m, true) + : ir.FPAdd32(reg_n, reg_m, true); ir.SetExtendedRegister(d, result); } return true; @@ -45,11 +45,11 @@ bool ArmTranslatorVisitor::vfp2_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bo ExtReg m = ToExtReg(sz, Vm, M); // VSUB.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m> if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(n); - auto b = ir.GetExtendedRegister(m); + auto reg_n = ir.GetExtendedRegister(n); + auto reg_m = ir.GetExtendedRegister(m); auto result = sz - ? ir.FPSub64(a, b, true) - : ir.FPSub32(a, b, true); + ? ir.FPSub64(reg_n, reg_m, true) + : ir.FPSub32(reg_n, reg_m, true); ir.SetExtendedRegister(d, result); } return true; @@ -64,11 +64,11 @@ bool ArmTranslatorVisitor::vfp2_VMUL(Cond cond, bool D, size_t Vn, size_t Vd, bo ExtReg m = ToExtReg(sz, Vm, M); // VMUL.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m> if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(n); - auto b = ir.GetExtendedRegister(m); + auto reg_n = ir.GetExtendedRegister(n); + auto reg_m = ir.GetExtendedRegister(m); auto result = sz - ? ir.FPMul64(a, b, true) - : ir.FPMul32(a, b, true); + ? ir.FPMul64(reg_n, reg_m, true) + : ir.FPMul32(reg_n, reg_m, true); ir.SetExtendedRegister(d, result); } return true; @@ -83,12 +83,12 @@ bool ArmTranslatorVisitor::vfp2_VMLA(Cond cond, bool D, size_t Vn, size_t Vd, bo ExtReg m = ToExtReg(sz, Vm, M); // VMLA.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m> if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(n); - auto b = ir.GetExtendedRegister(m); - auto c = ir.GetExtendedRegister(d); + auto reg_n = ir.GetExtendedRegister(n); + auto reg_m = ir.GetExtendedRegister(m); + auto reg_d = ir.GetExtendedRegister(d); auto result = sz - ? ir.FPAdd64(c, ir.FPMul64(a, b, true), true) - : ir.FPAdd32(c, ir.FPMul32(a, b, true), true); + ? ir.FPAdd64(reg_d, ir.FPMul64(reg_n, reg_m, true), true) + : ir.FPAdd32(reg_d, ir.FPMul32(reg_n, reg_m, true), true); ir.SetExtendedRegister(d, result); } return true; @@ -103,12 +103,12 @@ bool ArmTranslatorVisitor::vfp2_VMLS(Cond cond, bool D, size_t Vn, size_t Vd, bo ExtReg m = ToExtReg(sz, Vm, M); // VMLS.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m> if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(n); - auto b = ir.GetExtendedRegister(m); - auto c = ir.GetExtendedRegister(d); + auto reg_n = ir.GetExtendedRegister(n); + auto reg_m = ir.GetExtendedRegister(m); + auto reg_d = ir.GetExtendedRegister(d); auto result = sz - ? ir.FPAdd64(c, ir.FPNeg64(ir.FPMul64(a, b, true)), true) - : ir.FPAdd32(c, ir.FPNeg32(ir.FPMul32(a, b, true)), true); + ? ir.FPAdd64(reg_d, ir.FPNeg64(ir.FPMul64(reg_n, reg_m, true)), true) + : ir.FPAdd32(reg_d, ir.FPNeg32(ir.FPMul32(reg_n, reg_m, true)), true); ir.SetExtendedRegister(d, result); } return true; @@ -123,11 +123,11 @@ bool ArmTranslatorVisitor::vfp2_VNMUL(Cond cond, bool D, size_t Vn, size_t Vd, b ExtReg m = ToExtReg(sz, Vm, M); // VNMUL.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m> if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(n); - auto b = ir.GetExtendedRegister(m); + auto reg_n = ir.GetExtendedRegister(n); + auto reg_m = ir.GetExtendedRegister(m); auto result = sz - ? ir.FPNeg64(ir.FPMul64(a, b, true)) - : ir.FPNeg32(ir.FPMul32(a, b, true)); + ? ir.FPNeg64(ir.FPMul64(reg_n, reg_m, true)) + : ir.FPNeg32(ir.FPMul32(reg_n, reg_m, true)); ir.SetExtendedRegister(d, result); } return true; @@ -142,12 +142,12 @@ bool ArmTranslatorVisitor::vfp2_VNMLA(Cond cond, bool D, size_t Vn, size_t Vd, b ExtReg m = ToExtReg(sz, Vm, M); // VNMLA.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m> if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(n); - auto b = ir.GetExtendedRegister(m); - auto c = ir.GetExtendedRegister(d); + auto reg_n = ir.GetExtendedRegister(n); + auto reg_m = ir.GetExtendedRegister(m); + auto reg_d = ir.GetExtendedRegister(d); auto result = sz - ? ir.FPAdd64(ir.FPNeg64(c), ir.FPNeg64(ir.FPMul64(a, b, true)), true) - : ir.FPAdd32(ir.FPNeg32(c), ir.FPNeg32(ir.FPMul32(a, b, true)), true); + ? ir.FPAdd64(ir.FPNeg64(reg_d), ir.FPNeg64(ir.FPMul64(reg_n, reg_m, true)), true) + : ir.FPAdd32(ir.FPNeg32(reg_d), ir.FPNeg32(ir.FPMul32(reg_n, reg_m, true)), true); ir.SetExtendedRegister(d, result); } return true; @@ -162,12 +162,12 @@ bool ArmTranslatorVisitor::vfp2_VNMLS(Cond cond, bool D, size_t Vn, size_t Vd, b ExtReg m = ToExtReg(sz, Vm, M); // VNMLS.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m> if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(n); - auto b = ir.GetExtendedRegister(m); - auto c = ir.GetExtendedRegister(d); + auto reg_n = ir.GetExtendedRegister(n); + auto reg_m = ir.GetExtendedRegister(m); + auto reg_d = ir.GetExtendedRegister(d); auto result = sz - ? ir.FPAdd64(ir.FPNeg64(c), ir.FPMul64(a, b, true), true) - : ir.FPAdd32(ir.FPNeg32(c), ir.FPMul32(a, b, true), true); + ? ir.FPAdd64(ir.FPNeg64(reg_d), ir.FPMul64(reg_n, reg_m, true), true) + : ir.FPAdd32(ir.FPNeg32(reg_d), ir.FPMul32(reg_n, reg_m, true), true); ir.SetExtendedRegister(d, result); } return true; @@ -182,11 +182,11 @@ bool ArmTranslatorVisitor::vfp2_VDIV(Cond cond, bool D, size_t Vn, size_t Vd, bo ExtReg m = ToExtReg(sz, Vm, M); // VDIV.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m> if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(n); - auto b = ir.GetExtendedRegister(m); + auto reg_n = ir.GetExtendedRegister(n); + auto reg_m = ir.GetExtendedRegister(m); auto result = sz - ? ir.FPDiv64(a, b, true) - : ir.FPDiv32(a, b, true); + ? ir.FPDiv64(reg_n, reg_m, true) + : ir.FPDiv32(reg_n, reg_m, true); ir.SetExtendedRegister(d, result); } return true; @@ -317,10 +317,10 @@ bool ArmTranslatorVisitor::vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool ExtReg m = ToExtReg(sz, Vm, M); // VABS.{F32,F64} <{S,D}d>, <{S,D}m> if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(m); + auto reg_m = ir.GetExtendedRegister(m); auto result = sz - ? ir.FPAbs64(a) - : ir.FPAbs32(a); + ? ir.FPAbs64(reg_m) + : ir.FPAbs32(reg_m); ir.SetExtendedRegister(d, result); } return true; @@ -334,10 +334,10 @@ bool ArmTranslatorVisitor::vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool ExtReg m = ToExtReg(sz, Vm, M); // VNEG.{F32,F64} <{S,D}d>, <{S,D}m> if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(m); + auto reg_m = ir.GetExtendedRegister(m); auto result = sz - ? ir.FPNeg64(a) - : ir.FPNeg32(a); + ? ir.FPNeg64(reg_m) + : ir.FPNeg32(reg_m); ir.SetExtendedRegister(d, result); } return true; @@ -351,10 +351,10 @@ bool ArmTranslatorVisitor::vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, boo ExtReg m = ToExtReg(sz, Vm, M); // VSQRT.{F32,F64} <{S,D}d>, <{S,D}m> if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(m); + auto reg_m = ir.GetExtendedRegister(m); auto result = sz - ? ir.FPSqrt64(a) - : ir.FPSqrt32(a); + ? ir.FPSqrt64(reg_m) + : ir.FPSqrt32(reg_m); ir.SetExtendedRegister(d, result); } return true; @@ -366,10 +366,10 @@ bool ArmTranslatorVisitor::vfp2_VCVT_f_to_f(Cond cond, bool D, size_t Vd, bool s // VCVT.F64.F32 // VCVT.F32.F64
if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(m); + auto reg_m = ir.GetExtendedRegister(m); auto result = sz - ? ir.FPDoubleToSingle(a, true) - : ir.FPSingleToDouble(a, true); + ? ir.FPDoubleToSingle(reg_m, true) + : ir.FPSingleToDouble(reg_m, true); ir.SetExtendedRegister(d, result); } return true; @@ -382,14 +382,14 @@ bool ArmTranslatorVisitor::vfp2_VCVT_to_float(Cond cond, bool D, size_t Vd, bool // VCVT.F32.{S32,U32} , // VCVT.F64.{S32,U32} , if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(m); + auto reg_m = ir.GetExtendedRegister(m); auto result = sz ? is_signed - ? ir.FPS32ToDouble(a, round_to_nearest, true) - : ir.FPU32ToDouble(a, round_to_nearest, true) + ? ir.FPS32ToDouble(reg_m, round_to_nearest, true) + : ir.FPU32ToDouble(reg_m, round_to_nearest, true) : is_signed - ? ir.FPS32ToSingle(a, round_to_nearest, true) - : ir.FPU32ToSingle(a, round_to_nearest, true); + ? ir.FPS32ToSingle(reg_m, round_to_nearest, true) + : ir.FPU32ToSingle(reg_m, round_to_nearest, true); ir.SetExtendedRegister(d, result); } return true; @@ -401,10 +401,10 @@ bool ArmTranslatorVisitor::vfp2_VCVT_to_u32(Cond cond, bool D, size_t Vd, bool s // VCVT{,R}.U32.F32 , // VCVT{,R}.U32.F64 , if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(m); + auto reg_m = ir.GetExtendedRegister(m); auto result = sz - ? ir.FPDoubleToU32(a, round_towards_zero, true) - : ir.FPSingleToU32(a, round_towards_zero, true); + ? ir.FPDoubleToU32(reg_m, round_towards_zero, true) + : ir.FPSingleToU32(reg_m, round_towards_zero, true); ir.SetExtendedRegister(d, result); } return true; @@ -416,10 +416,10 @@ bool ArmTranslatorVisitor::vfp2_VCVT_to_s32(Cond cond, bool D, size_t Vd, bool s // VCVT{,R}.S32.F32 , // VCVT{,R}.S32.F64 , if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(m); + auto reg_m = ir.GetExtendedRegister(m); auto result = sz - ? ir.FPDoubleToS32(a, round_towards_zero, true) - : ir.FPSingleToS32(a, round_towards_zero, true); + ? ir.FPDoubleToS32(reg_m, round_towards_zero, true) + : ir.FPSingleToS32(reg_m, round_towards_zero, true); ir.SetExtendedRegister(d, result); } return true; @@ -432,12 +432,12 @@ bool ArmTranslatorVisitor::vfp2_VCMP(Cond cond, bool D, size_t Vd, bool sz, bool // VCMP{E}.F32 , // VCMP{E}.F64
, if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(d); - auto b = ir.GetExtendedRegister(m); + auto reg_d = ir.GetExtendedRegister(d); + auto reg_m = ir.GetExtendedRegister(m); if (sz) { - ir.FPCompare64(a, b, quiet, true); + ir.FPCompare64(reg_d, reg_m, quiet, true); } else { - ir.FPCompare32(a, b, quiet, true); + ir.FPCompare32(reg_d, reg_m, quiet, true); } } return true; @@ -449,14 +449,14 @@ bool ArmTranslatorVisitor::vfp2_VCMP_zero(Cond cond, bool D, size_t Vd, bool sz, // VCMP{E}.F32 , #0.0 // VCMP{E}.F64
, #0.0 if (ConditionPassed(cond)) { - auto a = ir.GetExtendedRegister(d); - auto b = sz - ? ir.TransferToFP64(ir.Imm64(0)) - : ir.TransferToFP32(ir.Imm32(0)); + auto reg_d = ir.GetExtendedRegister(d); + auto zero = sz + ? ir.TransferToFP64(ir.Imm64(0)) + : ir.TransferToFP32(ir.Imm32(0)); if (sz) { - ir.FPCompare64(a, b, quiet, true); + ir.FPCompare64(reg_d, zero, quiet, true); } else { - ir.FPCompare32(a, b, quiet, true); + ir.FPCompare32(reg_d, zero, quiet, true); } } return true;