From 0b53290dd76a1b67ee4af415bc3c3ce92aa76764 Mon Sep 17 00:00:00 2001
From: Merry <git@mary.rs>
Date: Tue, 26 Jul 2022 16:31:24 +0100
Subject: [PATCH] emit_arm64_a32: Implement A32GetCpsr

---
 src/dynarmic/backend/arm64/a32_jitstate.h     | 10 +++----
 src/dynarmic/backend/arm64/emit_arm64_a32.cpp | 28 ++++++++++++++++---
 2 files changed, 29 insertions(+), 9 deletions(-)

diff --git a/src/dynarmic/backend/arm64/a32_jitstate.h b/src/dynarmic/backend/arm64/a32_jitstate.h
index 687eda47..875d44b6 100644
--- a/src/dynarmic/backend/arm64/a32_jitstate.h
+++ b/src/dynarmic/backend/arm64/a32_jitstate.h
@@ -15,17 +15,17 @@
 namespace Dynarmic::Backend::Arm64 {
 
 struct A32JitState {
+    u32 cpsr_nzcv = 0;
+    u32 cpsr_ge = 0;
+    u32 cpsr_jaifm = 0;
+    u32 cpsr_q = 0;
+
     std::array<u32, 16> regs{};
 
     u32 upper_location_descriptor;
 
     alignas(16) std::array<u32, 64> ext_regs{};
 
-    u32 cpsr_nzcv = 0;
-    u32 cpsr_ge = 0;
-    u32 cpsr_jaifm = 0;
-    u32 cpsr_q = 0;
-
     u32 fpsr = 0;
 
     u32 exclusive_state = 0;
diff --git a/src/dynarmic/backend/arm64/emit_arm64_a32.cpp b/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
index cc928c30..cb73edec 100644
--- a/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
+++ b/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
@@ -221,10 +221,30 @@ void EmitIR<IR::Opcode::A32SetVector>(oaknut::CodeGenerator& code, EmitContext&
 
 template<>
 void EmitIR<IR::Opcode::A32GetCpsr>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    (void)code;
-    (void)ctx;
-    (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    auto Wcpsr = ctx.reg_alloc.WriteW(inst);
+    RegAlloc::Realize(Wcpsr);
+
+    static_assert(offsetof(A32JitState, cpsr_jaifm) + sizeof(u32) == offsetof(A32JitState, cpsr_q));
+
+    code.LDR(Wcpsr, Xstate, offsetof(A32JitState, cpsr_nzcv));
+    code.LDP(Wscratch0, Wscratch1, Xstate, offsetof(A32JitState, cpsr_jaifm));
+    code.ORR(Wcpsr, Wcpsr, Wscratch0);
+    code.ORR(Wcpsr, Wcpsr, Wscratch1);
+
+    code.LDR(Wscratch0, Xstate, offsetof(A32JitState, cpsr_ge));
+    code.AND(Wscratch0, Wscratch0, 0x80808080);
+    code.MOV(Wscratch1, 0x00204081);
+    code.MUL(Wscratch0, Wscratch0, Wscratch1);
+    code.AND(Wscratch0, Wscratch0, 0xf0000000);
+    code.ORR(Wcpsr, Wcpsr, Wscratch0, LSR, 12);
+
+    code.LDR(Wscratch0, Xstate, offsetof(A32JitState, upper_location_descriptor));
+    code.AND(Wscratch0, Wscratch0, 0b11);
+    // 9 8 7 6 5
+    //       E T
+    code.ORR(Wscratch0, Wscratch0, Wscratch0, LSL, 3);
+    code.AND(Wscratch0, Wscratch0, 0x11111111);
+    code.ORR(Wcpsr, Wcpsr, Wscratch0, LSL, 5);
 }
 
 template<>