From 10de36394e2ec21a350bb1dbcff6935d8b8bc295 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Wed, 25 Jul 2018 19:11:43 +0100 Subject: [PATCH] A64: Implement FRECPS, vector/scalar single/double variants --- src/frontend/A64/decoder/a64.inc | 4 ++-- .../A64/translate/impl/simd_scalar_three_same.cpp | 11 +++++++++++ .../A64/translate/impl/simd_three_same.cpp | 14 ++++++++++++++ 3 files changed, 27 insertions(+), 2 deletions(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index d3b12fa1..8cfd8790 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -343,7 +343,7 @@ INST(DUP_elt_1, "DUP (element)", "01011 //INST(FCMEQ_reg_1, "FCMEQ (register)", "01011110010mmmmm001001nnnnnddddd") INST(FCMEQ_reg_2, "FCMEQ (register)", "010111100z1mmmmm111001nnnnnddddd") //INST(FRECPS_1, "FRECPS", "01011110010mmmmm001111nnnnnddddd") -//INST(FRECPS_2, "FRECPS", "010111100z1mmmmm111111nnnnnddddd") +INST(FRECPS_2, "FRECPS", "010111100z1mmmmm111111nnnnnddddd") //INST(FRSQRTS_1, "FRSQRTS", "01011110110mmmmm001111nnnnnddddd") INST(FRSQRTS_2, "FRSQRTS", "010111101z1mmmmm111111nnnnnddddd") //INST(FCMGE_reg_1, "FCMGE (register)", "01111110010mmmmm001001nnnnnddddd") @@ -731,7 +731,7 @@ INST(FADD_2, "FADD (vector)", "0Q001 //INST(FMULX_vec_4, "FMULX", "0Q0011100z1mmmmm110111nnnnnddddd") INST(FCMEQ_reg_4, "FCMEQ (register)", "0Q0011100z1mmmmm111001nnnnnddddd") //INST(FMLAL_vec_1, "FMLAL, FMLAL2 (vector)", "0Q0011100z1mmmmm111011nnnnnddddd") -//INST(FRECPS_4, "FRECPS", "0Q0011100z1mmmmm111111nnnnnddddd") +INST(FRECPS_4, "FRECPS", "0Q0011100z1mmmmm111111nnnnnddddd") INST(AND_asimd, "AND (vector)", "0Q001110001mmmmm000111nnnnnddddd") INST(BIC_asimd_reg, "BIC (vector, register)", "0Q001110011mmmmm000111nnnnnddddd") //INST(FMINNM_2, "FMINNM (vector)", "0Q0011101z1mmmmm110001nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_scalar_three_same.cpp b/src/frontend/A64/translate/impl/simd_scalar_three_same.cpp index 62ef27e1..8d0df6ca 100644 --- a/src/frontend/A64/translate/impl/simd_scalar_three_same.cpp +++ b/src/frontend/A64/translate/impl/simd_scalar_three_same.cpp @@ -181,6 +181,17 @@ bool TranslatorVisitor::FABD_2(bool sz, Vec Vm, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::FRECPS_2(bool sz, Vec Vm, Vec Vn, Vec Vd) { + const size_t esize = sz ? 64 : 32; + + const IR::U32U64 operand1 = V_scalar(esize, Vn); + const IR::U32U64 operand2 = V_scalar(esize, Vm); + const IR::U32U64 result = ir.FPRecipStepFused(operand1, operand2); + + V_scalar(esize, Vd, result); + return true; +} + bool TranslatorVisitor::FRSQRTS_2(bool sz, Vec Vm, Vec Vn, Vec Vd) { const size_t esize = sz ? 64 : 32; diff --git a/src/frontend/A64/translate/impl/simd_three_same.cpp b/src/frontend/A64/translate/impl/simd_three_same.cpp index 1303b29a..c58fcceb 100644 --- a/src/frontend/A64/translate/impl/simd_three_same.cpp +++ b/src/frontend/A64/translate/impl/simd_three_same.cpp @@ -622,6 +622,20 @@ bool TranslatorVisitor::FSUB_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::FRECPS_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { + if (sz && !Q) { + return ReservedValue(); + } + const size_t esize = sz ? 64 : 32; + const size_t datasize = Q ? 128 : 64; + + const IR::U128 operand1 = V(datasize, Vn); + const IR::U128 operand2 = V(datasize, Vm); + const IR::U128 result = ir.FPVectorRecipStepFused(esize, operand1, operand2); + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::FRSQRTS_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { if (sz && !Q) { return ReservedValue();