From 129af4f6b464231bd233d569755b50e08c3adc6b Mon Sep 17 00:00:00 2001
From: Merry <git@mary.rs>
Date: Sun, 24 Jul 2022 16:12:53 +0100
Subject: [PATCH] backend/arm64: Implement A32SetCpsrNZ

---
 src/dynarmic/backend/arm64/emit_arm64_a32.cpp | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/src/dynarmic/backend/arm64/emit_arm64_a32.cpp b/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
index af864ba1..1c907ec2 100644
--- a/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
+++ b/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
@@ -263,10 +263,17 @@ void EmitIR<IR::Opcode::A32SetCpsrNZCVQ>(oaknut::CodeGenerator& code, EmitContex
 
 template<>
 void EmitIR<IR::Opcode::A32SetCpsrNZ>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    (void)code;
-    (void)ctx;
-    (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
+
+    auto Wnz = ctx.reg_alloc.ReadW(args[0]);
+    RegAlloc::Realize(Wnz);
+
+    // TODO: Track latent value
+
+    code.LDR(Wscratch0, Xstate, offsetof(A32JitState, cpsr_nzcv));
+    code.AND(Wscratch0, Wscratch0, 0x30000000);
+    code.ORR(Wscratch0, Wscratch0, Wnz);
+    code.STR(Wscratch0, Xstate, offsetof(A32JitState, cpsr_nzcv));
 }
 
 template<>