diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index 1e6a81d1..c4ade15a 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -501,7 +501,7 @@ INST(UQSUB_1,                "UQSUB",                                     "01111
 INST(CMHI_1,                 "CMHI (register)",                           "01111110zz1mmmmm001101nnnnnddddd")
 INST(CMHS_1,                 "CMHS (register)",                           "01111110zz1mmmmm001111nnnnnddddd")
 INST(USHL_1,                 "USHL",                                      "01111110zz1mmmmm010001nnnnnddddd")
-//INST(UQSHL_reg_1,            "UQSHL (register)",                          "01111110zz1mmmmm010011nnnnnddddd")
+INST(UQSHL_reg_1,            "UQSHL (register)",                          "01111110zz1mmmmm010011nnnnnddddd")
 INST(URSHL_1,                "URSHL",                                     "01111110zz1mmmmm010101nnnnnddddd")
 //INST(UQRSHL_1,               "UQRSHL",                                    "01111110zz1mmmmm010111nnnnnddddd")
 INST(SUB_1,                  "SUB (vector)",                              "01111110zz1mmmmm100001nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/simd_scalar_three_same.cpp b/src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
index 02605c06..c6926ed0 100644
--- a/src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
+++ b/src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
@@ -362,6 +362,17 @@ bool TranslatorVisitor::SUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
     return true;
 }
 
+bool TranslatorVisitor::UQSHL_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
+    const size_t esize = 8U << size.ZeroExtend();
+
+    const IR::U128 operand1 = ir.ZeroExtendToQuad(ir.VectorGetElement(esize, V(128, Vn), 0));
+    const IR::U128 operand2 = ir.ZeroExtendToQuad(ir.VectorGetElement(esize, V(128, Vm), 0));
+    const IR::U128 result = ir.VectorUnsignedSaturatedShiftLeft(esize, operand1, operand2);
+
+    ir.SetQ(Vd, result);
+    return true;
+}
+
 bool TranslatorVisitor::URSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
     return RoundingShiftLeft(*this, size, Vm, Vn, Vd, Signedness::Unsigned);
 }