From 18ad7f237df9fe8de1f831f290336dca3a898d36 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sun, 9 Sep 2018 01:43:51 -0400 Subject: [PATCH] A64: Implement SUQADD's scalar and vector variants --- src/frontend/A64/decoder/a64.inc | 4 ++-- .../impl/simd_scalar_two_register_misc.cpp | 12 ++++++++++++ .../translate/impl/simd_two_register_misc.cpp | 16 ++++++++++++++++ 3 files changed, 30 insertions(+), 2 deletions(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index c7c0f4f6..e59c4e2e 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -406,7 +406,7 @@ INST(FRSQRTE_2, "FRSQRTE", "01111 //INST(SQRDMLSH_vec_2, "SQRDMLSH (vector)", "0Q101110zz0mmmmm100011nnnnnddddd") // Data Processing - FP and SIMD - Scalar two-register misc -//INST(SUQADD_1, "SUQADD", "01011110zz100000001110nnnnnddddd") +INST(SUQADD_1, "SUQADD", "01011110zz100000001110nnnnnddddd") INST(SQABS_1, "SQABS", "01011110zz100000011110nnnnnddddd") INST(CMGT_zero_1, "CMGT (zero)", "01011110zz100000100010nnnnnddddd") INST(CMEQ_zero_1, "CMEQ (zero)", "01011110zz100000100110nnnnnddddd") @@ -569,7 +569,7 @@ INST(UDOT_vec, "UDOT (vector)", "0Q101 INST(REV64_asimd, "REV64", "0Q001110zz100000000010nnnnnddddd") INST(REV16_asimd, "REV16 (vector)", "0Q001110zz100000000110nnnnnddddd") INST(SADDLP, "SADDLP", "0Q001110zz100000001010nnnnnddddd") -//INST(SUQADD_2, "SUQADD", "0Q001110zz100000001110nnnnnddddd") +INST(SUQADD_2, "SUQADD", "0Q001110zz100000001110nnnnnddddd") //INST(CLS_asimd, "CLS (vector)", "0Q001110zz100000010010nnnnnddddd") INST(CNT, "CNT", "0Q001110zz100000010110nnnnnddddd") INST(SADALP, "SADALP", "0Q001110zz100000011010nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp index c285faba..ea84d50c 100644 --- a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp +++ b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp @@ -233,6 +233,18 @@ bool TranslatorVisitor::SQXTUN_1(Imm<2> size, Vec Vn, Vec Vd) { return SaturatedNarrow(*this, size, Vn, Vd, &IREmitter::VectorSignedSaturatedNarrowToUnsigned); } +bool TranslatorVisitor::SUQADD_1(Imm<2> size, Vec Vn, Vec Vd) { + const size_t esize = 8 << size.ZeroExtend(); + const size_t datasize = 64; + + const IR::U128 operand1 = ir.ZeroExtendToQuad(ir.VectorGetElement(esize, V(datasize, Vn), 0)); + const IR::U128 operand2 = ir.ZeroExtendToQuad(ir.VectorGetElement(esize, V(datasize, Vd), 0)); + const IR::U128 result = ir.VectorSignedSaturatedAccumulateUnsigned(esize, operand1, operand2); + + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) { const auto esize = sz ? 64 : 32; diff --git a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp index 6218dc30..328af5f2 100644 --- a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp +++ b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp @@ -629,6 +629,22 @@ bool TranslatorVisitor::SQNEG_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::SUQADD_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) { + if (size == 0b11 && !Q) { + return ReservedValue(); + } + + const size_t esize = 8 << size.ZeroExtend(); + const size_t datasize = Q ? 128 : 64; + + const IR::U128 operand1 = V(datasize, Vn); + const IR::U128 operand2 = V(datasize, Vd); + const IR::U128 result = ir.VectorSignedSaturatedAccumulateUnsigned(esize, operand1, operand2); + + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::SADALP(bool Q, Imm<2> size, Vec Vn, Vec Vd) { return PairedAddLong(*this, Q, size, Vn, Vd, Signedness::Signed, PairedAddLongExtraBehavior::Accumulate); }