diff --git a/src/dynarmic/backend/arm64/emit_arm64_packed.cpp b/src/dynarmic/backend/arm64/emit_arm64_packed.cpp
index c5baeec5..68c2fd28 100644
--- a/src/dynarmic/backend/arm64/emit_arm64_packed.cpp
+++ b/src/dynarmic/backend/arm64/emit_arm64_packed.cpp
@@ -74,10 +74,23 @@ void EmitIR<IR::Opcode::PackedAddS8>(oaknut::CodeGenerator& code, EmitContext& c
 
 template<>
 void EmitIR<IR::Opcode::PackedSubU8>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    (void)code;
-    (void)ctx;
-    (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    const auto ge_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetGEFromOp);
+
+    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
+    auto Vresult = ctx.reg_alloc.WriteD(inst);
+    auto Va = ctx.reg_alloc.ReadD(args[0]);
+    auto Vb = ctx.reg_alloc.ReadD(args[1]);
+    RegAlloc::Realize(Vresult, Va, Vb);
+
+    code.SUB(Vresult->B8(), Va->B8(), Vb->B8());
+
+    if (ge_inst) {
+        auto Vge = ctx.reg_alloc.WriteD(ge_inst);
+        RegAlloc::Realize(Vge);
+
+        code.UHSUB(Vge->B8(), Va->B8(), Vb->B8());
+        code.CMGE(Vge->B8(), Vge->B8(), 0);
+    }
 }
 
 template<>