From 239ee289cf5912ef8dad528d67e80672c50dbfb8 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sun, 21 Jun 2020 00:22:33 +0100 Subject: [PATCH] A32: Implement VDUP (scalar) --- src/frontend/A32/decoder/asimd.inc | 2 +- .../A32/translate/impl/asimd_misc.cpp | 23 +++++++++++++++++++ .../A32/translate/impl/translate_arm.h | 2 +- 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 43df7118..093a5ff6 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -113,7 +113,7 @@ INST(asimd_VRSQRTE, "VRSQRTE", "111100111D11zz11dddd010 INST(asimd_VEXT, "VEXT", "111100101D11nnnnddddiiiiNQM0mmmm") // ASIMD INST(asimd_VTBL, "VTBL", "111100111D11nnnndddd10zzN0M0mmmm") // ASIMD INST(asimd_VTBX, "VTBX", "111100111D11nnnndddd10zzN1M0mmmm") // ASIMD -//INST(asimd_VDUP_scalar, "VDUP (scalar)", "111100111D11iiiidddd11000QM0mmmm") // ASIMD +INST(asimd_VDUP_scalar, "VDUP (scalar)", "111100111D11iiiidddd11000QM0mmmm") // ASIMD // One register and modified immediate INST(asimd_VMOV_imm, "VBIC, VMOV, VMVN, VORR (immediate)", "1111001a1D000bcdVVVVmmmm0Qo1efgh") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_misc.cpp b/src/frontend/A32/translate/impl/asimd_misc.cpp index 1518ce48..039d06bf 100644 --- a/src/frontend/A32/translate/impl/asimd_misc.cpp +++ b/src/frontend/A32/translate/impl/asimd_misc.cpp @@ -65,4 +65,27 @@ bool ArmTranslatorVisitor::asimd_VTBX(bool D, size_t Vn, size_t Vd, size_t len, return TableLookup(*this, false, D, Vn, Vd, len, N, M, Vm); } +bool ArmTranslatorVisitor::asimd_VDUP_scalar(bool D, Imm<4> imm4, size_t Vd, bool Q, bool M, size_t Vm) { + if (Q && Common::Bit<0>(Vd)) { + return UndefinedInstruction(); + } + + if (imm4.Bits<0, 2>() == 0b000) { + return UndefinedInstruction(); + } + + const size_t imm4_lsb = Common::LowestSetBit(imm4.ZeroExtend()); + const size_t esize = 8u << imm4_lsb; + const size_t index = imm4.ZeroExtend() >> (imm4_lsb + 1); + const auto d = ToVector(Q, Vd, D); + const auto m = ToVector(false, Vm, M); + + const auto reg_m = ir.GetVector(m); + const auto scalar = ir.VectorGetElement(esize, reg_m, index); + const auto result = ir.VectorBroadcast(esize, scalar); + + ir.SetVector(d, result); + return true; +} + } // namespace Dynarmic::A32 diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index 666d8be9..7bce33c1 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -415,7 +415,6 @@ struct ArmTranslatorVisitor final { bool vfp_VMOV_imm(Cond cond, bool D, Imm<4> imm4H, size_t Vd, bool sz, Imm<4> imm4L); bool vfp_VMOV_reg(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm); - // Floating-point misc instructions bool vfp_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm); bool vfp_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm); @@ -529,6 +528,7 @@ struct ArmTranslatorVisitor final { bool asimd_VEXT(bool D, size_t Vn, size_t Vd, Imm<4> imm4, bool N, bool Q, bool M, size_t Vm); bool asimd_VTBL(bool D, size_t Vn, size_t Vd, size_t len, bool N, bool M, size_t Vm); bool asimd_VTBX(bool D, size_t Vn, size_t Vd, size_t len, bool N, bool M, size_t Vm); + bool asimd_VDUP_scalar(bool D, Imm<4> imm4, size_t Vd, bool Q, bool M, size_t Vm); // Advanced SIMD load/store structures bool v8_VST_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t sz, size_t align, Reg m);