From 24e329927617172819ba8f9bd1b0cde7ef4d5123 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sun, 3 Jun 2018 20:28:16 -0400 Subject: [PATCH] A64: Implement FCMGT, FCMGE (register) vector double and single precision variants --- src/frontend/A64/decoder/a64.inc | 4 +- .../A64/translate/impl/simd_three_same.cpp | 52 +++++++++++++++---- 2 files changed, 43 insertions(+), 13 deletions(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 00a3ee8e..838c15e4 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -768,7 +768,7 @@ INST(MLS_vec, "MLS (vector)", "0Q101 //INST(FMLAL_vec_2, "FMLAL, FMLAL2 (vector)", "0Q1011100z1mmmmm110011nnnnnddddd") //INST(FADDP_vec_2, "FADDP (vector)", "0Q1011100z1mmmmm110101nnnnnddddd") INST(FMUL_vec_2, "FMUL (vector)", "0Q1011100z1mmmmm110111nnnnnddddd") -//INST(FCMGE_reg_4, "FCMGE (register)", "0Q1011100z1mmmmm111001nnnnnddddd") +INST(FCMGE_reg_4, "FCMGE (register)", "0Q1011100z1mmmmm111001nnnnnddddd") //INST(FACGE_4, "FACGE", "0Q1011100z1mmmmm111011nnnnnddddd") //INST(FMAXP_vec_2, "FMAXP (vector)", "0Q1011100z1mmmmm111101nnnnnddddd") INST(FDIV_2, "FDIV (vector)", "0Q1011100z1mmmmm111111nnnnnddddd") @@ -777,7 +777,7 @@ INST(BSL, "BSL", "0Q101 //INST(FMINNMP_vec_2, "FMINNMP (vector)", "0Q1011101z1mmmmm110001nnnnnddddd") //INST(FMLSL_vec_2, "FMLSL, FMLSL2 (vector)", "0Q1011101z1mmmmm110011nnnnnddddd") //INST(FABD_4, "FABD", "0Q1011101z1mmmmm110101nnnnnddddd") -//INST(FCMGT_reg_4, "FCMGT (register)", "0Q1011101z1mmmmm111001nnnnnddddd") +INST(FCMGT_reg_4, "FCMGT (register)", "0Q1011101z1mmmmm111001nnnnnddddd") //INST(FACGT_4, "FACGT", "0Q1011101z1mmmmm111011nnnnnddddd") //INST(FMINP_vec_2, "FMINP (vector)", "0Q1011101z1mmmmm111101nnnnnddddd") INST(BIT, "BIT", "0Q101110101mmmmm000111nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_three_same.cpp b/src/frontend/A64/translate/impl/simd_three_same.cpp index 92d643bf..35ce5012 100644 --- a/src/frontend/A64/translate/impl/simd_three_same.cpp +++ b/src/frontend/A64/translate/impl/simd_three_same.cpp @@ -96,6 +96,40 @@ bool RoundingHalvingAdd(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec V v.V(datasize, Vd, result); return true; } + +enum class ComparisonType { + EQ, + GE, + GT +}; + +bool FPCompareRegister(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd, ComparisonType type) { + if (sz && !Q) { + return v.ReservedValue(); + } + + const size_t esize = sz ? 64 : 32; + const size_t datasize = Q ? 128 : 64; + + const IR::U128 operand1 = v.V(datasize, Vn); + const IR::U128 operand2 = v.V(datasize, Vm); + const IR::U128 result = [&] { + switch (type) { + case ComparisonType::EQ: + return v.ir.FPVectorEqual(esize, operand1, operand2); + case ComparisonType::GE: + return v.ir.FPVectorGreaterEqual(esize, operand1, operand2); + case ComparisonType::GT: + return v.ir.FPVectorGreater(esize, operand1, operand2); + } + + UNREACHABLE(); + return IR::U128{}; + }(); + + v.V(datasize, Vd, result); + return true; +} } // Anonymous namespace bool TranslatorVisitor::CMGT_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { @@ -345,19 +379,15 @@ bool TranslatorVisitor::FADD_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { } bool TranslatorVisitor::FCMEQ_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { - if (sz && !Q) { - return ReservedValue(); - } + return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::EQ); +} - const size_t esize = sz ? 64 : 32; - const size_t datasize = Q ? 128 : 64; +bool TranslatorVisitor::FCMGE_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { + return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::GE); +} - const IR::U128 operand1 = V(datasize, Vn); - const IR::U128 operand2 = V(datasize, Vm); - const IR::U128 result = ir.FPVectorEqual(esize, operand1, operand2); - - V(datasize, Vd, result); - return true; +bool TranslatorVisitor::FCMGT_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { + return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::GT); } bool TranslatorVisitor::AND_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {