diff --git a/src/frontend/A32/decoder/thumb32.inc b/src/frontend/A32/decoder/thumb32.inc
index c41766a6..39214faa 100644
--- a/src/frontend/A32/decoder/thumb32.inc
+++ b/src/frontend/A32/decoder/thumb32.inc
@@ -129,10 +129,10 @@ INST(thumb32_STRB_imm_2,     "STRB (imm)",               "111110000000nnnntttt11
 INST(thumb32_STRB_imm_3,     "STRB (imm)",               "111110001000nnnnttttiiiiiiiiiiii")
 INST(thumb32_STRBT,          "STRBT",                    "111110000000nnnntttt1110iiiiiiii")
 INST(thumb32_STRB,           "STRB (reg)",               "111110000000nnnntttt000000iimmmm")
-//INST(thumb32_STRH_imm_1,     "STRH (imm)",               "111110000010--------1--1--------")
-//INST(thumb32_STRH_imm_2,     "STRH (imm)",               "111110000010--------1100--------")
-//INST(thumb32_STRH_imm_3,     "STRH (imm)",               "111110001010--------------------")
-//INST(thumb32_STRHT,          "STRHT",                    "111110000010--------1110--------")
+INST(thumb32_STRH_imm_1,     "STRH (imm)",               "111110000010nnnntttt1PU1iiiiiiii")
+INST(thumb32_STRH_imm_2,     "STRH (imm)",               "111110000010nnnntttt1100iiiiiiii")
+INST(thumb32_STRH_imm_3,     "STRH (imm)",               "111110001010nnnnttttiiiiiiiiiiii")
+INST(thumb32_STRHT,          "STRHT",                    "111110000010nnnntttt1110iiiiiiii")
 INST(thumb32_STRH,           "STRH (reg)",               "111110000010nnnntttt000000iimmmm")
 //INST(thumb32_STR_imm_1,      "STR (imm)",                "111110000100--------1--1--------")
 //INST(thumb32_STR_imm_2,      "STR (imm)",                "111110000100--------1100--------")
diff --git a/src/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp b/src/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp
index 3b5617f6..c9820d67 100644
--- a/src/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp
+++ b/src/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp
@@ -29,8 +29,19 @@ static bool StoreRegister(ThumbTranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2,
     return true;
 }
 
-static bool StoreByteImmediate(ThumbTranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8) {
-    const auto imm32 = imm8.ZeroExtend();
+using StoreImmFn = void (*)(ThumbTranslatorVisitor&, const IR::U32&, const IR::U32&);
+
+static void StoreImmByteFn(ThumbTranslatorVisitor& v, const IR::U32& address, const IR::U32& data) {
+    v.ir.WriteMemory8(address, v.ir.LeastSignificantByte(data));
+}
+
+static void StoreImmHalfFn(ThumbTranslatorVisitor& v, const IR::U32& address, const IR::U32& data) {
+    v.ir.WriteMemory16(address, v.ir.LeastSignificantHalf(data));
+}
+
+static bool StoreImmediate(ThumbTranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W, Imm<12> imm12,
+                           StoreImmFn store_fn) {
+    const auto imm32 = imm12.ZeroExtend();
     const auto reg_n = v.ir.GetRegister(n);
     const auto reg_t = v.ir.GetRegister(t);
 
@@ -38,9 +49,8 @@ static bool StoreByteImmediate(ThumbTranslatorVisitor& v, Reg n, Reg t, bool P,
                                      : v.ir.Sub(reg_n, v.ir.Imm32(imm32));
     const IR::U32 address = P ? offset_address
                               : reg_n;
-    const IR::U8 data = v.ir.LeastSignificantByte(reg_t);
 
-    v.ir.WriteMemory8(address, data);
+    store_fn(v, address, reg_t);
     if (W) {
         v.ir.SetRegister(n, offset_address);
     }
@@ -55,7 +65,7 @@ bool ThumbTranslatorVisitor::thumb32_STRB_imm_1(Reg n, Reg t, bool P, bool U, Im
     if (t == Reg::PC || n == t) {
         return UnpredictableInstruction();
     }
-    return StoreByteImmediate(*this, n, t, P, U, true, imm8);
+    return StoreImmediate(*this, n, t, P, U, true, Imm<12>{imm8.ZeroExtend()}, StoreImmByteFn);
 }
 
 bool ThumbTranslatorVisitor::thumb32_STRB_imm_2(Reg n, Reg t, Imm<8> imm8) {
@@ -65,7 +75,7 @@ bool ThumbTranslatorVisitor::thumb32_STRB_imm_2(Reg n, Reg t, Imm<8> imm8) {
     if (t == Reg::PC) {
         return UnpredictableInstruction();
     }
-    return StoreByteImmediate(*this, n, t, true, false, false, imm8);
+    return StoreImmediate(*this, n, t, true, false, false, Imm<12>{imm8.ZeroExtend()}, StoreImmByteFn);
 }
 
 bool ThumbTranslatorVisitor::thumb32_STRB_imm_3(Reg n, Reg t, Imm<12> imm12) {
@@ -75,15 +85,7 @@ bool ThumbTranslatorVisitor::thumb32_STRB_imm_3(Reg n, Reg t, Imm<12> imm12) {
     if (t == Reg::PC) {
         return UnpredictableInstruction();
     }
-
-    const auto imm32 = imm12.ZeroExtend();
-    const auto reg_n = ir.GetRegister(n);
-    const auto reg_t = ir.GetRegister(t);
-    const auto address = ir.Add(reg_n, ir.Imm32(imm32));
-    const auto data = ir.LeastSignificantByte(reg_t);
-
-    ir.WriteMemory8(address, data);
-    return true;
+    return StoreImmediate(*this, n, t, true, true, false, imm12, StoreImmByteFn);
 }
 
 bool ThumbTranslatorVisitor::thumb32_STRBT(Reg n, Reg t, Imm<8> imm8) {
@@ -100,7 +102,7 @@ bool ThumbTranslatorVisitor::thumb32_STRBT(Reg n, Reg t, Imm<8> imm8) {
 
     // Treat this as a normal STRB, given we don't support
     // execution levels other than EL0 currently.
-    return StoreByteImmediate(*this, n, t, true, true, false, imm8);
+    return StoreImmediate(*this, n, t, true, true, false, Imm<12>{imm8.ZeroExtend()}, StoreImmByteFn);
 }
 
 bool ThumbTranslatorVisitor::thumb32_STRB(Reg n, Reg t, Imm<2> imm2, Reg m) {
@@ -109,6 +111,53 @@ bool ThumbTranslatorVisitor::thumb32_STRB(Reg n, Reg t, Imm<2> imm2, Reg m) {
     });
 }
 
+bool ThumbTranslatorVisitor::thumb32_STRH_imm_1(Reg n, Reg t, bool P, bool U, Imm<8> imm8) {
+    if (n == Reg::PC) {
+        return UndefinedInstruction();
+    }
+    if (t == Reg::PC || n == t) {
+        return UnpredictableInstruction();
+    }
+    return StoreImmediate(*this, n, t, P, U, true, Imm<12>{imm8.ZeroExtend()}, StoreImmHalfFn);
+}
+
+bool ThumbTranslatorVisitor::thumb32_STRH_imm_2(Reg n, Reg t, Imm<8> imm8) {
+    if (n == Reg::PC) {
+        return UndefinedInstruction();
+    }
+    if (t == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+    return StoreImmediate(*this, n, t, true, false, false, Imm<12>{imm8.ZeroExtend()}, StoreImmHalfFn);
+}
+
+bool ThumbTranslatorVisitor::thumb32_STRH_imm_3(Reg n, Reg t, Imm<12> imm12) {
+    if (n == Reg::PC) {
+        return UndefinedInstruction();
+    }
+    if (t == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+    return StoreImmediate(*this, n, t, true, true, false, imm12, StoreImmHalfFn);
+}
+
+bool ThumbTranslatorVisitor::thumb32_STRHT(Reg n, Reg t, Imm<8> imm8) {
+    // TODO: Add an unpredictable instruction path if this
+    //       is executed in hypervisor mode if we ever support
+    //       privileged execution levels.
+
+    if (n == Reg::PC) {
+        return UndefinedInstruction();
+    }
+    if (t == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    // Treat this as a normal STRH, given we don't support
+    // execution levels other than EL0 currently.
+    return StoreImmediate(*this, n, t, true, true, false, Imm<12>{imm8.ZeroExtend()}, StoreImmHalfFn);
+}
+
 bool ThumbTranslatorVisitor::thumb32_STRH(Reg n, Reg t, Imm<2> imm2, Reg m) {
     return StoreRegister(*this, n, t, imm2, m, [this](const IR::U32& offset_address, const IR::U32& data) {
         ir.WriteMemory16(offset_address, ir.LeastSignificantHalf(data));
diff --git a/src/frontend/A32/translate/impl/translate_thumb.h b/src/frontend/A32/translate/impl/translate_thumb.h
index 6541842e..70379209 100644
--- a/src/frontend/A32/translate/impl/translate_thumb.h
+++ b/src/frontend/A32/translate/impl/translate_thumb.h
@@ -248,6 +248,10 @@ struct ThumbTranslatorVisitor final {
     bool thumb32_STRB_imm_3(Reg n, Reg t, Imm<12> imm12);
     bool thumb32_STRBT(Reg n, Reg t, Imm<8> imm8);
     bool thumb32_STRB(Reg n, Reg t, Imm<2> imm2, Reg m);
+    bool thumb32_STRH_imm_1(Reg n, Reg t, bool P, bool U, Imm<8> imm8);
+    bool thumb32_STRH_imm_2(Reg n, Reg t, Imm<8> imm8);
+    bool thumb32_STRH_imm_3(Reg n, Reg t, Imm<12> imm12);
+    bool thumb32_STRHT(Reg n, Reg t, Imm<8> imm8);
     bool thumb32_STRH(Reg n, Reg t, Imm<2> imm2, Reg m);
     bool thumb32_STR_reg(Reg n, Reg t, Imm<2> imm2, Reg m);