From 276e0b71dc0c85b0248f957e722a5861478bd117 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Thu, 18 Jun 2020 10:53:19 -0400 Subject: [PATCH] A32: Implement ASIMD VSRA --- src/frontend/A32/decoder/asimd.inc | 2 +- .../translate/impl/asimd_two_regs_shift.cpp | 50 ++++++++++++------- .../A32/translate/impl/translate_arm.h | 1 + 3 files changed, 33 insertions(+), 20 deletions(-) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index faa483a0..82d431b7 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -59,7 +59,7 @@ INST(asimd_VQSUB, "VQSUB", "1111001U0Dzznnnndddd001 // Two registers and a shift amount INST(asimd_SHR, "SHR", "1111001U1Diiiiiidddd0000LQM1mmmm") // ASIMD -//INST(asimd_SRA, "SRA", "1111001U1-vvv-------0001LB-1----") // ASIMD +INST(asimd_SRA, "SRA", "1111001U1Diiiiiidddd0001LQM1mmmm") // ASIMD //INST(asimd_VRSHR, "VRSHR", "1111001U1-vvv-------0010LB-1----") // ASIMD //INST(asimd_VRSRA, "VRSRA", "1111001U1-vvv-------0011LB-1----") // ASIMD //INST(asimd_VSRI, "VSRI", "111100111-vvv-------0100LB-1----") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp index bac8ceee..f5602b28 100644 --- a/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp +++ b/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp @@ -9,44 +9,56 @@ namespace Dynarmic::A32 { namespace { +enum class Accumulating { + None, + Accumulate +}; + std::pair ElementSizeAndShiftAmount(bool L, size_t imm6) { if (L) { - return {64, 64U - imm6}; + return {64, 64 - imm6}; } - const int highest = Common::HighestSetBit(imm6 >> 3); - if (highest == 0) { - return {8, 16 - imm6}; - } - - if (highest == 1) { - return {16, 32U - imm6}; - } - - return {32, 64U - imm6}; + const size_t esize = 8U << Common::HighestSetBit(imm6 >> 3); + const size_t shift_amount = (esize * 2) - imm6; + return {esize, shift_amount}; } -} // Anonymous namespace -bool ArmTranslatorVisitor::asimd_SHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) { +bool ShiftRight(ArmTranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm, + Accumulating accumulate) { if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { - return UndefinedInstruction(); + return v.UndefinedInstruction(); } // Technically just a related encoding (One register and modified immediate instructions) if (!L && Common::Bits<3, 5>(imm6) == 0) { - return UndefinedInstruction(); + return v.UndefinedInstruction(); } const auto [esize, shift_amount] = ElementSizeAndShiftAmount(L, imm6); const auto d = ToVector(Q, Vd, D); const auto m = ToVector(Q, Vm, M); - const auto reg_m = ir.GetVector(m); - const auto result = U ? ir.VectorLogicalShiftRight(esize, reg_m, static_cast(shift_amount)) - : ir.VectorArithmeticShiftRight(esize, reg_m, static_cast(shift_amount)); + const auto reg_m = v.ir.GetVector(m); + auto result = U ? v.ir.VectorLogicalShiftRight(esize, reg_m, static_cast(shift_amount)) + : v.ir.VectorArithmeticShiftRight(esize, reg_m, static_cast(shift_amount)); - ir.SetVector(d, result); + if (accumulate == Accumulating::Accumulate) { + const auto reg_d = v.ir.GetVector(d); + result = v.ir.VectorAdd(esize, result, reg_d); + } + + v.ir.SetVector(d, result); return true; } +} // Anonymous namespace + +bool ArmTranslatorVisitor::asimd_SHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) { + return ShiftRight(*this, U, D, imm6, Vd, L, Q, M, Vm, Accumulating::None); +} + +bool ArmTranslatorVisitor::asimd_SRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) { + return ShiftRight(*this, U, D, imm6, Vd, L, Q, M, Vm, Accumulating::Accumulate); +} } // namespace Dynarmic::A32 diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index b0527ffe..8af65ee4 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -453,6 +453,7 @@ struct ArmTranslatorVisitor final { // Two registers and a shift amount bool asimd_SHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm); + bool asimd_SRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm); // Advanced SIMD two register, miscellaneous bool asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool Q, bool M, size_t Vm);