From 28b38916a898714f48ec705ae10fbe67a09a95fd Mon Sep 17 00:00:00 2001 From: MerryMage Date: Thu, 26 Jul 2018 12:10:00 +0100 Subject: [PATCH] A64: Implement FCVTZS (vector, integer), single/double variant --- src/frontend/A64/decoder/a64.inc | 2 +- .../A64/translate/impl/simd_two_register_misc.cpp | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 90d4aee2..6a433754 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -609,7 +609,7 @@ INST(FABS_2, "FABS (vector)", "0Q001 //INST(FCVTPS_3, "FCVTPS (vector)", "0Q00111011111001101010nnnnnddddd") //INST(FCVTPS_4, "FCVTPS (vector)", "0Q0011101z100001101010nnnnnddddd") //INST(FCVTZS_int_3, "FCVTZS (vector, integer)", "0Q00111011111001101110nnnnnddddd") -//INST(FCVTZS_int_4, "FCVTZS (vector, integer)", "0Q0011101z100001101110nnnnnddddd") +INST(FCVTZS_int_4, "FCVTZS (vector, integer)", "0Q0011101z100001101110nnnnnddddd") //INST(URECPE, "URECPE", "0Q0011101z100001110010nnnnnddddd") //INST(FRECPE_3, "FRECPE", "0Q00111011111001110110nnnnnddddd") INST(FRECPE_4, "FRECPE", "0Q0011101z100001110110nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp index e91e9e28..723d5941 100644 --- a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp +++ b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp @@ -234,6 +234,21 @@ bool TranslatorVisitor::FCMLT_4(bool Q, bool sz, Vec Vn, Vec Vd) { return FPCompareAgainstZero(*this, Q, sz, Vn, Vd, ComparisonType::LT); } +bool TranslatorVisitor::FCVTZS_int_4(bool Q, bool sz, Vec Vn, Vec Vd) { + if (sz && !Q) { + return ReservedValue(); + } + + const size_t datasize = Q ? 128 : 64; + const size_t esize = sz ? 64 : 32; + + const IR::U128 operand = V(datasize, Vn); + const IR::U128 result = ir.FPVectorToSignedFixed(esize, operand, 0, FP::RoundingMode::TowardsZero); + + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::FRECPE_4(bool Q, bool sz, Vec Vn, Vec Vd) { if (sz && !Q) { return ReservedValue();