diff --git a/src/backend_x64/a32_jitstate.h b/src/backend_x64/a32_jitstate.h index 3688ac82..16325226 100644 --- a/src/backend_x64/a32_jitstate.h +++ b/src/backend_x64/a32_jitstate.h @@ -67,6 +67,7 @@ struct A32JitState { void ResetRSB(); u32 fpsr_exc = 0; + u32 fpsr_qc = 0; // Dummy value u32 FPSCR_IDC = 0; u32 FPSCR_UFC = 0; u32 FPSCR_mode = 0; diff --git a/src/backend_x64/a64_jitstate.cpp b/src/backend_x64/a64_jitstate.cpp index eee952f5..194a7041 100644 --- a/src/backend_x64/a64_jitstate.cpp +++ b/src/backend_x64/a64_jitstate.cpp @@ -106,6 +106,7 @@ u32 A64JitState::GetFpsr() const { fpsr |= FPSCR_IDC; fpsr |= FPSCR_UFC; fpsr |= fpsr_exc; + fpsr |= (fpsr_qc & 1) << 27; return fpsr; } @@ -113,6 +114,7 @@ void A64JitState::SetFpsr(u32 value) { guest_MXCSR &= ~0x0000003D; FPSCR_IDC = 0; FPSCR_UFC = 0; + fpsr_qc = (value >> 27) & 1; fpsr_exc = value & 0x9F; } diff --git a/src/backend_x64/a64_jitstate.h b/src/backend_x64/a64_jitstate.h index b8fdd5e1..ad7eb7b5 100644 --- a/src/backend_x64/a64_jitstate.h +++ b/src/backend_x64/a64_jitstate.h @@ -72,6 +72,7 @@ struct A64JitState { } u32 fpsr_exc = 0; + u32 fpsr_qc = 0; u32 FPSCR_IDC = 0; u32 FPSCR_UFC = 0; u32 fpcr = 0; diff --git a/src/backend_x64/jitstate_info.h b/src/backend_x64/jitstate_info.h index 3caca413..509db074 100644 --- a/src/backend_x64/jitstate_info.h +++ b/src/backend_x64/jitstate_info.h @@ -27,6 +27,7 @@ struct JitStateInfo { , offsetof_FPSCR_IDC(offsetof(JitStateType, FPSCR_IDC)) , offsetof_FPSCR_UFC(offsetof(JitStateType, FPSCR_UFC)) , offsetof_fpsr_exc(offsetof(JitStateType, fpsr_exc)) + , offsetof_fpsr_qc(offsetof(JitStateType, fpsr_qc)) {} const size_t offsetof_cycles_remaining; @@ -41,6 +42,7 @@ struct JitStateInfo { const size_t offsetof_FPSCR_IDC; const size_t offsetof_FPSCR_UFC; const size_t offsetof_fpsr_exc; + const size_t offsetof_fpsr_qc; }; } // namespace Dynarmic::BackendX64