From 2db032ac83958d781792fd7097aeda233160baa4 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Sat, 7 Apr 2018 23:54:14 -0400
Subject: [PATCH] A64: Implement SRI (vector)

---
 src/frontend/A64/decoder/a64.inc              |  2 +-
 .../impl/simd_shift_by_immediate.cpp          | 26 +++++++++++++++++++
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index 576c112a..01a4a489 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -806,7 +806,7 @@ INST(USHR_2,                 "USHR",                                      "0Q101
 INST(USRA_2,                 "USRA",                                      "0Q1011110IIIIiii000101nnnnnddddd")
 INST(URSHR_2,                "URSHR",                                     "0Q1011110IIIIiii001001nnnnnddddd")
 INST(URSRA_2,                "URSRA",                                     "0Q1011110IIIIiii001101nnnnnddddd")
-//INST(SRI_2,                  "SRI",                                       "0Q1011110IIIIiii010001nnnnnddddd")
+INST(SRI_2,                  "SRI",                                       "0Q1011110IIIIiii010001nnnnnddddd")
 INST(SLI_2,                  "SLI",                                       "0Q1011110IIIIiii010101nnnnnddddd")
 //INST(SQSHLU_2,               "SQSHLU",                                    "0Q1011110IIIIiii011001nnnnnddddd")
 //INST(UQSHL_imm_2,            "UQSHL (immediate)",                         "0Q1011110IIIIiii011101nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
index 8a1d7332..a45e614c 100644
--- a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
+++ b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
@@ -304,6 +304,32 @@ bool TranslatorVisitor::USHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd)
     return true;
 }
 
+bool TranslatorVisitor::SRI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
+    if (immh == 0b0000) {
+        return DecodeError();
+    }
+
+    if (!Q && immh.Bit<3>()) {
+        return ReservedValue();
+    }
+
+    const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
+    const size_t datasize = Q ? 128 : 64;
+
+    const u8 shift_amount = static_cast<u8>((esize * 2) - concatenate(immh, immb).ZeroExtend<u8>());
+    const u64 mask = shift_amount == esize ? 0 : Common::Ones<u64>(esize) >> shift_amount;
+
+    const IR::U128 operand1 = V(datasize, Vn);
+    const IR::U128 operand2 = V(datasize, Vd);
+
+    const IR::U128 shifted = ir.VectorLogicalShiftRight(esize, operand1, shift_amount);
+    const IR::U128 mask_vec = ir.VectorBroadcast(esize, I(esize, mask));
+    const IR::U128 result = ir.VectorOr(ir.VectorAnd(operand2, ir.VectorNot(mask_vec)), shifted);
+
+    V(datasize, Vd, result);
+    return true;
+}
+
 bool TranslatorVisitor::SLI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
     if (immh == 0b0000) {
         return DecodeError();