From 3557576ece6d956f58ebc9ffb05e4081505d7600 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sun, 21 Jun 2020 18:34:44 +0100 Subject: [PATCH] A32: Implement ASIMD AESD, AESE, AESIMC, AESMC --- src/frontend/A32/decoder/asimd.inc | 4 ++ .../translate/impl/asimd_two_regs_misc.cpp | 58 +++++++++++++++++++ .../A32/translate/impl/translate_arm.h | 4 ++ 3 files changed, 66 insertions(+) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 735b8725..2a0ebcff 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -83,6 +83,10 @@ INST(asimd_VQRSHRN, "VQRSHRN", "1111001U1Diiiiiidddd100 // Two registers, miscellaneous INST(asimd_VREV, "VREV{16,32,64}", "111100111D11zz00dddd000ooQM0mmmm") // ASIMD INST(asimd_VPADDL, "VPADDL", "111100111D11zz00dddd0010oQM0mmmm") // ASIMD +INST(v8_AESE, "AESE", "111100111D11zz00dddd001100M0mmmm") // v8 +INST(v8_AESD, "AESD", "111100111D11zz00dddd001101M0mmmm") // v8 +INST(v8_AESMC, "AESMC", "111100111D11zz00dddd001110M0mmmm") // v8 +INST(v8_AESIMC, "AESIMC", "111100111D11zz00dddd001111M0mmmm") // v8 INST(asimd_VCLS, "VCLS", "111100111D11zz00dddd01000QM0mmmm") // ASIMD INST(asimd_VCLZ, "VCLZ", "111100111D11zz00dddd01001QM0mmmm") // ASIMD INST(asimd_VCNT, "VCNT", "111100111D11zz00dddd01010QM0mmmm") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp index 3e1ab2f5..f475c424 100644 --- a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp +++ b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp @@ -169,6 +169,64 @@ bool ArmTranslatorVisitor::asimd_VPADDL(bool D, size_t sz, size_t Vd, bool op, b return PairedAddOperation(*this, D, sz, Vd, op, Q, M, Vm, AccumulateBehavior::None); } +bool ArmTranslatorVisitor::v8_AESD(bool D, size_t sz, size_t Vd, bool M, size_t Vm) { + if (sz != 0b00 || Common::Bit<0>(Vd) || Common::Bit<0>(Vm)) { + return UndefinedInstruction(); + } + + const auto d = ToVector(true, Vd, D); + const auto m = ToVector(true, Vm, M); + const auto reg_d = ir.GetVector(d); + const auto reg_m = ir.GetVector(m); + const auto result = ir.AESDecryptSingleRound(ir.VectorEor(reg_d, reg_m)); + + ir.SetVector(d, result); + return true; +} + +bool ArmTranslatorVisitor::v8_AESE(bool D, size_t sz, size_t Vd, bool M, size_t Vm) { + if (sz != 0b00 || Common::Bit<0>(Vd) || Common::Bit<0>(Vm)) { + return UndefinedInstruction(); + } + + const auto d = ToVector(true, Vd, D); + const auto m = ToVector(true, Vm, M); + const auto reg_d = ir.GetVector(d); + const auto reg_m = ir.GetVector(m); + const auto result = ir.AESEncryptSingleRound(ir.VectorEor(reg_d, reg_m)); + + ir.SetVector(d, result); + return true; +} + +bool ArmTranslatorVisitor::v8_AESIMC(bool D, size_t sz, size_t Vd, bool M, size_t Vm) { + if (sz != 0b00 || Common::Bit<0>(Vd) || Common::Bit<0>(Vm)) { + return UndefinedInstruction(); + } + + const auto d = ToVector(true, Vd, D); + const auto m = ToVector(true, Vm, M); + const auto reg_m = ir.GetVector(m); + const auto result = ir.AESInverseMixColumns(reg_m); + + ir.SetVector(d, result); + return true; +} + +bool ArmTranslatorVisitor::v8_AESMC(bool D, size_t sz, size_t Vd, bool M, size_t Vm) { + if (sz != 0b00 || Common::Bit<0>(Vd) || Common::Bit<0>(Vm)) { + return UndefinedInstruction(); + } + + const auto d = ToVector(true, Vd, D); + const auto m = ToVector(true, Vm, M); + const auto reg_m = ir.GetVector(m); + const auto result = ir.AESMixColumns(reg_m); + + ir.SetVector(d, result); + return true; +} + bool ArmTranslatorVisitor::asimd_VCLS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) { if (sz == 0b11) { return UndefinedInstruction(); diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index e48cb609..0a50cfb8 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -515,6 +515,10 @@ struct ArmTranslatorVisitor final { // Advanced SIMD two register, miscellaneous bool asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool Q, bool M, size_t Vm); bool asimd_VPADDL(bool D, size_t sz, size_t Vd, bool op, bool Q, bool M, size_t Vm); + bool v8_AESD(bool D, size_t sz, size_t Vd, bool M, size_t Vm); + bool v8_AESE(bool D, size_t sz, size_t Vd, bool M, size_t Vm); + bool v8_AESIMC(bool D, size_t sz, size_t Vd, bool M, size_t Vm); + bool v8_AESMC(bool D, size_t sz, size_t Vd, bool M, size_t Vm); bool asimd_VCLS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VCLZ(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VCNT(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);