diff --git a/src/frontend/A32/decoder/thumb32.h b/src/frontend/A32/decoder/thumb32.h index b097f478..954a36f7 100644 --- a/src/frontend/A32/decoder/thumb32.h +++ b/src/frontend/A32/decoder/thumb32.h @@ -275,7 +275,7 @@ std::optional>> DecodeThumb32(u32 //INST(&V::thumb32_UHSUB8, "UHSUB8", "111110101100----1111----0110----"), // Miscellaneous Operations - //INST(&V::thumb32_QADD, "QADD", "111110101000----1111----1000----"), + INST(&V::thumb32_QADD, "QADD", "111110101000nnnn1111dddd1000mmmm"), INST(&V::thumb32_QDADD, "QDADD", "111110101000nnnn1111dddd1001mmmm"), INST(&V::thumb32_QSUB, "QSUB", "111110101000nnnn1111dddd1010mmmm"), INST(&V::thumb32_QDSUB, "QDSUB", "111110101000nnnn1111dddd1011mmmm"), diff --git a/src/frontend/A32/translate/impl/thumb32_misc.cpp b/src/frontend/A32/translate/impl/thumb32_misc.cpp index 34c9e50e..c2808735 100644 --- a/src/frontend/A32/translate/impl/thumb32_misc.cpp +++ b/src/frontend/A32/translate/impl/thumb32_misc.cpp @@ -19,6 +19,20 @@ bool ThumbTranslatorVisitor::thumb32_CLZ(Reg n, Reg d, Reg m) { return true; } +bool ThumbTranslatorVisitor::thumb32_QADD(Reg n, Reg d, Reg m) { + if (d == Reg::PC || n == Reg::PC || m == Reg::PC) { + return UnpredictableInstruction(); + } + + const auto reg_m = ir.GetRegister(m); + const auto reg_n = ir.GetRegister(n); + const auto result = ir.SignedSaturatedAdd(reg_m, reg_n); + + ir.SetRegister(d, result.result); + ir.OrQFlag(result.overflow); + return true; +} + bool ThumbTranslatorVisitor::thumb32_QDADD(Reg n, Reg d, Reg m) { if (d == Reg::PC || n == Reg::PC || m == Reg::PC) { return UnpredictableInstruction(); diff --git a/src/frontend/A32/translate/impl/translate_thumb.h b/src/frontend/A32/translate/impl/translate_thumb.h index 9e8f40de..2dfe5d8a 100644 --- a/src/frontend/A32/translate/impl/translate_thumb.h +++ b/src/frontend/A32/translate/impl/translate_thumb.h @@ -118,6 +118,7 @@ struct ThumbTranslatorVisitor final { // thumb32 miscellaneous instructions bool thumb32_CLZ(Reg n, Reg d, Reg m); + bool thumb32_QADD(Reg n, Reg d, Reg m); bool thumb32_QDADD(Reg n, Reg d, Reg m); bool thumb32_QDSUB(Reg n, Reg d, Reg m); bool thumb32_QSUB(Reg n, Reg d, Reg m); diff --git a/tests/A32/fuzz_thumb.cpp b/tests/A32/fuzz_thumb.cpp index 1cc596ba..dbc5dece 100644 --- a/tests/A32/fuzz_thumb.cpp +++ b/tests/A32/fuzz_thumb.cpp @@ -369,6 +369,13 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") { const auto n = Common::Bits<16, 19>(inst); return m == n && d != 15 && m != 15; }), + ThumbInstGen("111110101000nnnn1111dddd1000mmmm", // QADD + [](u32 inst) { + const auto d = Common::Bits<8, 11>(inst); + const auto m = Common::Bits<0, 3>(inst); + const auto n = Common::Bits<16, 19>(inst); + return d != 15 && m != 15 && n != 15; + }), ThumbInstGen("111110101000nnnn1111dddd1001mmmm", // QDADD [](u32 inst) { const auto d = Common::Bits<8, 11>(inst);