From 39488e4aad4b09277d2cc0f3e93e63d2aafa0fe0 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sun, 21 Jun 2020 17:41:15 -0400 Subject: [PATCH] A32: Implement ASIMD VRSHRN --- src/frontend/A32/decoder/asimd.inc | 2 +- src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp | 5 +++++ src/frontend/A32/translate/impl/translate_arm.h | 1 + 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 56287bbe..2064bf3f 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -88,7 +88,7 @@ INST(asimd_VSHL, "VSHL", "111100101Diiiiiidddd010 INST(asimd_VSLI, "VSLI", "111100111Diiiiiidddd0101LQM1mmmm") // ASIMD INST(asimd_VQSHL, "VQSHL" , "1111001U1Diiiiiidddd011oLQM1mmmm") // ASIMD INST(asimd_VSHRN, "VSHRN", "111100101Diiiiiidddd100000M1mmmm") // ASIMD -//INST(asimd_VRSHRN, "VRSHRN", "111100101-vvv-------100001-1----") // ASIMD +INST(asimd_VRSHRN, "VRSHRN", "111100101Diiiiiidddd100001M1mmmm") // ASIMD INST(asimd_VQSHRUN, "VQSHRUN", "111100111Diiiiiidddd100000M1mmmm") // ASIMD INST(asimd_VQRSHRUN, "VQRSHRUN", "111100111Diiiiiidddd100001M1mmmm") // ASIMD INST(asimd_VQSHRN, "VQSHRN", "1111001U1Diiiiiidddd100100M1mmmm") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp index e6256428..3c9cc655 100644 --- a/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp +++ b/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp @@ -281,6 +281,11 @@ bool ArmTranslatorVisitor::asimd_VSHRN(bool D, size_t imm6, size_t Vd, bool M, s Rounding::None, Narrowing::Truncation, Signedness::Unsigned); } +bool ArmTranslatorVisitor::asimd_VRSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm) { + return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm, + Rounding::Round, Narrowing::Truncation, Signedness::Unsigned); +} + bool ArmTranslatorVisitor::asimd_VQRSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm) { return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm, Rounding::Round, Narrowing::SaturateToUnsigned, Signedness::Signed); diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index 947de032..8200756c 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -515,6 +515,7 @@ struct ArmTranslatorVisitor final { bool asimd_VSLI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm); bool asimd_VQSHL(bool U, bool D, size_t imm6, size_t Vd, bool op, bool L, bool Q, bool M, size_t Vm); bool asimd_VSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm); + bool asimd_VRSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm); bool asimd_VQSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm); bool asimd_VQRSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm); bool asimd_VQSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm);