From 3d465e2c365a2e77ce21cb3a5cc9475668fce6bd Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sun, 19 Aug 2018 19:28:03 -0400 Subject: [PATCH] A64: Implement SQXTN, SQXTUN, and UQXTN's scalar variants We can implement these in terms of the vector variants --- src/frontend/A64/decoder/a64.inc | 6 ++-- src/frontend/A64/translate/impl/impl.h | 8 +++--- .../impl/simd_scalar_two_register_misc.cpp | 28 +++++++++++++++++++ 3 files changed, 35 insertions(+), 7 deletions(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 0169241a..bafde0b2 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -412,14 +412,14 @@ INST(CMGT_zero_1, "CMGT (zero)", "01011 INST(CMEQ_zero_1, "CMEQ (zero)", "01011110zz100000100110nnnnnddddd") INST(CMLT_1, "CMLT (zero)", "01011110zz100000101010nnnnnddddd") INST(ABS_1, "ABS", "01011110zz100000101110nnnnnddddd") -//INST(SQXTN_1, "SQXTN, SQXTN2", "01011110zz100001010010nnnnnddddd") +INST(SQXTN_1, "SQXTN, SQXTN2", "01011110zz100001010010nnnnnddddd") //INST(USQADD_1, "USQADD", "01111110zz100000001110nnnnnddddd") //INST(SQNEG_1, "SQNEG", "01111110zz100000011110nnnnnddddd") INST(CMGE_zero_1, "CMGE (zero)", "01111110zz100000100010nnnnnddddd") INST(CMLE_1, "CMLE (zero)", "01111110zz100000100110nnnnnddddd") INST(NEG_1, "NEG (vector)", "01111110zz100000101110nnnnnddddd") -//INST(SQXTUN_1, "SQXTUN, SQXTUN2", "01111110zz100001001010nnnnnddddd") -//INST(UQXTN_1, "UQXTN, UQXTN2", "01111110zz100001010010nnnnnddddd") +INST(SQXTUN_1, "SQXTUN, SQXTUN2", "01111110zz100001001010nnnnnddddd") +INST(UQXTN_1, "UQXTN, UQXTN2", "01111110zz100001010010nnnnnddddd") //INST(FCVTXN_1, "FCVTXN, FCVTXN2", "011111100z100001011010nnnnnddddd") // Data Processing - FP and SIMD - SIMD Scalar pairwise diff --git a/src/frontend/A64/translate/impl/impl.h b/src/frontend/A64/translate/impl/impl.h index 59c1861b..a811e831 100644 --- a/src/frontend/A64/translate/impl/impl.h +++ b/src/frontend/A64/translate/impl/impl.h @@ -522,15 +522,15 @@ struct TranslatorVisitor final { bool CMEQ_zero_1(Imm<2> size, Vec Vn, Vec Vd); bool CMLT_1(Imm<2> size, Vec Vn, Vec Vd); bool ABS_1(Imm<2> size, Vec Vn, Vec Vd); - bool SQXTN_1(Imm<2> size, Vec Vn, Reg Rd); + bool SQXTN_1(Imm<2> size, Vec Vn, Vec Vd); bool USQADD_1(Imm<2> size, Vec Vn, Vec Vd); bool SQNEG_1(Imm<2> size, Vec Vn, Vec Vd); bool CMGE_zero_1(Imm<2> size, Vec Vn, Vec Vd); bool CMLE_1(Imm<2> size, Vec Vn, Vec Vd); bool NEG_1(Imm<2> size, Vec Vn, Vec Vd); - bool SQXTUN_1(Imm<2> size, Vec Vn, Reg Rd); - bool UQXTN_1(Imm<2> size, Vec Vn, Reg Rd); - bool FCVTXN_1(bool sz, Vec Vn, Reg Rd); + bool SQXTUN_1(Imm<2> size, Vec Vn, Vec Vd); + bool UQXTN_1(Imm<2> size, Vec Vn, Vec Vd); + bool FCVTXN_1(bool sz, Vec Vn, Vec Vd); // Data Processing - FP and SIMD - SIMD Scalar pairwise bool ADDP_pair(Imm<2> size, Vec Vn, Vec Vd); diff --git a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp index 98de4ea6..d3d5b585 100644 --- a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp +++ b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp @@ -73,6 +73,22 @@ bool ScalarFPConvertWithRound(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, v.V_scalar(esize, Vd, result); return true; } + +using NarrowingFn = IR::U128 (IR::IREmitter::*)(size_t, const IR::U128&); + +bool SaturatedNarrow(TranslatorVisitor& v, Imm<2> size, Vec Vn, Vec Vd, NarrowingFn fn) { + if (size == 0b11) { + return v.ReservedValue(); + } + + const size_t esize = 8 << size.ZeroExtend(); + + const IR::U128 operand = v.ir.ZeroExtendToQuad(v.V_scalar(2 * esize, Vn)); + const IR::U128 result = (v.ir.*fn)(2 * esize, operand); + + v.V_scalar(64, Vd, v.ir.VectorGetElement(64, result, 0)); + return true; +} } // Anonymous namespace bool TranslatorVisitor::ABS_1(Imm<2> size, Vec Vn, Vec Vd) { @@ -193,6 +209,14 @@ bool TranslatorVisitor::SCVTF_int_2(bool sz, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::SQXTN_1(Imm<2> size, Vec Vn, Vec Vd) { + return SaturatedNarrow(*this, size, Vn, Vd, &IREmitter::VectorSignedSaturatedNarrowToSigned); +} + +bool TranslatorVisitor::SQXTUN_1(Imm<2> size, Vec Vn, Vec Vd) { + return SaturatedNarrow(*this, size, Vn, Vd, &IREmitter::VectorSignedSaturatedNarrowToUnsigned); +} + bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) { const auto esize = sz ? 64 : 32; @@ -206,4 +230,8 @@ bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::UQXTN_1(Imm<2> size, Vec Vn, Vec Vd) { + return SaturatedNarrow(*this, size, Vn, Vd, &IREmitter::VectorUnsignedSaturatedNarrow); +} + } // namespace Dynarmic::A64