From 4339a8fff6db497b120706a80ed3131b63718a23 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Mon, 4 Mar 2019 10:58:19 -0500 Subject: [PATCH] A64: Implement the scalar version of FCVTXN --- src/frontend/A64/decoder/a64.inc | 2 +- .../translate/impl/simd_scalar_two_register_misc.cpp | 12 ++++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 9186a024..199cebfe 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -464,7 +464,7 @@ INST(CMLE_1, "CMLE (zero)", "01111 INST(NEG_1, "NEG (vector)", "01111110zz100000101110nnnnnddddd") INST(SQXTUN_1, "SQXTUN, SQXTUN2", "01111110zz100001001010nnnnnddddd") INST(UQXTN_1, "UQXTN, UQXTN2", "01111110zz100001010010nnnnnddddd") -//INST(FCVTXN_1, "FCVTXN, FCVTXN2", "011111100z100001011010nnnnnddddd") +INST(FCVTXN_1, "FCVTXN, FCVTXN2", "011111100z100001011010nnnnnddddd") // Data Processing - FP and SIMD - SIMD Scalar pairwise INST(ADDP_pair, "ADDP (scalar)", "01011110zz110001101110nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp index b8283d7c..7dcc89d3 100644 --- a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp +++ b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp @@ -152,6 +152,18 @@ bool TranslatorVisitor::FCVTPU_2(bool sz, Vec Vn, Vec Vd) { return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsPlusInfinity, Signedness::Unsigned); } +bool TranslatorVisitor::FCVTXN_1(bool sz, Vec Vn, Vec Vd) { + if (!sz) { + return UnallocatedEncoding(); + } + + const IR::U64 element = V_scalar(64, Vn); + const IR::U32 result = ir.FPDoubleToSingle(element, FP::RoundingMode::ToOdd); + + V_scalar(32, Vd, result); + return true; +} + bool TranslatorVisitor::FCVTZS_int_2(bool sz, Vec Vn, Vec Vd) { return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsZero, Signedness::Signed); }