diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index 52ed8da8..c286fecc 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -175,6 +175,7 @@ INST(STURx_LDURx,            "STURx/LDURx",                               "zz111
 INST(UnallocatedEncoding,    "",                                          "111110001-0---------00----------")
 INST(UnallocatedEncoding,    "",                                          "10111000110---------00----------")
 INST(PRFM_imm,               "PRFM (immediate)",                          "1111100110iiiiiiiiiiiinnnnnttttt")
+INST(PRFM_unscaled_imm,      "PRFM (unscaled offset)",                    "11111000100iiiiiiiii00nnnnnttttt")
 INST(STUR_fpsimd,            "STUR (SIMD&FP)",                            "zz111100o00iiiiiiiii00nnnnnttttt")
 INST(LDUR_fpsimd,            "LDUR (SIMD&FP)",                            "zz111100o10iiiiiiiii00nnnnnttttt")
 
diff --git a/src/frontend/A64/translate/impl/impl.h b/src/frontend/A64/translate/impl/impl.h
index a021d5a5..abef30a1 100644
--- a/src/frontend/A64/translate/impl/impl.h
+++ b/src/frontend/A64/translate/impl/impl.h
@@ -247,6 +247,7 @@ struct TranslatorVisitor final {
     bool STRx_LDRx_imm_2(Imm<2> size, Imm<2> opc, Imm<12> imm12, Reg Rn, Reg Rt);
     bool STURx_LDURx(Imm<2> size, Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt);
     bool PRFM_imm(Imm<12> imm12, Reg Rn, Reg Rt);
+    bool PRFM_unscaled_imm(Imm<9> imm9, Reg Rn, Reg Rt);
     bool STR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, bool not_postindex, Reg Rn, Vec Vt);
     bool STR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt);
     bool LDR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, bool not_postindex, Reg Rn, Vec Vt);
diff --git a/src/frontend/A64/translate/impl/load_store_register_immediate.cpp b/src/frontend/A64/translate/impl/load_store_register_immediate.cpp
index 3aa4995b..744a1d06 100644
--- a/src/frontend/A64/translate/impl/load_store_register_immediate.cpp
+++ b/src/frontend/A64/translate/impl/load_store_register_immediate.cpp
@@ -106,6 +106,12 @@ bool TranslatorVisitor::PRFM_imm([[maybe_unused]] Imm<12> imm12, [[maybe_unused]
     return true;
 }
 
+bool TranslatorVisitor::PRFM_unscaled_imm([[maybe_unused]] Imm<9> imm9, [[maybe_unused]] Reg Rn, [[maybe_unused]] Reg Rt) {
+    // Currently a NOP (which is valid behavior, as indicated by
+    // the ARMv8 architecture reference manual)
+    return true;
+}
+
 static bool LoadStoreSIMD(TranslatorVisitor& tv, IREmitter& ir, bool wback, bool postindex, size_t scale, u64 offset, MemOp memop, Reg Rn, Vec Vt) {
     const AccType acctype = AccType::VEC;
     const size_t datasize = 8 << scale;