diff --git a/src/frontend/ir/microinstruction.cpp b/src/frontend/ir/microinstruction.cpp
index 3a1e8f81..c24ad834 100644
--- a/src/frontend/ir/microinstruction.cpp
+++ b/src/frontend/ir/microinstruction.cpp
@@ -152,6 +152,15 @@ bool Inst::WritesToCPSR() const {
     }
 }
 
+bool Inst::WritesToSystemRegister() const {
+    switch (op) {
+    case Opcode::A64SetTPIDR:
+        return true;
+    default:
+        return false;
+    }
+}
+
 bool Inst::ReadsFromCoreRegister() const {
     switch (op) {
     case Opcode::A32GetRegister:
@@ -287,6 +296,7 @@ bool Inst::MayHaveSideEffects() const {
            op == Opcode::A64DataMemoryBarrier           ||
            CausesCPUException()                         ||
            WritesToCoreRegister()                       ||
+           WritesToSystemRegister()                     ||
            WritesToCPSR()                               ||
            WritesToFPSCR()                              ||
            AltersExclusiveState()                       ||
diff --git a/src/frontend/ir/microinstruction.h b/src/frontend/ir/microinstruction.h
index 2349797b..36a66083 100644
--- a/src/frontend/ir/microinstruction.h
+++ b/src/frontend/ir/microinstruction.h
@@ -55,6 +55,9 @@ public:
     /// Determines whether or not this instruction writes to the CPSR.
     bool WritesToCPSR() const;
 
+    /// Determines whether or not this instruction writes to a system register.
+    bool WritesToSystemRegister() const;
+
     /// Determines whether or not this instruction reads from a core register.
     bool ReadsFromCoreRegister() const;
     /// Determines whether or not this instruction writes to a core register.