From 48b2ffdde95c3bb9f330e7b2f3cd095ef679a298 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Mon, 22 Jun 2020 20:02:52 +0100 Subject: [PATCH] A32: Implement ASIMD VQMOVUN, VQMOVN --- src/frontend/A32/decoder/asimd.inc | 4 +-- .../translate/impl/asimd_two_regs_misc.cpp | 31 +++++++++++++++++++ .../A32/translate/impl/translate_arm.h | 2 ++ 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 10866222..4d5c5f14 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -122,8 +122,8 @@ INST(asimd_VTRN, "VTRN", "111100111D11zz10dddd000 INST(asimd_VUZP, "VUZP", "111100111D11zz10dddd00010QM0mmmm") // ASIMD INST(asimd_VZIP, "VZIP", "111100111D11zz10dddd00011QM0mmmm") // ASIMD INST(asimd_VMOVN, "VMOVN", "111100111D11zz10dddd001000M0mmmm") // ASIMD -//INST(asimd_VQMOVUN, "VQMOVUN", "111100111-11--10----001001-0----") // ASIMD -//INST(asimd_VQMOVN, "VQMOVN", "111100111-11--10----00101x-0----") // ASIMD +INST(asimd_VQMOVUN, "VQMOVUN", "111100111D11zz10dddd001001M0mmmm") // ASIMD +INST(asimd_VQMOVN, "VQMOVN", "111100111D11zz10dddd00101oM0mmmm") // ASIMD //INST(asimd_VSHLL_max, "VSHLL_max", "111100111-11--10----001100-0----") // ASIMD //INST(asimd_VCVT_half, "VCVT (half-precision)", "111100111-11--10----011x00-0----") // ASIMD INST(asimd_VRECPE, "VRECPE", "111100111D11zz11dddd010F0QM0mmmm") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp index f475c424..2ae5858a 100644 --- a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp +++ b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp @@ -564,6 +564,37 @@ bool ArmTranslatorVisitor::asimd_VMOVN(bool D, size_t sz, size_t Vd, bool M, siz return true; } +bool ArmTranslatorVisitor::asimd_VQMOVUN(bool D, size_t sz, size_t Vd, bool M, size_t Vm) { + if (sz == 0b11 || Common::Bit<0>(Vm)) { + return UndefinedInstruction(); + } + const size_t esize = 8U << sz; + const auto d = ToVector(false, Vd, D); + const auto m = ToVector(true, Vm, M); + + const auto reg_m = ir.GetVector(m); + const auto result = ir.VectorSignedSaturatedNarrowToUnsigned(2 * esize, reg_m); + + ir.SetVector(d, result); + return true; +} + +bool ArmTranslatorVisitor::asimd_VQMOVN(bool D, size_t sz, size_t Vd, bool op, bool M, size_t Vm) { + if (sz == 0b11 || Common::Bit<0>(Vm)) { + return UndefinedInstruction(); + } + const size_t esize = 8U << sz; + const auto d = ToVector(false, Vd, D); + const auto m = ToVector(true, Vm, M); + + const auto reg_m = ir.GetVector(m); + const auto result = op ? ir.VectorUnsignedSaturatedNarrow(2 * esize, reg_m) + : ir.VectorSignedSaturatedNarrowToSigned(2 * esize, reg_m); + + ir.SetVector(d, result); + return true; +} + bool ArmTranslatorVisitor::asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) { if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { return UndefinedInstruction(); diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index cfe57d52..2db6acfc 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -552,6 +552,8 @@ struct ArmTranslatorVisitor final { bool asimd_VUZP(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VZIP(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VMOVN(bool D, size_t sz, size_t Vd, bool M, size_t Vm); + bool asimd_VQMOVUN(bool D, size_t sz, size_t Vd, bool M, size_t Vm); + bool asimd_VQMOVN(bool D, size_t sz, size_t Vd, bool op, bool M, size_t Vm); bool asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); bool asimd_VRSQRTE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); bool asimd_VCVT_integer(bool D, size_t sz, size_t Vd, bool op, bool U, bool Q, bool M, size_t Vm);