From 4d6f68525de19ff782f01e342429424d6c2c9619 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Thu, 18 Jun 2020 22:16:44 -0400 Subject: [PATCH] A32: Implement ASIMD VADD (integer) --- src/frontend/A32/decoder/asimd.inc | 4 ++-- .../A32/translate/impl/asimd_three_same.cpp | 18 ++++++++++++++++++ .../A32/translate/impl/translate_arm.h | 1 + 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 402842be..12e0c999 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -21,8 +21,8 @@ INST(asimd_VQSUB, "VQSUB", "1111001U0Dzznnnndddd001 //INST(asimd_VMAX, "VMAX/VMIN", "1111001U0-CC--------0110---B----") // ASIMD //INST(asimd_VABD, "VABD/VABDL", "1111001U0-CC--------0111---0----") // ASIMD //INST(asimd_VABA, "VABA/ABAL", "1111001U0-CC--------0111---1----") // ASIMD -//INST(asimd_VADD_int, "VADD (integer)", "111100100-CC--------1000---0----") // ASIMD -//INST(asimd_VSUB_int, "VAND (integer)", "111100110-CC--------1000---0----") // ASIMD +INST(asimd_VADD_int, "VADD (integer)", "111100100Dzznnnndddd1000NQM0mmmm") // ASIMD +//INST(asimd_VSUB_int, "VSUB (integer)", "111100110-CC--------1000---0----") // ASIMD INST(asimd_VTST, "VTST", "111100100Dzznnnndddd1000NQM1mmmm") // ASIMD //INST(asimd_VCEQ_reg, "VCEG (register)", "111100110-CC--------1000---1----") // ASIMD //INST(asimd_VMLA, "VMLA/VMLAL/VMLS/VMLSL", "1111001U0-CC--------1001---0----") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_three_same.cpp b/src/frontend/A32/translate/impl/asimd_three_same.cpp index 587c51b7..ac2925b0 100644 --- a/src/frontend/A32/translate/impl/asimd_three_same.cpp +++ b/src/frontend/A32/translate/impl/asimd_three_same.cpp @@ -194,6 +194,24 @@ bool ArmTranslatorVisitor::asimd_VQSUB(bool U, bool D, size_t sz, size_t Vn, siz return true; } +bool ArmTranslatorVisitor::asimd_VADD_int(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { + if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + return UndefinedInstruction(); + } + + const size_t esize = 8U << sz; + const auto d = ToVector(Q, Vd, D); + const auto m = ToVector(Q, Vm, M); + const auto n = ToVector(Q, Vn, N); + + const auto reg_m = ir.GetVector(m); + const auto reg_n = ir.GetVector(n); + const auto result = ir.VectorAdd(esize, reg_m, reg_n); + + ir.SetVector(d, result); + return true; +} + bool ArmTranslatorVisitor::asimd_VTST(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { return UndefinedInstruction(); diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index 0f772839..ccb65bf0 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -450,6 +450,7 @@ struct ArmTranslatorVisitor final { bool asimd_VBIF(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VHSUB(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VQSUB(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); + bool asimd_VADD_int(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VTST(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); // Two registers and a shift amount