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backend/arm64: Implement And64

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Merry 2022-07-24 16:42:43 +01:00 committed by merry
parent 32e54481e7
commit 4e3fd70f6e
1 changed files with 26 additions and 18 deletions
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44
src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp
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@ -655,50 +655,58 @@ static void MaybeBitImm(oaknut::CodeGenerator& code, u64 imm, EmitFn emit_fn) {
} }
} }
template<> template<size_t bitsize, typename EmitFn1, typename EmitFn2>
void EmitIR<IR::Opcode::And32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { static void EmitBitOp(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, EmitFn1 emit_without_flags, EmitFn2 emit_with_flags) {
const auto nz_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZFromOp); const auto nz_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZFromOp);
const auto nzcv_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZCVFromOp); const auto nzcv_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZCVFromOp);
ASSERT(!(nz_inst && nzcv_inst)); ASSERT(!(nz_inst && nzcv_inst));
const auto flag_inst = nz_inst ? nz_inst : nzcv_inst; const auto flag_inst = nz_inst ? nz_inst : nzcv_inst;
auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto args = ctx.reg_alloc.GetArgumentInfo(inst);
auto Wresult = ctx.reg_alloc.WriteW(inst); auto Rresult = ctx.reg_alloc.WriteReg<bitsize>(inst);
auto Wa = ctx.reg_alloc.ReadW(args[0]); auto Ra = ctx.reg_alloc.ReadReg<bitsize>(args[0]);
if (flag_inst) { if (flag_inst) {
auto Wflags = ctx.reg_alloc.WriteFlags(flag_inst); auto Wflags = ctx.reg_alloc.WriteFlags(flag_inst);
if (args[1].IsImmediate()) { if (args[1].IsImmediate()) {
RegAlloc::Realize(Wresult, Wa, Wflags); RegAlloc::Realize(Rresult, Ra, Wflags);
MaybeBitImm<32>(code, args[1].GetImmediateU64(), [&](const auto& b) { code.ANDS(Wresult, Wa, b); }); MaybeBitImm<bitsize>(code, args[1].GetImmediateU64(), [&](const auto& b) { emit_with_flags(Rresult, Ra, b); });
} else { } else {
auto Wb = ctx.reg_alloc.ReadW(args[1]); auto Rb = ctx.reg_alloc.ReadReg<bitsize>(args[1]);
RegAlloc::Realize(Wresult, Wa, Wb, Wflags); RegAlloc::Realize(Rresult, Ra, Rb, Wflags);
code.ANDS(Wresult, Wb, Wb); emit_with_flags(Rresult, Ra, Rb);
} }
} else { } else {
if (args[1].IsImmediate()) { if (args[1].IsImmediate()) {
RegAlloc::Realize(Wresult, Wa); RegAlloc::Realize(Rresult, Ra);
MaybeBitImm<32>(code, args[1].GetImmediateU64(), [&](const auto& b) { code.AND(Wresult, Wa, b); }); MaybeBitImm<bitsize>(code, args[1].GetImmediateU64(), [&](const auto& b) { emit_without_flags(Rresult, Ra, b); });
} else { } else {
auto Wb = ctx.reg_alloc.ReadW(args[1]); auto Rb = ctx.reg_alloc.ReadReg<bitsize>(args[1]);
RegAlloc::Realize(Wresult, Wa, Wb); RegAlloc::Realize(Rresult, Ra, Rb);
code.AND(Wresult, Wb, Wb); emit_without_flags(Rresult, Rb, Rb);
} }
} }
} }
template<>
void EmitIR<IR::Opcode::And32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
EmitBitOp<32>(
code, ctx, inst,
[&](auto& result, auto& a, auto& b) { code.AND(result, a, b); },
[&](auto& result, auto& a, auto& b) { code.ANDS(result, a, b); });
}
template<> template<>
void EmitIR<IR::Opcode::And64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::And64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; EmitBitOp<64>(
(void)ctx; code, ctx, inst,
(void)inst; [&](auto& result, auto& a, auto& b) { code.AND(result, a, b); },
ASSERT_FALSE("Unimplemented"); [&](auto& result, auto& a, auto& b) { code.ANDS(result, a, b); });
} }
template<> template<>