diff --git a/.clang-format b/.clang-format new file mode 100644 index 00000000..5c5555ea --- /dev/null +++ b/.clang-format @@ -0,0 +1,218 @@ +--- +Language: Cpp +AccessModifierOffset: -4 +AlignAfterOpenBracket: Align +AlignConsecutiveMacros: None +AlignConsecutiveAssignments: None +AlignConsecutiveBitFields: None +AlignConsecutiveDeclarations: None +AlignConsecutiveMacros: None +AlignEscapedNewlines: Right +AlignOperands: AlignAfterOperator +AlignTrailingComments: true +AllowAllArgumentsOnNextLine: true +AllowAllConstructorInitializersOnNextLine: true +AllowAllParametersOfDeclarationOnNextLine: true +AllowShortEnumsOnASingleLine: true +AllowShortBlocksOnASingleLine: Empty +AllowShortCaseLabelsOnASingleLine: false +AllowShortFunctionsOnASingleLine: Inline +AllowShortLambdasOnASingleLine: All +AllowShortIfStatementsOnASingleLine: Never +AllowShortLoopsOnASingleLine: false +AlwaysBreakAfterDefinitionReturnType: None +AlwaysBreakAfterReturnType: None +AlwaysBreakBeforeMultilineStrings: true +AlwaysBreakTemplateDeclarations: Yes +AttributeMacros: + - __capability +BinPackArguments: true +BinPackParameters: false +BitFieldColonSpacing: Both +BraceWrapping: + AfterCaseLabel: false + AfterClass: false + AfterControlStatement: Never + AfterEnum: false + AfterFunction: false + AfterNamespace: false + AfterObjCDeclaration: false + AfterStruct: false + AfterUnion: false + AfterExternBlock: false + BeforeCatch: false + BeforeElse: false + BeforeLambdaBody: false + BeforeWhile: false + IndentBraces: false + SplitEmptyFunction: false + SplitEmptyRecord: false + SplitEmptyNamespace: false +BreakBeforeBinaryOperators: All +BreakBeforeBraces: Custom +BreakBeforeConceptDeclarations: true +BreakBeforeTernaryOperators: true +BreakBeforeInheritanceComma: false +BreakConstructorInitializersBeforeComma: true +BreakConstructorInitializers: BeforeComma +BreakInheritanceList: BeforeComma +BreakAfterJavaFieldAnnotations: false +BreakStringLiterals: true +ColumnLimit: 0 +CommentPragmas: '^ IWYU pragma:' +CompactNamespaces: false +ConstructorInitializerAllOnOneLineOrOnePerLine: true +ConstructorInitializerIndentWidth: 8 +ContinuationIndentWidth: 4 +Cpp11BracedListStyle: true +DeriveLineEnding: true +DerivePointerAlignment: false +DisableFormat: false +# EmptyLineAfterAccessModifier: Leave +EmptyLineBeforeAccessModifier: Always +ExperimentalAutoDetectBinPacking: false +FixNamespaceComments: true +ForEachMacros: + - foreach + - Q_FOREACH + - BOOST_FOREACH +IncludeBlocks: Regroup +IncludeCategories: + - Regex: '^' + Priority: 1 + SortPriority: 0 + CaseSensitive: false + - Regex: '(^)|(^)|(^)' + Priority: 1 + SortPriority: 0 + CaseSensitive: false + - Regex: '^<([^\.])*>$' + Priority: 2 + SortPriority: 0 + CaseSensitive: false + - Regex: '^<.*\.' + Priority: 3 + SortPriority: 0 + CaseSensitive: false + - Regex: '.*' + Priority: 4 + SortPriority: 0 + CaseSensitive: false +IncludeIsMainRegex: '([-_](test|unittest))?$' +IncludeIsMainSourceRegex: '' +# IndentAccessModifiers: false +IndentCaseBlocks: false +IndentCaseLabels: false +IndentExternBlock: NoIndent +IndentGotoLabels: false +IndentPPDirectives: AfterHash +IndentRequires: false +IndentWidth: 4 +IndentWrappedFunctionNames: false +# InsertTrailingCommas: None +JavaScriptQuotes: Leave +JavaScriptWrapImports: true +KeepEmptyLinesAtTheStartOfBlocks: false +MacroBlockBegin: '' +MacroBlockEnd: '' +MaxEmptyLinesToKeep: 1 +NamespaceIndentation: None +NamespaceMacros: +ObjCBinPackProtocolList: Never +ObjCBlockIndentWidth: 2 +ObjCBreakBeforeNestedBlockParam: true +ObjCSpaceAfterProperty: false +ObjCSpaceBeforeProtocolList: true +PenaltyBreakAssignment: 2 +PenaltyBreakBeforeFirstCallParameter: 1 +PenaltyBreakComment: 300 +PenaltyBreakFirstLessLess: 120 +PenaltyBreakString: 1000 +PenaltyBreakTemplateDeclaration: 10 +PenaltyExcessCharacter: 1000000 +PenaltyReturnTypeOnItsOwnLine: 200 +PenaltyIndentedWhitespace: 0 +PointerAlignment: Left +RawStringFormats: + - Language: Cpp + Delimiters: + - cc + - CC + - cpp + - Cpp + - CPP + - 'c++' + - 'C++' + CanonicalDelimiter: '' + BasedOnStyle: google + - Language: TextProto + Delimiters: + - pb + - PB + - proto + - PROTO + EnclosingFunctions: + - EqualsProto + - EquivToProto + - PARSE_PARTIAL_TEXT_PROTO + - PARSE_TEST_PROTO + - PARSE_TEXT_PROTO + - ParseTextOrDie + - ParseTextProtoOrDie + - ParseTestProto + - ParsePartialTestProto + CanonicalDelimiter: '' + BasedOnStyle: google +ReflowComments: true +# ShortNamespaceLines: 5 +SortIncludes: true +SortJavaStaticImport: Before +SortUsingDeclarations: true +SpaceAfterCStyleCast: false +SpaceAfterLogicalNot: false +SpaceAfterTemplateKeyword: false +SpaceAroundPointerQualifiers: Default +SpaceBeforeAssignmentOperators: true +SpaceBeforeCaseColon: false +SpaceBeforeCpp11BracedList: false +SpaceBeforeCtorInitializerColon: true +SpaceBeforeInheritanceColon: true +SpaceBeforeParens: ControlStatements +SpaceAroundPointerQualifiers: Default +SpaceBeforeRangeBasedForLoopColon: true +SpaceBeforeSquareBrackets: false +SpaceInEmptyBlock: false +SpaceInEmptyParentheses: false +SpacesBeforeTrailingComments: 2 +SpacesInAngles: false +SpacesInConditionalStatement: false +SpacesInCStyleCastParentheses: false +SpacesInConditionalStatement: false +SpacesInContainerLiterals: false +# SpacesInLineCommentPrefix: -1 +SpacesInParentheses: false +SpacesInSquareBrackets: false +Standard: Latest +StatementAttributeLikeMacros: + - Q_EMIT +StatementMacros: + - Q_UNUSED + - QT_REQUIRE_VERSION +TabWidth: 4 +TypenameMacros: +UseCRLF: false +UseTab: Never +WhitespaceSensitiveMacros: + - STRINGIZE + - PP_STRINGIZE + - BOOST_PP_STRINGIZE + - NS_SWIFT_NAME + - CF_SWIFT_NAME + - FCODE + - ICODE +... + diff --git a/src/dynarmic/backend/x64/a32_emit_x64.cpp b/src/dynarmic/backend/x64/a32_emit_x64.cpp index 56d20795..ea37b805 100644 --- a/src/dynarmic/backend/x64/a32_emit_x64.cpp +++ b/src/dynarmic/backend/x64/a32_emit_x64.cpp @@ -3,6 +3,8 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/backend/x64/a32_emit_x64.h" + #include #include #include @@ -11,7 +13,6 @@ #include #include -#include "dynarmic/backend/x64/a32_emit_x64.h" #include "dynarmic/backend/x64/a32_jitstate.h" #include "dynarmic/backend/x64/abi.h" #include "dynarmic/backend/x64/block_of_code.h" @@ -61,7 +62,7 @@ static Xbyak::Address MJitStateExtReg(A32::ExtReg reg) { } A32EmitContext::A32EmitContext(const A32::UserConfig& conf, RegAlloc& reg_alloc, IR::Block& block) - : EmitContext(reg_alloc, block), conf(conf) {} + : EmitContext(reg_alloc, block), conf(conf) {} A32::LocationDescriptor A32EmitContext::Location() const { return A32::LocationDescriptor{block.Location()}; @@ -87,7 +88,7 @@ A32EmitX64::A32EmitX64(BlockOfCode& code, A32::UserConfig conf, A32::Jit* jit_in code.PreludeComplete(); ClearFastDispatchTable(); - exception_handler.SetFastmemCallback([this](u64 rip_){ + exception_handler.SetFastmemCallback([this](u64 rip_) { return FastmemCallback(rip_); }); } @@ -98,7 +99,7 @@ A32EmitX64::BlockDescriptor A32EmitX64::Emit(IR::Block& block) { code.EnableWriting(); SCOPE_EXIT { code.DisableWriting(); }; - static const std::vector gpr_order = [this]{ + static const std::vector gpr_order = [this] { std::vector gprs{any_gpr}; if (conf.page_table) { gprs.erase(std::find(gprs.begin(), gprs.end(), HostLoc::R14)); @@ -126,15 +127,14 @@ A32EmitX64::BlockDescriptor A32EmitX64::Emit(IR::Block& block) { // Call the relevant Emit* member function. switch (inst->GetOpcode()) { - -#define OPCODE(name, type, ...) \ - case IR::Opcode::name: \ - A32EmitX64::Emit##name(ctx, inst); \ - break; -#define A32OPC(name, type, ...) \ - case IR::Opcode::A32##name: \ - A32EmitX64::EmitA32##name(ctx, inst); \ - break; +#define OPCODE(name, type, ...) \ + case IR::Opcode::name: \ + A32EmitX64::Emit##name(ctx, inst); \ + break; +#define A32OPC(name, type, ...) \ + case IR::Opcode::A32##name: \ + A32EmitX64::EmitA32##name(ctx, inst); \ + break; #define A64OPC(...) #include "dynarmic/ir/opcodes.inc" #undef OPCODE @@ -216,7 +216,7 @@ void A32EmitX64::GenFastmemFallbacks() { for (int value_idx : idxes) { for (const auto& [bitsize, callback] : read_callbacks) { code.align(); - read_fallbacks[std::make_tuple(bitsize, vaddr_idx, value_idx)] = code.getCurr(); + read_fallbacks[std::make_tuple(bitsize, vaddr_idx, value_idx)] = code.getCurr(); ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocRegIdx(value_idx)); if (vaddr_idx != code.ABI_PARAM2.getIdx()) { code.mov(code.ABI_PARAM2, Xbyak::Reg64{vaddr_idx}); @@ -232,7 +232,7 @@ void A32EmitX64::GenFastmemFallbacks() { for (const auto& [bitsize, callback] : write_callbacks) { code.align(); - write_fallbacks[std::make_tuple(bitsize, vaddr_idx, value_idx)] = code.getCurr(); + write_fallbacks[std::make_tuple(bitsize, vaddr_idx, value_idx)] = code.getCurr(); ABI_PushCallerSaveRegistersAndAdjustStack(code); if (vaddr_idx == code.ABI_PARAM3.getIdx() && value_idx == code.ABI_PARAM2.getIdx()) { code.xchg(code.ABI_PARAM2, code.ABI_PARAM3); @@ -310,7 +310,7 @@ void A32EmitX64::GenTerminalHandlers() { PerfMapRegister(terminal_handler_fast_dispatch_hint, code.getCurr(), "a32_terminal_handler_fast_dispatch_hint"); code.align(); - fast_dispatch_table_lookup = code.getCurr(); + fast_dispatch_table_lookup = code.getCurr(); code.mov(code.ABI_PARAM2, reinterpret_cast(fast_dispatch_table.data())); if (code.HasHostFeature(HostFeature::SSE42)) { code.crc32(code.ABI_PARAM1.cvt32(), code.ABI_PARAM2.cvt32()); @@ -728,7 +728,7 @@ void A32EmitX64::EmitA32DataMemoryBarrier(A32EmitContext&, IR::Inst*) { void A32EmitX64::EmitA32InstructionSynchronizationBarrier(A32EmitContext& ctx, IR::Inst*) { if (!conf.hook_isb) { - return; + return; } ctx.reg_alloc.HostCall(nullptr); @@ -766,7 +766,7 @@ void A32EmitX64::EmitA32BXWritePC(A32EmitContext& ctx, IR::Inst* inst) { code.mov(mask, new_pc); code.and_(mask, 1); code.lea(new_upper, ptr[mask.cvt64() + upper_without_t]); - code.lea(mask, ptr[mask.cvt64() + mask.cvt64() * 1 - 4]); // mask = pc & 1 ? 0xFFFFFFFE : 0xFFFFFFFC + code.lea(mask, ptr[mask.cvt64() + mask.cvt64() * 1 - 4]); // mask = pc & 1 ? 0xFFFFFFFE : 0xFFFFFFFC code.and_(new_pc, mask); code.mov(MJitStateReg(A32::Reg::PC), new_pc); code.mov(dword[r15 + offsetof(A32JitState, upper_location_descriptor)], new_upper); @@ -1021,7 +1021,7 @@ void EmitWriteMemoryMov(BlockOfCode& code, const Xbyak::RegExp& addr, const Xbya } } -} // anonymous namespace +} // anonymous namespace template void A32EmitX64::ReadMemory(A32EmitContext& ctx, IR::Inst* inst) { @@ -1048,8 +1048,7 @@ void A32EmitX64::ReadMemory(A32EmitContext& ctx, IR::Inst* inst) { Common::BitCast(code.getCurr()), Common::BitCast(wrapped_fn), *marker, - } - ); + }); ctx.reg_alloc.DefineValue(inst, value); return; @@ -1095,8 +1094,7 @@ void A32EmitX64::WriteMemory(A32EmitContext& ctx, IR::Inst* inst) { Common::BitCast(code.getCurr()), Common::BitCast(wrapped_fn), *marker, - } - ); + }); return; } @@ -1146,7 +1144,7 @@ void A32EmitX64::EmitA32WriteMemory64(A32EmitContext& ctx, IR::Inst* inst) { WriteMemory<64, &A32::UserCallbacks::MemoryWrite64>(ctx, inst); } -template +template void A32EmitX64::ExclusiveReadMemory(A32EmitContext& ctx, IR::Inst* inst) { using T = mp::unsigned_integer_of_size; @@ -1162,11 +1160,10 @@ void A32EmitX64::ExclusiveReadMemory(A32EmitContext& ctx, IR::Inst* inst) { return conf.global_monitor->ReadAndMark(conf.processor_id, vaddr, [&]() -> T { return (conf.callbacks->*callback)(vaddr); }); - } - ); + }); } -template +template void A32EmitX64::ExclusiveWriteMemory(A32EmitContext& ctx, IR::Inst* inst) { using T = mp::unsigned_integer_of_size; @@ -1185,11 +1182,12 @@ void A32EmitX64::ExclusiveWriteMemory(A32EmitContext& ctx, IR::Inst* inst) { code.CallLambda( [](A32::UserConfig& conf, u32 vaddr, T value) -> u32 { return conf.global_monitor->DoExclusiveOperation(conf.processor_id, vaddr, - [&](T expected) -> bool { - return (conf.callbacks->*callback)(vaddr, value, expected); - }) ? 0 : 1; - } - ); + [&](T expected) -> bool { + return (conf.callbacks->*callback)(vaddr, value, expected); + }) + ? 0 + : 1; + }); code.L(end); } @@ -1229,10 +1227,7 @@ static void EmitCoprocessorException() { ASSERT_FALSE("Should raise coproc exception here"); } -static void CallCoprocCallback(BlockOfCode& code, RegAlloc& reg_alloc, A32::Jit* jit_interface, - A32::Coprocessor::Callback callback, IR::Inst* inst = nullptr, - std::optional arg0 = {}, - std::optional arg1 = {}) { +static void CallCoprocCallback(BlockOfCode& code, RegAlloc& reg_alloc, A32::Jit* jit_interface, A32::Coprocessor::Callback callback, IR::Inst* inst = nullptr, std::optional arg0 = {}, std::optional arg1 = {}) { reg_alloc.HostCall(inst, {}, {}, arg0, arg1); code.mov(code.ABI_PARAM1, reinterpret_cast(jit_interface)); @@ -1519,7 +1514,7 @@ void A32EmitX64::EmitTerminalImpl(IR::Term::Interpret terminal, IR::LocationDesc code.mov(MJitStateReg(A32::Reg::PC), code.ABI_PARAM2.cvt32()); code.SwitchMxcsrOnExit(); Devirtualize<&A32::UserCallbacks::InterpreterFallback>(conf.callbacks).EmitCall(code); - code.ReturnFromRunCode(true); // TODO: Check cycles + code.ReturnFromRunCode(true); // TODO: Check cycles } void A32EmitX64::EmitTerminalImpl(IR::Term::ReturnToDispatch, IR::LocationDescriptor, bool) { @@ -1532,7 +1527,7 @@ void A32EmitX64::EmitSetUpperLocationDescriptor(IR::LocationDescriptor new_locat }; const u32 old_upper = get_upper(old_location); - const u32 new_upper = [&]{ + const u32 new_upper = [&] { const u32 mask = ~u32(conf.always_little_endian ? 0x2 : 0); return get_upper(new_location) & mask; }(); @@ -1666,4 +1661,4 @@ void A32EmitX64::Unpatch(const IR::LocationDescriptor& location) { } } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/a32_emit_x64.h b/src/dynarmic/backend/x64/a32_emit_x64.h index 385490db..f9836c63 100644 --- a/src/dynarmic/backend/x64/a32_emit_x64.h +++ b/src/dynarmic/backend/x64/a32_emit_x64.h @@ -71,8 +71,8 @@ protected: std::array fast_dispatch_table; void ClearFastDispatchTable(); - std::map, void(*)()> read_fallbacks; - std::map, void(*)()> write_fallbacks; + std::map, void (*)()> read_fallbacks; + std::map, void (*)()> write_fallbacks; void GenFastmemFallbacks(); const void* terminal_handler_pop_rsb_hint; @@ -133,4 +133,4 @@ protected: void EmitPatchMovRcx(CodePtr target_code_ptr = nullptr) override; }; -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/a32_interface.cpp b/src/dynarmic/backend/x64/a32_interface.cpp index e917a356..af0ee8ea 100644 --- a/src/dynarmic/backend/x64/a32_interface.cpp +++ b/src/dynarmic/backend/x64/a32_interface.cpp @@ -55,8 +55,7 @@ struct Jit::Impl { : block_of_code(GenRunCodeCallbacks(conf.callbacks, &GetCurrentBlockThunk, this), JitStateInfo{jit_state}, conf.code_cache_size, conf.far_code_offset, GenRCP(conf)) , emitter(block_of_code, conf, jit) , conf(std::move(conf)) - , jit_interface(jit) - {} + , jit_interface(jit) {} A32JitState jit_state; BlockOfCode block_of_code; @@ -70,7 +69,7 @@ struct Jit::Impl { bool invalidate_entire_cache = false; void Execute() { - const CodePtr current_codeptr = [this]{ + const CodePtr current_codeptr = [this] { // RSB optimization const u32 new_rsb_ptr = (jit_state.rsb_ptr - 1) & A32JitState::RSBPtrMask; if (jit_state.GetUniqueHash() == jit_state.rsb_location_descriptors[new_rsb_ptr]) { @@ -176,7 +175,8 @@ private: } }; -Jit::Jit(UserConfig conf) : impl(std::make_unique(this, std::move(conf))) {} +Jit::Jit(UserConfig conf) + : impl(std::make_unique(this, std::move(conf))) {} Jit::~Jit() = default; @@ -269,10 +269,15 @@ struct Context::Impl { size_t invalid_cache_generation; }; -Context::Context() : impl(std::make_unique()) { impl->jit_state.ResetRSB(); } +Context::Context() + : impl(std::make_unique()) { + impl->jit_state.ResetRSB(); +} Context::~Context() = default; -Context::Context(const Context& ctx) : impl(std::make_unique(*ctx.impl)) {} -Context::Context(Context&& ctx) noexcept : impl(std::move(ctx.impl)) {} +Context::Context(const Context& ctx) + : impl(std::make_unique(*ctx.impl)) {} +Context::Context(Context&& ctx) noexcept + : impl(std::move(ctx.impl)) {} Context& Context::operator=(const Context& ctx) { *impl = *ctx.impl; return *this; @@ -323,4 +328,4 @@ std::string Jit::Disassemble() const { return Common::DisassembleX64(impl->block_of_code.GetCodeBegin(), impl->block_of_code.getCurr()); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/backend/x64/a32_jitstate.cpp b/src/dynarmic/backend/x64/a32_jitstate.cpp index e98e5bd5..4d9cf07b 100644 --- a/src/dynarmic/backend/x64/a32_jitstate.cpp +++ b/src/dynarmic/backend/x64/a32_jitstate.cpp @@ -4,6 +4,7 @@ */ #include "dynarmic/backend/x64/a32_jitstate.h" + #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/nzcv_util.h" #include "dynarmic/common/assert.h" @@ -89,7 +90,7 @@ void A32JitState::SetCpsr(u32 cpsr) { upper_location_descriptor |= Common::Bit<9>(cpsr) ? 2 : 0; upper_location_descriptor |= Common::Bit<5>(cpsr) ? 1 : 0; // IT state - upper_location_descriptor |= (cpsr >> 0) & 0b11111100'00000000; + upper_location_descriptor |= (cpsr >> 0) & 0b11111100'00000000; upper_location_descriptor |= (cpsr >> 17) & 0b00000011'00000000; // Other flags @@ -188,7 +189,7 @@ void A32JitState::SetFpscr(u32 FPSCR) { asimd_MXCSR = 0x00009fc0; // RMode - const std::array MXCSR_RMode {0x0, 0x4000, 0x2000, 0x6000}; + const std::array MXCSR_RMode{0x0, 0x4000, 0x2000, 0x6000}; guest_MXCSR |= MXCSR_RMode[(FPSCR >> 22) & 0x3]; // Cumulative flags IDC, IOC, IXC, UFC, OFC, DZC @@ -196,9 +197,9 @@ void A32JitState::SetFpscr(u32 FPSCR) { if (Common::Bit<24>(FPSCR)) { // VFP Flush to Zero - guest_MXCSR |= (1 << 15); // SSE Flush to Zero - guest_MXCSR |= (1 << 6); // SSE Denormals are Zero + guest_MXCSR |= (1 << 15); // SSE Flush to Zero + guest_MXCSR |= (1 << 6); // SSE Denormals are Zero } } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/a32_jitstate.h b/src/dynarmic/backend/x64/a32_jitstate.h index c52b5427..68e37c6c 100644 --- a/src/dynarmic/backend/x64/a32_jitstate.h +++ b/src/dynarmic/backend/x64/a32_jitstate.h @@ -16,8 +16,8 @@ namespace Dynarmic::Backend::X64 { class BlockOfCode; #ifdef _MSC_VER -#pragma warning(push) -#pragma warning(disable:4324) // Structure was padded due to alignment specifier +# pragma warning(push) +# pragma warning(disable : 4324) // Structure was padded due to alignment specifier #endif struct A32JitState { @@ -25,7 +25,7 @@ struct A32JitState { A32JitState() { ResetRSB(); } - std::array Reg{}; // Current register file. + std::array Reg{}; // Current register file. // TODO: Mode-specific register sets unimplemented. u32 upper_location_descriptor = 0; @@ -37,7 +37,7 @@ struct A32JitState { u32 Cpsr() const; void SetCpsr(u32 cpsr); - alignas(16) std::array ExtReg{}; // Extension registers. + alignas(16) std::array ExtReg{}; // Extension registers. // For internal use (See: BlockOfCode::RunCode) u32 guest_MXCSR = 0x00001f80; @@ -47,7 +47,7 @@ struct A32JitState { // Exclusive state u32 exclusive_state = 0; - static constexpr size_t RSBSize = 8; // MUST be a power of 2. + static constexpr size_t RSBSize = 8; // MUST be a power of 2. static constexpr size_t RSBPtrMask = RSBSize - 1; u32 rsb_ptr = 0; std::array rsb_location_descriptors; @@ -55,7 +55,7 @@ struct A32JitState { void ResetRSB(); u32 fpsr_exc = 0; - u32 fpsr_qc = 0; // Dummy value + u32 fpsr_qc = 0; // Dummy value u32 fpsr_nzcv = 0; u32 Fpscr() const; void SetFpscr(u32 FPSCR); @@ -91,9 +91,9 @@ struct A32JitState { }; #ifdef _MSC_VER -#pragma warning(pop) +# pragma warning(pop) #endif using CodePtr = const void*; -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/a64_emit_x64.cpp b/src/dynarmic/backend/x64/a64_emit_x64.cpp index 7c6fdc35..a1078524 100644 --- a/src/dynarmic/backend/x64/a64_emit_x64.cpp +++ b/src/dynarmic/backend/x64/a64_emit_x64.cpp @@ -3,13 +3,14 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/backend/x64/a64_emit_x64.h" + #include #include #include #include -#include "dynarmic/backend/x64/a64_emit_x64.h" #include "dynarmic/backend/x64/a64_jitstate.h" #include "dynarmic/backend/x64/abi.h" #include "dynarmic/backend/x64/block_of_code.h" @@ -38,7 +39,7 @@ namespace Dynarmic::Backend::X64 { using namespace Xbyak::util; A64EmitContext::A64EmitContext(const A64::UserConfig& conf, RegAlloc& reg_alloc, IR::Block& block) - : EmitContext(reg_alloc, block), conf(conf) {} + : EmitContext(reg_alloc, block), conf(conf) {} A64::LocationDescriptor A64EmitContext::Location() const { return A64::LocationDescriptor{block.Location()}; @@ -67,7 +68,7 @@ A64EmitX64::BlockDescriptor A64EmitX64::Emit(IR::Block& block) { code.EnableWriting(); SCOPE_EXIT { code.DisableWriting(); }; - static const std::vector gpr_order = [this]{ + static const std::vector gpr_order = [this] { std::vector gprs{any_gpr}; if (conf.page_table) { gprs.erase(std::find(gprs.begin(), gprs.end(), HostLoc::R14)); @@ -92,16 +93,15 @@ A64EmitX64::BlockDescriptor A64EmitX64::Emit(IR::Block& block) { // Call the relevant Emit* member function. switch (inst->GetOpcode()) { - -#define OPCODE(name, type, ...) \ - case IR::Opcode::name: \ - A64EmitX64::Emit##name(ctx, inst); \ - break; +#define OPCODE(name, type, ...) \ + case IR::Opcode::name: \ + A64EmitX64::Emit##name(ctx, inst); \ + break; #define A32OPC(...) -#define A64OPC(name, type, ...) \ - case IR::Opcode::A64##name: \ - A64EmitX64::EmitA64##name(ctx, inst); \ - break; +#define A64OPC(name, type, ...) \ + case IR::Opcode::A64##name: \ + A64EmitX64::EmitA64##name(ctx, inst); \ + break; #include "dynarmic/ir/opcodes.inc" #undef OPCODE #undef A32OPC @@ -150,14 +150,13 @@ void A64EmitX64::ClearFastDispatchTable() { void A64EmitX64::GenMemory128Accessors() { code.align(); - memory_read_128 = code.getCurr(); + memory_read_128 = code.getCurr(); #ifdef _WIN32 - Devirtualize<&A64::UserCallbacks::MemoryRead128>(conf.callbacks).EmitCallWithReturnPointer(code, - [&](Xbyak::Reg64 return_value_ptr, [[maybe_unused]] RegList args) { - code.mov(code.ABI_PARAM3, code.ABI_PARAM2); - code.sub(rsp, 8 + 16 + ABI_SHADOW_SPACE); - code.lea(return_value_ptr, ptr[rsp + ABI_SHADOW_SPACE]); - }); + Devirtualize<&A64::UserCallbacks::MemoryRead128>(conf.callbacks).EmitCallWithReturnPointer(code, [&](Xbyak::Reg64 return_value_ptr, [[maybe_unused]] RegList args) { + code.mov(code.ABI_PARAM3, code.ABI_PARAM2); + code.sub(rsp, 8 + 16 + ABI_SHADOW_SPACE); + code.lea(return_value_ptr, ptr[rsp + ABI_SHADOW_SPACE]); + }); code.movups(xmm1, xword[code.ABI_RETURN]); code.add(rsp, 8 + 16 + ABI_SHADOW_SPACE); #else @@ -177,7 +176,7 @@ void A64EmitX64::GenMemory128Accessors() { PerfMapRegister(memory_read_128, code.getCurr(), "a64_memory_read_128"); code.align(); - memory_write_128 = code.getCurr(); + memory_write_128 = code.getCurr(); #ifdef _WIN32 code.sub(rsp, 8 + 16 + ABI_SHADOW_SPACE); code.lea(code.ABI_PARAM3, ptr[rsp + ABI_SHADOW_SPACE]); @@ -223,7 +222,7 @@ void A64EmitX64::GenFastmemFallbacks() { for (int value_idx : idxes) { code.align(); - read_fallbacks[std::make_tuple(128, vaddr_idx, value_idx)] = code.getCurr(); + read_fallbacks[std::make_tuple(128, vaddr_idx, value_idx)] = code.getCurr(); ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(value_idx)); if (vaddr_idx != code.ABI_PARAM2.getIdx()) { code.mov(code.ABI_PARAM2, Xbyak::Reg64{vaddr_idx}); @@ -237,7 +236,7 @@ void A64EmitX64::GenFastmemFallbacks() { PerfMapRegister(read_fallbacks[std::make_tuple(128, vaddr_idx, value_idx)], code.getCurr(), "a64_read_fallback_128"); code.align(); - write_fallbacks[std::make_tuple(128, vaddr_idx, value_idx)] = code.getCurr(); + write_fallbacks[std::make_tuple(128, vaddr_idx, value_idx)] = code.getCurr(); ABI_PushCallerSaveRegistersAndAdjustStack(code); if (vaddr_idx != code.ABI_PARAM2.getIdx()) { code.mov(code.ABI_PARAM2, Xbyak::Reg64{vaddr_idx}); @@ -256,7 +255,7 @@ void A64EmitX64::GenFastmemFallbacks() { for (const auto& [bitsize, callback] : read_callbacks) { code.align(); - read_fallbacks[std::make_tuple(bitsize, vaddr_idx, value_idx)] = code.getCurr(); + read_fallbacks[std::make_tuple(bitsize, vaddr_idx, value_idx)] = code.getCurr(); ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocRegIdx(value_idx)); if (vaddr_idx != code.ABI_PARAM2.getIdx()) { code.mov(code.ABI_PARAM2, Xbyak::Reg64{vaddr_idx}); @@ -272,7 +271,7 @@ void A64EmitX64::GenFastmemFallbacks() { for (const auto& [bitsize, callback] : write_callbacks) { code.align(); - write_fallbacks[std::make_tuple(bitsize, vaddr_idx, value_idx)] = code.getCurr(); + write_fallbacks[std::make_tuple(bitsize, vaddr_idx, value_idx)] = code.getCurr(); ABI_PushCallerSaveRegistersAndAdjustStack(code); if (vaddr_idx == code.ABI_PARAM3.getIdx() && value_idx == code.ABI_PARAM2.getIdx()) { code.xchg(code.ABI_PARAM2, code.ABI_PARAM3); @@ -353,7 +352,7 @@ void A64EmitX64::GenTerminalHandlers() { PerfMapRegister(terminal_handler_fast_dispatch_hint, code.getCurr(), "a64_terminal_handler_fast_dispatch_hint"); code.align(); - fast_dispatch_table_lookup = code.getCurr(); + fast_dispatch_table_lookup = code.getCurr(); code.mov(code.ABI_PARAM2, reinterpret_cast(fast_dispatch_table.data())); if (code.HasHostFeature(HostFeature::SSE42)) { code.crc32(code.ABI_PARAM1, code.ABI_PARAM2); @@ -542,7 +541,7 @@ void A64EmitX64::EmitA64SetD(A64EmitContext& ctx, IR::Inst* inst) { const auto addr = xword[r15 + offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast(vec)]; const Xbyak::Xmm to_store = ctx.reg_alloc.UseScratchXmm(args[1]); - code.movq(to_store, to_store); // TODO: Remove when able + code.movq(to_store, to_store); // TODO: Remove when able code.movaps(addr, to_store); } @@ -628,10 +627,9 @@ void A64EmitX64::EmitA64CallSupervisor(A64EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); ASSERT(args[0].IsImmediate()); const u32 imm = args[0].GetImmediateU32(); - Devirtualize<&A64::UserCallbacks::CallSVC>(conf.callbacks).EmitCall(code, - [&](RegList param) { - code.mov(param[0], imm); - }); + Devirtualize<&A64::UserCallbacks::CallSVC>(conf.callbacks).EmitCall(code, [&](RegList param) { + code.mov(param[0], imm); + }); // The kernel would have to execute ERET to get here, which would clear exclusive state. code.mov(code.byte[r15 + offsetof(A64JitState, exclusive_state)], u8(0)); } @@ -642,11 +640,10 @@ void A64EmitX64::EmitA64ExceptionRaised(A64EmitContext& ctx, IR::Inst* inst) { ASSERT(args[0].IsImmediate() && args[1].IsImmediate()); const u64 pc = args[0].GetImmediateU64(); const u64 exception = args[1].GetImmediateU64(); - Devirtualize<&A64::UserCallbacks::ExceptionRaised>(conf.callbacks).EmitCall(code, - [&](RegList param) { - code.mov(param[0], pc); - code.mov(param[1], exception); - }); + Devirtualize<&A64::UserCallbacks::ExceptionRaised>(conf.callbacks).EmitCall(code, [&](RegList param) { + code.mov(param[0], pc); + code.mov(param[1], exception); + }); } void A64EmitX64::EmitA64DataCacheOperationRaised(A64EmitContext& ctx, IR::Inst* inst) { @@ -881,7 +878,7 @@ void EmitWriteMemoryMov(BlockOfCode& code, const Xbyak::RegExp& addr, const Xbya } } -} // anonymous namepsace +} // namespace template void A64EmitX64::EmitDirectPageTableMemoryRead(A64EmitContext& ctx, IR::Inst* inst) { @@ -1090,8 +1087,7 @@ void A64EmitX64::EmitExclusiveReadMemory(A64EmitContext& ctx, IR::Inst* inst) { return conf.global_monitor->ReadAndMark(conf.processor_id, vaddr, [&]() -> T { return (conf.callbacks->*callback)(vaddr); }); - } - ); + }); } else { const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(); ctx.reg_alloc.Use(args[0], ABI_PARAM2); @@ -1107,8 +1103,7 @@ void A64EmitX64::EmitExclusiveReadMemory(A64EmitContext& ctx, IR::Inst* inst) { ret = conf.global_monitor->ReadAndMark(conf.processor_id, vaddr, [&]() -> A64::Vector { return (conf.callbacks->*callback)(vaddr); }); - } - ); + }); code.movups(result, xword[rsp + ABI_SHADOW_SPACE]); ctx.reg_alloc.ReleaseStackSpace(16 + ABI_SHADOW_SPACE); @@ -1163,11 +1158,12 @@ void A64EmitX64::EmitExclusiveWriteMemory(A64EmitContext& ctx, IR::Inst* inst) { code.CallLambda( [](A64::UserConfig& conf, u64 vaddr, T value) -> u32 { return conf.global_monitor->DoExclusiveOperation(conf.processor_id, vaddr, - [&](T expected) -> bool { - return (conf.callbacks->*callback)(vaddr, value, expected); - }) ? 0 : 1; - } - ); + [&](T expected) -> bool { + return (conf.callbacks->*callback)(vaddr, value, expected); + }) + ? 0 + : 1; + }); } else { ctx.reg_alloc.AllocStackSpace(16 + ABI_SHADOW_SPACE); code.lea(code.ABI_PARAM3, ptr[rsp + ABI_SHADOW_SPACE]); @@ -1175,11 +1171,12 @@ void A64EmitX64::EmitExclusiveWriteMemory(A64EmitContext& ctx, IR::Inst* inst) { code.CallLambda( [](A64::UserConfig& conf, u64 vaddr, A64::Vector& value) -> u32 { return conf.global_monitor->DoExclusiveOperation(conf.processor_id, vaddr, - [&](A64::Vector expected) -> bool { - return (conf.callbacks->*callback)(vaddr, value, expected); - }) ? 0 : 1; - } - ); + [&](A64::Vector expected) -> bool { + return (conf.callbacks->*callback)(vaddr, value, expected); + }) + ? 0 + : 1; + }); ctx.reg_alloc.ReleaseStackSpace(16 + ABI_SHADOW_SPACE); } code.L(end); @@ -1214,13 +1211,12 @@ std::string A64EmitX64::LocationDescriptorToFriendlyName(const IR::LocationDescr void A64EmitX64::EmitTerminalImpl(IR::Term::Interpret terminal, IR::LocationDescriptor, bool) { code.SwitchMxcsrOnExit(); - Devirtualize<&A64::UserCallbacks::InterpreterFallback>(conf.callbacks).EmitCall(code, - [&](RegList param) { - code.mov(param[0], A64::LocationDescriptor{terminal.next}.PC()); - code.mov(qword[r15 + offsetof(A64JitState, pc)], param[0]); - code.mov(param[1].cvt32(), terminal.num_instructions); - }); - code.ReturnFromRunCode(true); // TODO: Check cycles + Devirtualize<&A64::UserCallbacks::InterpreterFallback>(conf.callbacks).EmitCall(code, [&](RegList param) { + code.mov(param[0], A64::LocationDescriptor{terminal.next}.PC()); + code.mov(qword[r15 + offsetof(A64JitState, pc)], param[0]); + code.mov(param[1].cvt32(), terminal.num_instructions); + }); + code.ReturnFromRunCode(true); // TODO: Check cycles } void A64EmitX64::EmitTerminalImpl(IR::Term::ReturnToDispatch, IR::LocationDescriptor, bool) { @@ -1352,4 +1348,4 @@ void A64EmitX64::Unpatch(const IR::LocationDescriptor& location) { } } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/a64_emit_x64.h b/src/dynarmic/backend/x64/a64_emit_x64.h index 7844d653..8d886038 100644 --- a/src/dynarmic/backend/x64/a64_emit_x64.h +++ b/src/dynarmic/backend/x64/a64_emit_x64.h @@ -69,8 +69,8 @@ protected: void (*memory_write_128)(); void GenMemory128Accessors(); - std::map, void(*)()> read_fallbacks; - std::map, void(*)()> write_fallbacks; + std::map, void (*)()> read_fallbacks; + std::map, void (*)()> write_fallbacks; void GenFastmemFallbacks(); const void* terminal_handler_pop_rsb_hint; @@ -118,4 +118,4 @@ protected: void EmitPatchMovRcx(CodePtr target_code_ptr = nullptr) override; }; -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/a64_interface.cpp b/src/dynarmic/backend/x64/a64_interface.cpp index 1f80b34a..a758672a 100644 --- a/src/dynarmic/backend/x64/a64_interface.cpp +++ b/src/dynarmic/backend/x64/a64_interface.cpp @@ -44,10 +44,9 @@ static std::function GenRCP(const A64::UserConfig& conf) { struct Jit::Impl final { public: Impl(Jit* jit, UserConfig conf) - : conf(conf) - , block_of_code(GenRunCodeCallbacks(conf.callbacks, &GetCurrentBlockThunk, this), JitStateInfo{jit_state}, conf.code_cache_size, conf.far_code_offset, GenRCP(conf)) - , emitter(block_of_code, conf, jit) - { + : conf(conf) + , block_of_code(GenRunCodeCallbacks(conf.callbacks, &GetCurrentBlockThunk, this), JitStateInfo{jit_state}, conf.code_cache_size, conf.far_code_offset, GenRCP(conf)) + , emitter(block_of_code, conf, jit) { ASSERT(conf.page_table_address_space_bits >= 12 && conf.page_table_address_space_bits <= 64); } @@ -61,7 +60,7 @@ public: // TODO: Check code alignment - const CodePtr current_code_ptr = [this]{ + const CodePtr current_code_ptr = [this] { // RSB optimization const u32 new_rsb_ptr = (jit_state.rsb_ptr - 1) & A64JitState::RSBPtrMask; if (jit_state.GetUniqueHash() == jit_state.rsb_location_descriptors[new_rsb_ptr]) { @@ -233,7 +232,7 @@ private: // JIT Compile const auto get_code = [this](u64 vaddr) { return conf.callbacks->MemoryReadCode(vaddr); }; IR::Block ir_block = A64::Translate(A64::LocationDescriptor{current_location}, get_code, - {conf.define_unpredictable_behaviour, conf.wall_clock_cntpct}); + {conf.define_unpredictable_behaviour, conf.wall_clock_cntpct}); Optimization::A64CallbackConfigPass(ir_block, conf); if (conf.HasOptimization(OptimizationFlag::GetSetElimination)) { Optimization::A64GetSetElimination(ir_block); @@ -287,7 +286,7 @@ private: }; Jit::Jit(UserConfig conf) - : impl(std::make_unique(this, conf)) {} + : impl(std::make_unique(this, conf)) {} Jit::~Jit() = default; @@ -399,4 +398,4 @@ std::string Jit::Disassemble() const { return impl->Disassemble(); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/backend/x64/a64_jitstate.cpp b/src/dynarmic/backend/x64/a64_jitstate.cpp index 74be862f..c0e7a1c6 100644 --- a/src/dynarmic/backend/x64/a64_jitstate.cpp +++ b/src/dynarmic/backend/x64/a64_jitstate.cpp @@ -4,6 +4,7 @@ */ #include "dynarmic/backend/x64/a64_jitstate.h" + #include "dynarmic/common/bit_util.h" #include "dynarmic/frontend/A64/location_descriptor.h" @@ -58,15 +59,15 @@ void A64JitState::SetFpcr(u32 value) { asimd_MXCSR &= 0x0000003D; guest_MXCSR &= 0x0000003D; asimd_MXCSR |= 0x00001f80; - guest_MXCSR |= 0x00001f80; // Mask all exceptions + guest_MXCSR |= 0x00001f80; // Mask all exceptions // RMode - const std::array MXCSR_RMode {0x0, 0x4000, 0x2000, 0x6000}; + const std::array MXCSR_RMode{0x0, 0x4000, 0x2000, 0x6000}; guest_MXCSR |= MXCSR_RMode[(value >> 22) & 0x3]; if (Common::Bit<24>(value)) { - guest_MXCSR |= (1 << 15); // SSE Flush to Zero - guest_MXCSR |= (1 << 6); // SSE Denormals are Zero + guest_MXCSR |= (1 << 15); // SSE Flush to Zero + guest_MXCSR |= (1 << 6); // SSE Denormals are Zero } } @@ -111,4 +112,4 @@ void A64JitState::SetFpsr(u32 value) { fpsr_exc = value & 0x9F; } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/a64_jitstate.h b/src/dynarmic/backend/x64/a64_jitstate.h index 4e47f180..40cd9cc5 100644 --- a/src/dynarmic/backend/x64/a64_jitstate.h +++ b/src/dynarmic/backend/x64/a64_jitstate.h @@ -18,8 +18,8 @@ namespace Dynarmic::Backend::X64 { class BlockOfCode; #ifdef _MSC_VER -#pragma warning(push) -#pragma warning(disable:4324) // Structure was padded due to alignment specifier +# pragma warning(push) +# pragma warning(disable : 4324) // Structure was padded due to alignment specifier #endif struct A64JitState { @@ -40,7 +40,7 @@ struct A64JitState { cpsr_nzcv = NZCV::ToX64(new_pstate); } - alignas(16) std::array vec{}; // Extension registers. + alignas(16) std::array vec{}; // Extension registers. // For internal use (See: BlockOfCode::RunCode) u32 guest_MXCSR = 0x00001f80; @@ -51,7 +51,7 @@ struct A64JitState { static constexpr u64 RESERVATION_GRANULE_MASK = 0xFFFF'FFFF'FFFF'FFF0ull; u8 exclusive_state = 0; - static constexpr size_t RSBSize = 8; // MUST be a power of 2. + static constexpr size_t RSBSize = 8; // MUST be a power of 2. static constexpr size_t RSBPtrMask = RSBSize - 1; u32 rsb_ptr = 0; std::array rsb_location_descriptors; @@ -77,9 +77,9 @@ struct A64JitState { }; #ifdef _MSC_VER -#pragma warning(pop) +# pragma warning(pop) #endif using CodePtr = const void*; -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/abi.cpp b/src/dynarmic/backend/x64/abi.cpp index 0bf31654..b1c16a2d 100644 --- a/src/dynarmic/backend/x64/abi.cpp +++ b/src/dynarmic/backend/x64/abi.cpp @@ -3,12 +3,13 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/backend/x64/abi.h" + #include #include #include -#include "dynarmic/backend/x64/abi.h" #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/common/common_types.h" #include "dynarmic/common/iterator_util.h" @@ -131,4 +132,4 @@ void ABI_PopCallerSaveRegistersAndAdjustStackExcept(BlockOfCode& code, HostLoc e ABI_PopRegistersAndAdjustStack(code, 0, regs); } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/abi.h b/src/dynarmic/backend/x64/abi.h index 3a848d20..0ccc92ba 100644 --- a/src/dynarmic/backend/x64/abi.h +++ b/src/dynarmic/backend/x64/abi.h @@ -61,7 +61,7 @@ constexpr std::array ABI_ALL_CALLEE_SAVE = { HostLoc::XMM15, }; -constexpr size_t ABI_SHADOW_SPACE = 32; // bytes +constexpr size_t ABI_SHADOW_SPACE = 32; // bytes #else @@ -114,7 +114,7 @@ constexpr std::array ABI_ALL_CALLEE_SAVE = { HostLoc::R15, }; -constexpr size_t ABI_SHADOW_SPACE = 0; // bytes +constexpr size_t ABI_SHADOW_SPACE = 0; // bytes #endif @@ -128,4 +128,4 @@ void ABI_PopCallerSaveRegistersAndAdjustStack(BlockOfCode& code, size_t frame_si void ABI_PushCallerSaveRegistersAndAdjustStackExcept(BlockOfCode& code, HostLoc exception); void ABI_PopCallerSaveRegistersAndAdjustStackExcept(BlockOfCode& code, HostLoc exception); -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/block_of_code.cpp b/src/dynarmic/backend/x64/block_of_code.cpp index a981b7cb..9e03143f 100644 --- a/src/dynarmic/backend/x64/block_of_code.cpp +++ b/src/dynarmic/backend/x64/block_of_code.cpp @@ -3,6 +3,15 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/backend/x64/block_of_code.h" + +#ifdef _WIN32 +# define WIN32_LEAN_AND_MEAN +# include +#else +# include +#endif + #include #include @@ -10,19 +19,12 @@ #include "dynarmic/backend/x64/a32_jitstate.h" #include "dynarmic/backend/x64/abi.h" -#include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/hostloc.h" #include "dynarmic/backend/x64/perf_map.h" #include "dynarmic/backend/x64/stack_layout.h" #include "dynarmic/common/assert.h" #include "dynarmic/common/bit_util.h" -#ifdef _WIN32 - #include -#else - #include -#endif - namespace Dynarmic::Backend::X64 { #ifdef _WIN32 @@ -60,47 +62,66 @@ CustomXbyakAllocator s_allocator; #ifdef DYNARMIC_ENABLE_NO_EXECUTE_SUPPORT void ProtectMemory(const void* base, size_t size, bool is_executable) { -#ifdef _WIN32 +# ifdef _WIN32 DWORD oldProtect = 0; VirtualProtect(const_cast(base), size, is_executable ? PAGE_EXECUTE_READ : PAGE_READWRITE, &oldProtect); -#else +# else static const size_t pageSize = sysconf(_SC_PAGESIZE); const size_t iaddr = reinterpret_cast(base); const size_t roundAddr = iaddr & ~(pageSize - static_cast(1)); const int mode = is_executable ? (PROT_READ | PROT_EXEC) : (PROT_READ | PROT_WRITE); mprotect(reinterpret_cast(roundAddr), size + (iaddr - roundAddr), mode); -#endif +# endif } #endif -HostFeature GetHostFeatures() -{ +HostFeature GetHostFeatures() { HostFeature features = {}; #ifdef DYNARMIC_ENABLE_CPU_FEATURE_DETECTION using Cpu = Xbyak::util::Cpu; Xbyak::util::Cpu cpu_info; - if (cpu_info.has(Cpu::tSSSE3)) features |= HostFeature::SSSE3; - if (cpu_info.has(Cpu::tSSE41)) features |= HostFeature::SSE41; - if (cpu_info.has(Cpu::tSSE42)) features |= HostFeature::SSE42; - if (cpu_info.has(Cpu::tAVX)) features |= HostFeature::AVX; - if (cpu_info.has(Cpu::tAVX2)) features |= HostFeature::AVX2; - if (cpu_info.has(Cpu::tAVX512F)) features |= HostFeature::AVX512F; - if (cpu_info.has(Cpu::tAVX512CD)) features |= HostFeature::AVX512CD; - if (cpu_info.has(Cpu::tAVX512VL)) features |= HostFeature::AVX512VL; - if (cpu_info.has(Cpu::tAVX512BW)) features |= HostFeature::AVX512BW; - if (cpu_info.has(Cpu::tAVX512DQ)) features |= HostFeature::AVX512DQ; - if (cpu_info.has(Cpu::tAVX512_BITALG)) features |= HostFeature::AVX512BITALG; - if (cpu_info.has(Cpu::tPCLMULQDQ)) features |= HostFeature::PCLMULQDQ; - if (cpu_info.has(Cpu::tF16C)) features |= HostFeature::F16C; - if (cpu_info.has(Cpu::tFMA)) features |= HostFeature::FMA; - if (cpu_info.has(Cpu::tAESNI)) features |= HostFeature::AES; - if (cpu_info.has(Cpu::tPOPCNT)) features |= HostFeature::POPCNT; - if (cpu_info.has(Cpu::tBMI1)) features |= HostFeature::BMI1; - if (cpu_info.has(Cpu::tBMI2)) features |= HostFeature::BMI2; - if (cpu_info.has(Cpu::tLZCNT)) features |= HostFeature::LZCNT; - if (cpu_info.has(Cpu::tGFNI)) features |= HostFeature::GFNI; + if (cpu_info.has(Cpu::tSSSE3)) + features |= HostFeature::SSSE3; + if (cpu_info.has(Cpu::tSSE41)) + features |= HostFeature::SSE41; + if (cpu_info.has(Cpu::tSSE42)) + features |= HostFeature::SSE42; + if (cpu_info.has(Cpu::tAVX)) + features |= HostFeature::AVX; + if (cpu_info.has(Cpu::tAVX2)) + features |= HostFeature::AVX2; + if (cpu_info.has(Cpu::tAVX512F)) + features |= HostFeature::AVX512F; + if (cpu_info.has(Cpu::tAVX512CD)) + features |= HostFeature::AVX512CD; + if (cpu_info.has(Cpu::tAVX512VL)) + features |= HostFeature::AVX512VL; + if (cpu_info.has(Cpu::tAVX512BW)) + features |= HostFeature::AVX512BW; + if (cpu_info.has(Cpu::tAVX512DQ)) + features |= HostFeature::AVX512DQ; + if (cpu_info.has(Cpu::tAVX512_BITALG)) + features |= HostFeature::AVX512BITALG; + if (cpu_info.has(Cpu::tPCLMULQDQ)) + features |= HostFeature::PCLMULQDQ; + if (cpu_info.has(Cpu::tF16C)) + features |= HostFeature::F16C; + if (cpu_info.has(Cpu::tFMA)) + features |= HostFeature::FMA; + if (cpu_info.has(Cpu::tAESNI)) + features |= HostFeature::AES; + if (cpu_info.has(Cpu::tPOPCNT)) + features |= HostFeature::POPCNT; + if (cpu_info.has(Cpu::tBMI1)) + features |= HostFeature::BMI1; + if (cpu_info.has(Cpu::tBMI2)) + features |= HostFeature::BMI2; + if (cpu_info.has(Cpu::tLZCNT)) + features |= HostFeature::LZCNT; + if (cpu_info.has(Cpu::tGFNI)) + features |= HostFeature::GFNI; if (cpu_info.has(Cpu::tBMI2)) { // BMI2 instructions such as pdep and pext have been very slow up until Zen 3. @@ -109,7 +130,7 @@ HostFeature GetHostFeatures() if (cpu_info.has(Cpu::tAMD)) { std::array data{}; cpu_info.getCpuid(1, data.data()); - const u32 family_base = Common::Bits< 8, 11>(data[0]); + const u32 family_base = Common::Bits<8, 11>(data[0]); const u32 family_extended = Common::Bits<20, 27>(data[0]); const u32 family = family_base + family_extended; if (family >= 0x19) @@ -123,7 +144,7 @@ HostFeature GetHostFeatures() return features; } -} // anonymous namespace +} // anonymous namespace BlockOfCode::BlockOfCode(RunCodeCallbacks cb, JitStateInfo jsi, size_t total_code_size, size_t far_code_offset, std::function rcp) : Xbyak::CodeGenerator(total_code_size, nullptr, &s_allocator) @@ -131,8 +152,7 @@ BlockOfCode::BlockOfCode(RunCodeCallbacks cb, JitStateInfo jsi, size_t total_cod , jsi(jsi) , far_code_offset(far_code_offset) , constant_pool(*this, CONSTANT_POOL_SIZE) - , host_features(GetHostFeatures()) -{ + , host_features(GetHostFeatures()) { ASSERT(total_code_size > far_code_offset); EnableWriting(); GenRunCode(rcp); @@ -210,7 +230,7 @@ void BlockOfCode::GenRunCode(std::function rcp) { ABI_PushCalleeSaveRegistersAndAdjustStack(*this, sizeof(StackLayout)); mov(r15, ABI_PARAM1); - mov(rbx, ABI_PARAM2); // save temporarily in non-volatile register + mov(rbx, ABI_PARAM2); // save temporarily in non-volatile register cb.GetTicksRemaining->EmitCall(*this); mov(qword[rsp + ABI_SHADOW_SPACE + offsetof(StackLayout, cycles_to_run)], ABI_RETURN); @@ -368,4 +388,4 @@ void BlockOfCode::EnsurePatchLocationSize(CodePtr begin, size_t size) { nop(size - current_size); } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/block_of_code.h b/src/dynarmic/backend/x64/block_of_code.h index 8a5911f0..b56ba9d3 100644 --- a/src/dynarmic/backend/x64/block_of_code.h +++ b/src/dynarmic/backend/x64/block_of_code.h @@ -73,12 +73,12 @@ public: void LookupBlock(); /// Code emitter: Calls the function - template + template void CallFunction(FunctionPointer fn) { static_assert(std::is_pointer_v && std::is_function_v>, "Supplied type must be a pointer to a function"); - const u64 address = reinterpret_cast(fn); + const u64 address = reinterpret_cast(fn); const u64 distance = address - (getCurr() + 5); if (distance >= 0x0000000080000000ULL && distance < 0xFFFFFFFF80000000ULL) { @@ -91,7 +91,7 @@ public: } /// Code emitter: Calls the lambda. Lambda must not have any captures. - template + template void CallLambda(Lambda l) { CallFunction(Common::FptrCast(l)); } @@ -165,7 +165,7 @@ private: CodePtr near_code_ptr; CodePtr far_code_ptr; - using RunCodeFuncType = void(*)(void*, CodePtr); + using RunCodeFuncType = void (*)(void*, CodePtr); RunCodeFuncType run_code = nullptr; RunCodeFuncType step_code = nullptr; static constexpr size_t MXCSR_ALREADY_EXITED = 1 << 0; @@ -176,4 +176,4 @@ private: const HostFeature host_features; }; -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/block_range_information.cpp b/src/dynarmic/backend/x64/block_range_information.cpp index 66783c6d..7dab84e5 100644 --- a/src/dynarmic/backend/x64/block_range_information.cpp +++ b/src/dynarmic/backend/x64/block_range_information.cpp @@ -3,32 +3,33 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/backend/x64/block_range_information.h" + #include #include #include -#include "dynarmic/backend/x64/block_range_information.h" #include "dynarmic/common/common_types.h" namespace Dynarmic::Backend::X64 { -template +template void BlockRangeInformation::AddRange(boost::icl::discrete_interval range, IR::LocationDescriptor location) { block_ranges.add(std::make_pair(range, std::set{location})); } -template +template void BlockRangeInformation::ClearCache() { block_ranges.clear(); } -template +template tsl::robin_set BlockRangeInformation::InvalidateRanges(const boost::icl::interval_set& ranges) { tsl::robin_set erase_locations; for (auto invalidate_interval : ranges) { auto pair = block_ranges.equal_range(invalidate_interval); for (auto it = pair.first; it != pair.second; ++it) { - for (const auto &descriptor : it->second) { + for (const auto& descriptor : it->second) { erase_locations.insert(descriptor); } } @@ -40,4 +41,4 @@ tsl::robin_set BlockRangeInformation template class BlockRangeInformation; template class BlockRangeInformation; -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/block_range_information.h b/src/dynarmic/backend/x64/block_range_information.h index 377ac82d..a3d43f2b 100644 --- a/src/dynarmic/backend/x64/block_range_information.h +++ b/src/dynarmic/backend/x64/block_range_information.h @@ -15,7 +15,7 @@ namespace Dynarmic::Backend::X64 { -template +template class BlockRangeInformation { public: void AddRange(boost::icl::discrete_interval range, IR::LocationDescriptor location); @@ -26,4 +26,4 @@ private: boost::icl::interval_map> block_ranges; }; -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/callback.cpp b/src/dynarmic/backend/x64/callback.cpp index 9a9232ec..1ecd8304 100644 --- a/src/dynarmic/backend/x64/callback.cpp +++ b/src/dynarmic/backend/x64/callback.cpp @@ -4,6 +4,7 @@ */ #include "dynarmic/backend/x64/callback.h" + #include "dynarmic/backend/x64/block_of_code.h" namespace Dynarmic::Backend::X64 { @@ -37,4 +38,4 @@ void ArgCallback::EmitCallWithReturnPointer(BlockOfCode& code, std::function fn = [](RegList){}) const = 0; + void EmitCall(BlockOfCode& code) const { + EmitCall(code, [](RegList) {}); + } + + virtual void EmitCall(BlockOfCode& code, std::function fn) const = 0; virtual void EmitCallWithReturnPointer(BlockOfCode& code, std::function fn) const = 0; }; class SimpleCallback final : public Callback { public: - template - SimpleCallback(Function fn) : fn(reinterpret_cast(fn)) {} + template + SimpleCallback(Function fn) + : fn(reinterpret_cast(fn)) {} - void EmitCall(BlockOfCode& code, std::function fn = [](RegList){}) const override; + using Callback::EmitCall; + + void EmitCall(BlockOfCode& code, std::function fn) const override; void EmitCallWithReturnPointer(BlockOfCode& code, std::function fn) const override; private: @@ -40,10 +47,13 @@ private: class ArgCallback final : public Callback { public: - template - ArgCallback(Function fn, u64 arg) : fn(reinterpret_cast(fn)), arg(arg) {} + template + ArgCallback(Function fn, u64 arg) + : fn(reinterpret_cast(fn)), arg(arg) {} - void EmitCall(BlockOfCode& code, std::function fn = [](RegList){}) const override; + using Callback::EmitCall; + + void EmitCall(BlockOfCode& code, std::function fn) const override; void EmitCallWithReturnPointer(BlockOfCode& code, std::function fn) const override; private: @@ -51,4 +61,4 @@ private: u64 arg; }; -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/constant_pool.cpp b/src/dynarmic/backend/x64/constant_pool.cpp index a48aa071..2f501523 100644 --- a/src/dynarmic/backend/x64/constant_pool.cpp +++ b/src/dynarmic/backend/x64/constant_pool.cpp @@ -3,15 +3,17 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/backend/x64/constant_pool.h" + #include #include "dynarmic/backend/x64/block_of_code.h" -#include "dynarmic/backend/x64/constant_pool.h" #include "dynarmic/common/assert.h" namespace Dynarmic::Backend::X64 { -ConstantPool::ConstantPool(BlockOfCode& code, size_t size) : code(code), pool_size(size) { +ConstantPool::ConstantPool(BlockOfCode& code, size_t size) + : code(code), pool_size(size) { code.int3(); code.align(align_size); pool_begin = reinterpret_cast(code.AllocateFromCodeSpace(size)); @@ -31,4 +33,4 @@ Xbyak::Address ConstantPool::GetConstant(const Xbyak::AddressFrame& frame, u64 l return frame[code.rip + iter->second]; } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/constant_pool.h b/src/dynarmic/backend/x64/constant_pool.h index 0983bc3a..792918bd 100644 --- a/src/dynarmic/backend/x64/constant_pool.h +++ b/src/dynarmic/backend/x64/constant_pool.h @@ -27,7 +27,7 @@ public: Xbyak::Address GetConstant(const Xbyak::AddressFrame& frame, u64 lower, u64 upper = 0); private: - static constexpr size_t align_size = 16; // bytes + static constexpr size_t align_size = 16; // bytes std::map, void*> constant_info; @@ -37,4 +37,4 @@ private: u8* current_pool_ptr; }; -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/devirtualize.h b/src/dynarmic/backend/x64/devirtualize.h index a2bf9e18..3914a4d7 100644 --- a/src/dynarmic/backend/x64/devirtualize.h +++ b/src/dynarmic/backend/x64/devirtualize.h @@ -19,17 +19,17 @@ namespace Backend::X64 { namespace impl { -template +template struct ThunkBuilder; -template -struct ThunkBuilder { +template +struct ThunkBuilder { static R Thunk(C* this_, Args... args) { return (this_->*mfp)(std::forward(args)...); } }; -} // namespace impl +} // namespace impl template ArgCallback DevirtualizeGeneric(mp::class_type* this_) { @@ -77,5 +77,5 @@ ArgCallback Devirtualize(mp::class_type* this_) { #endif } -} // namespace Backend::X64 -} // namespace Dynarmic +} // namespace Backend::X64 +} // namespace Dynarmic diff --git a/src/dynarmic/backend/x64/emit_x64.cpp b/src/dynarmic/backend/x64/emit_x64.cpp index e4577388..abdda42d 100644 --- a/src/dynarmic/backend/x64/emit_x64.cpp +++ b/src/dynarmic/backend/x64/emit_x64.cpp @@ -3,12 +3,13 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/backend/x64/emit_x64.h" + #include #include #include "dynarmic/backend/x64/block_of_code.h" -#include "dynarmic/backend/x64/emit_x64.h" #include "dynarmic/backend/x64/nzcv_util.h" #include "dynarmic/backend/x64/perf_map.h" #include "dynarmic/backend/x64/stack_layout.h" @@ -29,7 +30,7 @@ namespace Dynarmic::Backend::X64 { using namespace Xbyak::util; EmitContext::EmitContext(RegAlloc& reg_alloc, IR::Block& block) - : reg_alloc(reg_alloc), block(block) {} + : reg_alloc(reg_alloc), block(block) {} size_t EmitContext::GetInstOffset(IR::Inst* inst) const { return static_cast(std::distance(block.begin(), IR::Block::iterator(inst))); @@ -40,7 +41,8 @@ void EmitContext::EraseInstruction(IR::Inst* inst) { inst->ClearArgs(); } -EmitX64::EmitX64(BlockOfCode& code) : code(code) { +EmitX64::EmitX64(BlockOfCode& code) + : code(code) { exception_handler.Register(code); } @@ -73,8 +75,8 @@ void EmitX64::PushRSBHelper(Xbyak::Reg64 loc_desc_reg, Xbyak::Reg64 index_reg, I const auto iter = block_descriptors.find(target); CodePtr target_code_ptr = iter != block_descriptors.end() - ? iter->second.entrypoint - : code.GetReturnFromRunCodeAddress(); + ? iter->second.entrypoint + : code.GetReturnFromRunCodeAddress(); code.mov(index_reg.cvt32(), dword[r15 + code.GetJitStateInfo().offsetof_rsb_ptr]); @@ -126,7 +128,7 @@ void EmitX64::EmitGetLowerFromOp(EmitContext&, IR::Inst*) { void EmitX64::EmitGetNZCVFromOp(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - const int bitsize = [&]{ + const int bitsize = [&] { switch (args[0].GetType()) { case IR::Type::U8: return 8; @@ -195,64 +197,64 @@ Xbyak::Label EmitX64::EmitCond(IR::Cond cond) { // add al, 0x7F restores OF switch (cond) { - case IR::Cond::EQ: //z + case IR::Cond::EQ: //z code.sahf(); code.jz(pass); break; - case IR::Cond::NE: //!z + case IR::Cond::NE: //!z code.sahf(); code.jnz(pass); break; - case IR::Cond::CS: //c + case IR::Cond::CS: //c code.sahf(); code.jc(pass); break; - case IR::Cond::CC: //!c + case IR::Cond::CC: //!c code.sahf(); code.jnc(pass); break; - case IR::Cond::MI: //n + case IR::Cond::MI: //n code.sahf(); code.js(pass); break; - case IR::Cond::PL: //!n + case IR::Cond::PL: //!n code.sahf(); code.jns(pass); break; - case IR::Cond::VS: //v + case IR::Cond::VS: //v code.cmp(al, 0x81); code.jo(pass); break; - case IR::Cond::VC: //!v + case IR::Cond::VC: //!v code.cmp(al, 0x81); code.jno(pass); break; - case IR::Cond::HI: //c & !z + case IR::Cond::HI: //c & !z code.sahf(); code.cmc(); code.ja(pass); break; - case IR::Cond::LS: //!c | z + case IR::Cond::LS: //!c | z code.sahf(); code.cmc(); code.jna(pass); break; - case IR::Cond::GE: // n == v + case IR::Cond::GE: // n == v code.cmp(al, 0x81); code.sahf(); code.jge(pass); break; - case IR::Cond::LT: // n != v + case IR::Cond::LT: // n != v code.cmp(al, 0x81); code.sahf(); code.jl(pass); break; - case IR::Cond::GT: // !z & (n == v) + case IR::Cond::GT: // !z & (n == v) code.cmp(al, 0x81); code.sahf(); code.jg(pass); break; - case IR::Cond::LE: // z | (n != v) + case IR::Cond::LE: // z | (n != v) code.cmp(al, 0x81); code.sahf(); code.jle(pass); @@ -325,7 +327,7 @@ void EmitX64::InvalidateBasicBlocks(const tsl::robin_set code.EnableWriting(); SCOPE_EXIT { code.DisableWriting(); }; - for (const auto &descriptor : locations) { + for (const auto& descriptor : locations) { const auto it = block_descriptors.find(descriptor); if (it == block_descriptors.end()) { continue; @@ -338,4 +340,4 @@ void EmitX64::InvalidateBasicBlocks(const tsl::robin_set } } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/emit_x64.h b/src/dynarmic/backend/x64/emit_x64.h index 12102a24..aea7b5cf 100644 --- a/src/dynarmic/backend/x64/emit_x64.h +++ b/src/dynarmic/backend/x64/emit_x64.h @@ -13,7 +13,6 @@ #include #include - #include #include "dynarmic/backend/x64/exception_handler.h" @@ -26,11 +25,11 @@ namespace Dynarmic::IR { class Block; class Inst; -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR namespace Dynarmic { enum class OptimizationFlag : u32; -} // namespace Dynarmic +} // namespace Dynarmic namespace Dynarmic::Backend::X64 { @@ -41,10 +40,10 @@ using A64FullVectorWidth = std::integral_constant; // Array alias that always sizes itself according to the given type T // relative to the size of a vector register. e.g. T = u32 would result // in a std::array. -template +template using VectorArray = std::array()>; -template +template using HalfVectorArray = std::array() / 2>; struct EmitContext { @@ -128,4 +127,4 @@ protected: tsl::robin_map patch_information; }; -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/emit_x64_aes.cpp b/src/dynarmic/backend/x64/emit_x64_aes.cpp index e3644ee3..be9faa3e 100644 --- a/src/dynarmic/backend/x64/emit_x64_aes.cpp +++ b/src/dynarmic/backend/x64/emit_x64_aes.cpp @@ -73,7 +73,7 @@ void EmitX64::EmitAESEncryptSingleRound(EmitContext& ctx, IR::Inst* inst) { } void EmitX64::EmitAESInverseMixColumns(EmitContext& ctx, IR::Inst* inst) { - auto args = ctx.reg_alloc.GetArgumentInfo(inst); + auto args = ctx.reg_alloc.GetArgumentInfo(inst); if (code.HasHostFeature(HostFeature::AES)) { const Xbyak::Xmm data = ctx.reg_alloc.UseScratchXmm(args[0]); @@ -105,4 +105,4 @@ void EmitX64::EmitAESMixColumns(EmitContext& ctx, IR::Inst* inst) { EmitAESFunction(args, ctx, code, inst, AES::MixColumns); } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/emit_x64_crc32.cpp b/src/dynarmic/backend/x64/emit_x64_crc32.cpp index 781bb91d..e15b5df0 100644 --- a/src/dynarmic/backend/x64/emit_x64_crc32.cpp +++ b/src/dynarmic/backend/x64/emit_x64_crc32.cpp @@ -145,4 +145,4 @@ void EmitX64::EmitCRC32ISO64(EmitContext& ctx, IR::Inst* inst) { EmitCRC32ISO(code, ctx, inst, 64); } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/emit_x64_data_processing.cpp b/src/dynarmic/backend/x64/emit_x64_data_processing.cpp index 9e941f32..78cdd96a 100644 --- a/src/dynarmic/backend/x64/emit_x64_data_processing.cpp +++ b/src/dynarmic/backend/x64/emit_x64_data_processing.cpp @@ -24,7 +24,7 @@ void EmitX64::EmitPack2x32To1x64(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Reg64 hi = ctx.reg_alloc.UseScratchGpr(args[1]); code.shl(hi, 32); - code.mov(lo.cvt32(), lo.cvt32()); // Zero extend to 64-bits + code.mov(lo.cvt32(), lo.cvt32()); // Zero extend to 64-bits code.or_(lo, hi); ctx.reg_alloc.DefineValue(inst, lo); @@ -146,64 +146,64 @@ static void EmitConditionalSelect(BlockOfCode& code, EmitContext& ctx, IR::Inst* // add al, 0x7F restores OF switch (args[0].GetImmediateCond()) { - case IR::Cond::EQ: //z + case IR::Cond::EQ: //z code.sahf(); code.cmovz(else_, then_); break; - case IR::Cond::NE: //!z + case IR::Cond::NE: //!z code.sahf(); code.cmovnz(else_, then_); break; - case IR::Cond::CS: //c + case IR::Cond::CS: //c code.sahf(); code.cmovc(else_, then_); break; - case IR::Cond::CC: //!c + case IR::Cond::CC: //!c code.sahf(); code.cmovnc(else_, then_); break; - case IR::Cond::MI: //n + case IR::Cond::MI: //n code.sahf(); code.cmovs(else_, then_); break; - case IR::Cond::PL: //!n + case IR::Cond::PL: //!n code.sahf(); code.cmovns(else_, then_); break; - case IR::Cond::VS: //v + case IR::Cond::VS: //v code.cmp(nzcv.cvt8(), 0x81); code.cmovo(else_, then_); break; - case IR::Cond::VC: //!v + case IR::Cond::VC: //!v code.cmp(nzcv.cvt8(), 0x81); code.cmovno(else_, then_); break; - case IR::Cond::HI: //c & !z + case IR::Cond::HI: //c & !z code.sahf(); code.cmc(); code.cmova(else_, then_); break; - case IR::Cond::LS: //!c | z + case IR::Cond::LS: //!c | z code.sahf(); code.cmc(); code.cmovna(else_, then_); break; - case IR::Cond::GE: // n == v + case IR::Cond::GE: // n == v code.cmp(nzcv.cvt8(), 0x81); code.sahf(); code.cmovge(else_, then_); break; - case IR::Cond::LT: // n != v + case IR::Cond::LT: // n != v code.cmp(nzcv.cvt8(), 0x81); code.sahf(); code.cmovl(else_, then_); break; - case IR::Cond::GT: // !z & (n == v) + case IR::Cond::GT: // !z & (n == v) code.cmp(nzcv.cvt8(), 0x81); code.sahf(); code.cmovg(else_, then_); break; - case IR::Cond::LE: // z | (n != v) + case IR::Cond::LE: // z | (n != v) code.cmp(nzcv.cvt8(), 0x81); code.sahf(); code.cmovle(else_, then_); @@ -814,7 +814,7 @@ void EmitX64::EmitRotateRightExtended(EmitContext& ctx, IR::Inst* inst) { ctx.reg_alloc.DefineValue(inst, result); } -template +template static void EmitMaskedShift32(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, ShfitFT shift_fn, [[maybe_unused]] BMI2FT bmi2_shift) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto& operand_arg = args[0]; @@ -851,7 +851,7 @@ static void EmitMaskedShift32(BlockOfCode& code, EmitContext& ctx, IR::Inst* ins ctx.reg_alloc.DefineValue(inst, result); } -template +template static void EmitMaskedShift64(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, ShfitFT shift_fn, [[maybe_unused]] BMI2FT bmi2_shift) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto& operand_arg = args[0]; @@ -889,35 +889,43 @@ static void EmitMaskedShift64(BlockOfCode& code, EmitContext& ctx, IR::Inst* ins } void EmitX64::EmitLogicalShiftLeftMasked32(EmitContext& ctx, IR::Inst* inst) { - EmitMaskedShift32(code, ctx, inst, [&](auto result, auto shift) { code.shl(result, shift); }, &Xbyak::CodeGenerator::shlx); + EmitMaskedShift32( + code, ctx, inst, [&](auto result, auto shift) { code.shl(result, shift); }, &Xbyak::CodeGenerator::shlx); } void EmitX64::EmitLogicalShiftLeftMasked64(EmitContext& ctx, IR::Inst* inst) { - EmitMaskedShift64(code, ctx, inst, [&](auto result, auto shift) { code.shl(result, shift); }, &Xbyak::CodeGenerator::shlx); + EmitMaskedShift64( + code, ctx, inst, [&](auto result, auto shift) { code.shl(result, shift); }, &Xbyak::CodeGenerator::shlx); } void EmitX64::EmitLogicalShiftRightMasked32(EmitContext& ctx, IR::Inst* inst) { - EmitMaskedShift32(code, ctx, inst, [&](auto result, auto shift) { code.shr(result, shift); }, &Xbyak::CodeGenerator::shrx); + EmitMaskedShift32( + code, ctx, inst, [&](auto result, auto shift) { code.shr(result, shift); }, &Xbyak::CodeGenerator::shrx); } void EmitX64::EmitLogicalShiftRightMasked64(EmitContext& ctx, IR::Inst* inst) { - EmitMaskedShift64(code, ctx, inst, [&](auto result, auto shift) { code.shr(result, shift); }, &Xbyak::CodeGenerator::shrx); + EmitMaskedShift64( + code, ctx, inst, [&](auto result, auto shift) { code.shr(result, shift); }, &Xbyak::CodeGenerator::shrx); } void EmitX64::EmitArithmeticShiftRightMasked32(EmitContext& ctx, IR::Inst* inst) { - EmitMaskedShift32(code, ctx, inst, [&](auto result, auto shift) { code.sar(result, shift); }, &Xbyak::CodeGenerator::sarx); + EmitMaskedShift32( + code, ctx, inst, [&](auto result, auto shift) { code.sar(result, shift); }, &Xbyak::CodeGenerator::sarx); } void EmitX64::EmitArithmeticShiftRightMasked64(EmitContext& ctx, IR::Inst* inst) { - EmitMaskedShift64(code, ctx, inst, [&](auto result, auto shift) { code.sar(result, shift); }, &Xbyak::CodeGenerator::sarx); + EmitMaskedShift64( + code, ctx, inst, [&](auto result, auto shift) { code.sar(result, shift); }, &Xbyak::CodeGenerator::sarx); } void EmitX64::EmitRotateRightMasked32(EmitContext& ctx, IR::Inst* inst) { - EmitMaskedShift32(code, ctx, inst, [&](auto result, auto shift) { code.ror(result, shift); }, nullptr); + EmitMaskedShift32( + code, ctx, inst, [&](auto result, auto shift) { code.ror(result, shift); }, nullptr); } void EmitX64::EmitRotateRightMasked64(EmitContext& ctx, IR::Inst* inst) { - EmitMaskedShift64(code, ctx, inst, [&](auto result, auto shift) { code.ror(result, shift); }, nullptr); + EmitMaskedShift64( + code, ctx, inst, [&](auto result, auto shift) { code.ror(result, shift); }, nullptr); } static Xbyak::Reg8 DoCarry(RegAlloc& reg_alloc, Argument& carry_in, IR::Inst* carry_out) { @@ -1132,25 +1140,25 @@ void EmitX64::EmitMul64(EmitContext& ctx, IR::Inst* inst) { } void EmitX64::EmitUnsignedMultiplyHigh64(EmitContext& ctx, IR::Inst* inst) { - auto args = ctx.reg_alloc.GetArgumentInfo(inst); + auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ctx.reg_alloc.ScratchGpr(HostLoc::RDX); - ctx.reg_alloc.UseScratch(args[0], HostLoc::RAX); - OpArg op_arg = ctx.reg_alloc.UseOpArg(args[1]); - code.mul(*op_arg); + ctx.reg_alloc.ScratchGpr(HostLoc::RDX); + ctx.reg_alloc.UseScratch(args[0], HostLoc::RAX); + OpArg op_arg = ctx.reg_alloc.UseOpArg(args[1]); + code.mul(*op_arg); - ctx.reg_alloc.DefineValue(inst, rdx); + ctx.reg_alloc.DefineValue(inst, rdx); } void EmitX64::EmitSignedMultiplyHigh64(EmitContext& ctx, IR::Inst* inst) { - auto args = ctx.reg_alloc.GetArgumentInfo(inst); + auto args = ctx.reg_alloc.GetArgumentInfo(inst); - ctx.reg_alloc.ScratchGpr(HostLoc::RDX); - ctx.reg_alloc.UseScratch(args[0], HostLoc::RAX); - OpArg op_arg = ctx.reg_alloc.UseOpArg(args[1]); - code.imul(*op_arg); + ctx.reg_alloc.ScratchGpr(HostLoc::RDX); + ctx.reg_alloc.UseScratch(args[0], HostLoc::RAX); + OpArg op_arg = ctx.reg_alloc.UseOpArg(args[1]); + code.imul(*op_arg); - ctx.reg_alloc.DefineValue(inst, rdx); + ctx.reg_alloc.DefineValue(inst, rdx); } void EmitX64::EmitUnsignedDiv32(EmitContext& ctx, IR::Inst* inst) { @@ -1441,7 +1449,7 @@ void EmitX64::EmitZeroExtendHalfToLong(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitZeroExtendWordToLong(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const Xbyak::Reg64 result = ctx.reg_alloc.UseScratchGpr(args[0]); - code.mov(result.cvt32(), result.cvt32()); // x64 zeros upper 32 bits on a 32-bit move + code.mov(result.cvt32(), result.cvt32()); // x64 zeros upper 32 bits on a 32-bit move ctx.reg_alloc.DefineValue(inst, result); } @@ -1505,27 +1513,27 @@ void EmitX64::EmitCountLeadingZeros32(EmitContext& ctx, IR::Inst* inst) { } void EmitX64::EmitCountLeadingZeros64(EmitContext& ctx, IR::Inst* inst) { - auto args = ctx.reg_alloc.GetArgumentInfo(inst); - if (code.HasHostFeature(HostFeature::LZCNT)) { - const Xbyak::Reg64 source = ctx.reg_alloc.UseGpr(args[0]).cvt64(); - const Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr().cvt64(); + auto args = ctx.reg_alloc.GetArgumentInfo(inst); + if (code.HasHostFeature(HostFeature::LZCNT)) { + const Xbyak::Reg64 source = ctx.reg_alloc.UseGpr(args[0]).cvt64(); + const Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr().cvt64(); - code.lzcnt(result, source); + code.lzcnt(result, source); - ctx.reg_alloc.DefineValue(inst, result); - } else { - const Xbyak::Reg64 source = ctx.reg_alloc.UseScratchGpr(args[0]).cvt64(); - const Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr().cvt64(); + ctx.reg_alloc.DefineValue(inst, result); + } else { + const Xbyak::Reg64 source = ctx.reg_alloc.UseScratchGpr(args[0]).cvt64(); + const Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr().cvt64(); - // The result of a bsr of zero is undefined, but zf is set after it. - code.bsr(result, source); - code.mov(source.cvt32(), 0xFFFFFFFF); - code.cmovz(result.cvt32(), source.cvt32()); - code.neg(result.cvt32()); - code.add(result.cvt32(), 63); + // The result of a bsr of zero is undefined, but zf is set after it. + code.bsr(result, source); + code.mov(source.cvt32(), 0xFFFFFFFF); + code.cmovz(result.cvt32(), source.cvt32()); + code.neg(result.cvt32()); + code.add(result.cvt32(), 63); - ctx.reg_alloc.DefineValue(inst, result); - } + ctx.reg_alloc.DefineValue(inst, result); + } } void EmitX64::EmitMaxSigned32(EmitContext& ctx, IR::Inst* inst) { @@ -1624,4 +1632,4 @@ void EmitX64::EmitMinUnsigned64(EmitContext& ctx, IR::Inst* inst) { ctx.reg_alloc.DefineValue(inst, y); } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/emit_x64_floating_point.cpp b/src/dynarmic/backend/x64/emit_x64_floating_point.cpp index 51482357..9d908a08 100644 --- a/src/dynarmic/backend/x64/emit_x64_floating_point.cpp +++ b/src/dynarmic/backend/x64/emit_x64_floating_point.cpp @@ -51,32 +51,32 @@ constexpr u64 f64_nan = 0x7ff8000000000000u; constexpr u64 f64_non_sign_mask = 0x7fffffffffffffffu; constexpr u64 f64_smallest_normal = 0x0010000000000000u; -constexpr u64 f64_min_s16 = 0xc0e0000000000000u; // -32768 as a double -constexpr u64 f64_max_s16 = 0x40dfffc000000000u; // 32767 as a double -constexpr u64 f64_min_u16 = 0x0000000000000000u; // 0 as a double -constexpr u64 f64_max_u16 = 0x40efffe000000000u; // 65535 as a double -constexpr u64 f64_max_s32 = 0x41dfffffffc00000u; // 2147483647 as a double -constexpr u64 f64_min_u32 = 0x0000000000000000u; // 0 as a double -constexpr u64 f64_max_u32 = 0x41efffffffe00000u; // 4294967295 as a double -constexpr u64 f64_max_s64_lim = 0x43e0000000000000u; // 2^63 as a double (actual maximum unrepresentable) -constexpr u64 f64_min_u64 = 0x0000000000000000u; // 0 as a double -constexpr u64 f64_max_u64_lim = 0x43f0000000000000u; // 2^64 as a double (actual maximum unrepresentable) +constexpr u64 f64_min_s16 = 0xc0e0000000000000u; // -32768 as a double +constexpr u64 f64_max_s16 = 0x40dfffc000000000u; // 32767 as a double +constexpr u64 f64_min_u16 = 0x0000000000000000u; // 0 as a double +constexpr u64 f64_max_u16 = 0x40efffe000000000u; // 65535 as a double +constexpr u64 f64_max_s32 = 0x41dfffffffc00000u; // 2147483647 as a double +constexpr u64 f64_min_u32 = 0x0000000000000000u; // 0 as a double +constexpr u64 f64_max_u32 = 0x41efffffffe00000u; // 4294967295 as a double +constexpr u64 f64_max_s64_lim = 0x43e0000000000000u; // 2^63 as a double (actual maximum unrepresentable) +constexpr u64 f64_min_u64 = 0x0000000000000000u; // 0 as a double +constexpr u64 f64_max_u64_lim = 0x43f0000000000000u; // 2^64 as a double (actual maximum unrepresentable) -#define FCODE(NAME) \ - [&code](auto... args){ \ - if constexpr (fsize == 32) { \ - code.NAME##s(args...); \ - } else { \ - code.NAME##d(args...); \ - } \ +#define FCODE(NAME) \ + [&code](auto... args) { \ + if constexpr (fsize == 32) { \ + code.NAME##s(args...); \ + } else { \ + code.NAME##d(args...); \ + } \ } -#define ICODE(NAME) \ - [&code](auto... args){ \ - if constexpr (fsize == 32) { \ - code.NAME##d(args...); \ - } else { \ - code.NAME##q(args...); \ - } \ +#define ICODE(NAME) \ + [&code](auto... args) { \ + if constexpr (fsize == 32) { \ + code.NAME##d(args...); \ + } else { \ + code.NAME##q(args...); \ + } \ } std::optional ConvertRoundingModeToX64Immediate(FP::RoundingMode rounding_mode) { @@ -117,7 +117,7 @@ void DenormalsAreZero(BlockOfCode& code, EmitContext& ctx, std::initializer_list template void ZeroIfNaN(BlockOfCode& code, Xbyak::Xmm xmm_value, Xbyak::Xmm xmm_scratch) { code.xorps(xmm_scratch, xmm_scratch); - FCODE(cmpords)(xmm_scratch, xmm_value); // true mask when ordered (i.e.: when not an NaN) + FCODE(cmpords)(xmm_scratch, xmm_value); // true mask when ordered (i.e.: when not an NaN) code.pand(xmm_value, xmm_scratch); } @@ -248,7 +248,7 @@ void EmitPostProcessNaNs(BlockOfCode& code, Xbyak::Xmm result, Xbyak::Xmm op1, X code.jmp(end, code.T_NEAR); } -template +template void FPTwoOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); @@ -276,7 +276,7 @@ void FPTwoOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) { ctx.reg_alloc.DefineValue(inst, result); } -template +template void FPThreeOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) { using FPT = mp::unsigned_integer_of_size; @@ -331,7 +331,7 @@ void FPThreeOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) ctx.reg_alloc.DefineValue(inst, result); } -} // anonymous namespace +} // anonymous namespace void EmitX64::EmitFPAbs16(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); @@ -459,7 +459,7 @@ static void EmitFPMinMaxNumeric(BlockOfCode& code, EmitContext& ctx, IR::Inst* i auto args = ctx.reg_alloc.GetArgumentInfo(inst); const Xbyak::Xmm op1 = ctx.reg_alloc.UseScratchXmm(args[0]); - const Xbyak::Xmm op2 = ctx.reg_alloc.UseScratchXmm(args[1]); // Result stored here! + const Xbyak::Xmm op2 = ctx.reg_alloc.UseScratchXmm(args[1]); // Result stored here! Xbyak::Reg tmp = ctx.reg_alloc.ScratchGpr(); tmp.setBit(fsize); @@ -793,7 +793,7 @@ void EmitX64::EmitFPRecipEstimate64(EmitContext& ctx, IR::Inst* inst) { EmitFPRecipEstimate<64>(code, ctx, inst); } -template +template static void EmitFPRecipExponent(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { using FPT = mp::unsigned_integer_of_size; @@ -930,8 +930,7 @@ static void EmitFPRound(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, siz mp::lift_value, mp::lift_value, mp::lift_value, - mp::lift_value - >; + mp::lift_value>; using exact_list = mp::list; static const auto lut = Common::GenerateLookupTableFromList( @@ -947,12 +946,9 @@ static void EmitFPRound(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, siz using InputSize = mp::unsigned_integer_of_size; return FP::FPRoundInt(static_cast(input), fpcr, rounding_mode, exact, fpsr); - } - ) - }; + })}; }, - mp::cartesian_product{} - ); + mp::cartesian_product{}); auto args = ctx.reg_alloc.GetArgumentInfo(inst); ctx.reg_alloc.HostCall(inst, args[0]); @@ -1267,7 +1263,7 @@ void EmitX64::EmitFPSub64(EmitContext& ctx, IR::Inst* inst) { } static Xbyak::Reg64 SetFpscrNzcvFromFlags(BlockOfCode& code, EmitContext& ctx) { - ctx.reg_alloc.ScratchGpr(HostLoc::RCX); // shifting requires use of cl + ctx.reg_alloc.ScratchGpr(HostLoc::RCX); // shifting requires use of cl const Xbyak::Reg64 nzcv = ctx.reg_alloc.ScratchGpr(); // x64 flags ARM flags @@ -1287,7 +1283,7 @@ static Xbyak::Reg64 SetFpscrNzcvFromFlags(BlockOfCode& code, EmitContext& ctx) { code.mov(nzcv, 0x0101'4100'8000'0100); code.sete(cl); - code.rcl(cl, 5); // cl = ZF:CF:0000 + code.rcl(cl, 5); // cl = ZF:CF:0000 code.shr(nzcv, cl); return nzcv; @@ -1467,7 +1463,7 @@ static void EmitFPToFixed(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { if constexpr (fsize != 16) { const auto round_imm = ConvertRoundingModeToX64Immediate(rounding_mode); - if (code.HasHostFeature(HostFeature::SSE41) && round_imm){ + if (code.HasHostFeature(HostFeature::SSE41) && round_imm) { const Xbyak::Xmm src = ctx.reg_alloc.UseScratchXmm(args[0]); const Xbyak::Xmm scratch = ctx.reg_alloc.ScratchXmm(); const Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr().cvt64(); @@ -1512,7 +1508,7 @@ static void EmitFPToFixed(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { code.jmp(end); code.L(below_max); } - code.cvttsd2si(result, src); // 64 bit gpr + code.cvttsd2si(result, src); // 64 bit gpr code.L(end); code.SwitchToFarCode(); @@ -1524,14 +1520,14 @@ static void EmitFPToFixed(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { code.minsd(src, code.MConst(xword, unsigned_ ? f64_max_u32 : f64_max_s32)); if (unsigned_) { code.maxsd(src, code.MConst(xword, f64_min_u32)); - code.cvttsd2si(result, src); // 64 bit gpr + code.cvttsd2si(result, src); // 64 bit gpr } else { code.cvttsd2si(result.cvt32(), src); } } else { code.minsd(src, code.MConst(xword, unsigned_ ? f64_max_u16 : f64_max_s16)); code.maxsd(src, code.MConst(xword, unsigned_ ? f64_min_u16 : f64_min_s16)); - code.cvttsd2si(result, src); // 64 bit gpr + code.cvttsd2si(result, src); // 64 bit gpr } ctx.reg_alloc.DefineValue(inst, result); @@ -1546,8 +1542,7 @@ static void EmitFPToFixed(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { mp::lift_value, mp::lift_value, mp::lift_value, - mp::lift_value - >; + mp::lift_value>; static const auto lut = Common::GenerateLookupTableFromList( [](auto args) { @@ -1561,12 +1556,9 @@ static void EmitFPToFixed(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { using FPT = mp::unsigned_integer_of_size; return FP::FPToFixed(isize, static_cast(input), fbits, unsigned_, fpcr, rounding_mode, fpsr); - } - ) - }; + })}; }, - mp::cartesian_product{} - ); + mp::cartesian_product{}); ctx.reg_alloc.HostCall(inst, args[0]); code.lea(code.ABI_PARAM2, code.ptr[code.r15 + code.GetJitStateInfo().offsetof_fpsr_exc]); @@ -1653,7 +1645,7 @@ void EmitX64::EmitFPFixedS16ToSingle(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32(); const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(); const size_t fbits = args[1].GetImmediateU8(); - [[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); // Not required + [[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); // Not required code.movsx(tmp, from); code.cvtsi2ss(result, tmp); @@ -1673,7 +1665,7 @@ void EmitX64::EmitFPFixedU16ToSingle(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32(); const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(); const size_t fbits = args[1].GetImmediateU8(); - [[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); // Not required + [[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); // Not required code.movzx(tmp, from); code.cvtsi2ss(result, tmp); @@ -1718,14 +1710,14 @@ void EmitX64::EmitFPFixedU32ToSingle(EmitContext& ctx, IR::Inst* inst) { const size_t fbits = args[1].GetImmediateU8(); const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); - const auto op = [&]{ + const auto op = [&] { if (code.HasHostFeature(HostFeature::AVX512F)) { const Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(args[0]); code.vcvtusi2ss(result, result, from.cvt32()); } else { // We are using a 64-bit GPR register to ensure we don't end up treating the input as signed const Xbyak::Reg64 from = ctx.reg_alloc.UseScratchGpr(args[0]); - code.mov(from.cvt32(), from.cvt32()); // TODO: Verify if this is necessary + code.mov(from.cvt32(), from.cvt32()); // TODO: Verify if this is necessary code.cvtsi2ss(result, from); } }; @@ -1754,7 +1746,7 @@ void EmitX64::EmitFPFixedS16ToDouble(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32(); const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(); const size_t fbits = args[1].GetImmediateU8(); - [[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); // Not required + [[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); // Not required code.movsx(tmp, from); code.cvtsi2sd(result, tmp); @@ -1774,7 +1766,7 @@ void EmitX64::EmitFPFixedU16ToDouble(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32(); const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(); const size_t fbits = args[1].GetImmediateU8(); - [[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); // Not required + [[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); // Not required code.movzx(tmp, from); code.cvtsi2sd(result, tmp); @@ -1793,7 +1785,7 @@ void EmitX64::EmitFPFixedS32ToDouble(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Reg32 from = ctx.reg_alloc.UseGpr(args[0]).cvt32(); const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(); const size_t fbits = args[1].GetImmediateU8(); - [[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); // Not required + [[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); // Not required code.cvtsi2sd(result, from); @@ -1810,7 +1802,7 @@ void EmitX64::EmitFPFixedU32ToDouble(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Xmm to = ctx.reg_alloc.ScratchXmm(); const size_t fbits = args[1].GetImmediateU8(); - [[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); // Not required + [[maybe_unused]] const FP::RoundingMode rounding_mode = static_cast(args[2].GetImmediateU8()); // Not required if (code.HasHostFeature(HostFeature::AVX512F)) { const Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(args[0]); @@ -1818,7 +1810,7 @@ void EmitX64::EmitFPFixedU32ToDouble(EmitContext& ctx, IR::Inst* inst) { } else { // We are using a 64-bit GPR register to ensure we don't end up treating the input as signed const Xbyak::Reg64 from = ctx.reg_alloc.UseScratchGpr(args[0]); - code.mov(from.cvt32(), from.cvt32()); // TODO: Verify if this is necessary + code.mov(from.cvt32(), from.cvt32()); // TODO: Verify if this is necessary code.cvtsi2sd(to, from); } @@ -1943,4 +1935,4 @@ void EmitX64::EmitFPFixedU64ToSingle(EmitContext& ctx, IR::Inst* inst) { ctx.reg_alloc.DefineValue(inst, result); } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/emit_x64_packed.cpp b/src/dynarmic/backend/x64/emit_x64_packed.cpp index bda2ab40..3354df32 100644 --- a/src/dynarmic/backend/x64/emit_x64_packed.cpp +++ b/src/dynarmic/backend/x64/emit_x64_packed.cpp @@ -98,7 +98,7 @@ void EmitX64::EmitPackedAddU16(EmitContext& ctx, IR::Inst* inst) { code.movdqa(tmp_b, xmm_b); code.paddw(tmp_a, code.MConst(xword, 0x80008000)); code.paddw(tmp_b, code.MConst(xword, 0x80008000)); - code.pcmpgtw(tmp_b, tmp_a); // *Signed* comparison! + code.pcmpgtw(tmp_b, tmp_a); // *Signed* comparison! ctx.reg_alloc.DefineValue(ge_inst, tmp_b); ctx.EraseInstruction(ge_inst); @@ -205,7 +205,7 @@ void EmitX64::EmitPackedSubU16(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Xmm xmm_ge = ctx.reg_alloc.ScratchXmm(); code.movdqa(xmm_ge, xmm_a); - code.pmaxuw(xmm_ge, xmm_b); // Requires SSE 4.1 + code.pmaxuw(xmm_ge, xmm_b); // Requires SSE 4.1 code.pcmpeqw(xmm_ge, xmm_a); code.psubw(xmm_a, xmm_b); @@ -226,7 +226,7 @@ void EmitX64::EmitPackedSubU16(EmitContext& ctx, IR::Inst* inst) { code.paddw(xmm_a, code.MConst(xword, 0x80008000)); code.paddw(xmm_b, code.MConst(xword, 0x80008000)); code.movdqa(xmm_ge, xmm_b); - code.pcmpgtw(xmm_ge, xmm_a); // *Signed* comparison! + code.pcmpgtw(xmm_ge, xmm_a); // *Signed* comparison! code.pxor(xmm_ge, ones); code.psubw(xmm_a, xmm_b); @@ -709,4 +709,4 @@ void EmitX64::EmitPackedSelect(EmitContext& ctx, IR::Inst* inst) { } } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/emit_x64_saturation.cpp b/src/dynarmic/backend/x64/emit_x64_saturation.cpp index a458b4be..a4cd2bec 100644 --- a/src/dynarmic/backend/x64/emit_x64_saturation.cpp +++ b/src/dynarmic/backend/x64/emit_x64_saturation.cpp @@ -106,7 +106,7 @@ void EmitUnsignedSaturatedOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst ctx.reg_alloc.DefineValue(inst, addend); } -} // anonymous namespace +} // anonymous namespace void EmitX64::EmitSignedSaturatedAdd8(EmitContext& ctx, IR::Inst* inst) { EmitSignedSaturatedOp(code, ctx, inst); @@ -312,4 +312,4 @@ void EmitX64::EmitUnsignedSaturation(EmitContext& ctx, IR::Inst* inst) { ctx.reg_alloc.DefineValue(inst, result); } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/emit_x64_sm4.cpp b/src/dynarmic/backend/x64/emit_x64_sm4.cpp index 0f105689..bee51a80 100644 --- a/src/dynarmic/backend/x64/emit_x64_sm4.cpp +++ b/src/dynarmic/backend/x64/emit_x64_sm4.cpp @@ -17,4 +17,4 @@ void EmitX64::EmitSM4AccessSubstitutionBox(EmitContext& ctx, IR::Inst* inst) { code.CallFunction(&Common::Crypto::SM4::AccessSubstitutionBox); } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/emit_x64_vector.cpp b/src/dynarmic/backend/x64/emit_x64_vector.cpp index 644d7f66..7e7346b3 100644 --- a/src/dynarmic/backend/x64/emit_x64_vector.cpp +++ b/src/dynarmic/backend/x64/emit_x64_vector.cpp @@ -25,7 +25,7 @@ namespace Dynarmic::Backend::X64 { using namespace Xbyak::util; -template +template static void EmitVectorOperation(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); @@ -37,7 +37,7 @@ static void EmitVectorOperation(BlockOfCode& code, EmitContext& ctx, IR::Inst* i ctx.reg_alloc.DefineValue(inst, xmm_a); } -template +template static void EmitAVXVectorOperation(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); @@ -49,7 +49,7 @@ static void EmitAVXVectorOperation(BlockOfCode& code, EmitContext& ctx, IR::Inst ctx.reg_alloc.DefineValue(inst, xmm_a); } -template +template static void EmitOneArgumentFallback(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Lambda lambda) { const auto fn = static_cast*>(lambda); constexpr u32 stack_space = 2 * 16; @@ -72,7 +72,7 @@ static void EmitOneArgumentFallback(BlockOfCode& code, EmitContext& ctx, IR::Ins ctx.reg_alloc.DefineValue(inst, result); } -template +template static void EmitOneArgumentFallbackWithSaturation(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Lambda lambda) { const auto fn = static_cast*>(lambda); constexpr u32 stack_space = 2 * 16; @@ -97,7 +97,7 @@ static void EmitOneArgumentFallbackWithSaturation(BlockOfCode& code, EmitContext ctx.reg_alloc.DefineValue(inst, result); } -template +template static void EmitTwoArgumentFallbackWithSaturation(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Lambda lambda) { const auto fn = static_cast*>(lambda); constexpr u32 stack_space = 3 * 16; @@ -125,7 +125,7 @@ static void EmitTwoArgumentFallbackWithSaturation(BlockOfCode& code, EmitContext ctx.reg_alloc.DefineValue(inst, result); } -template +template static void EmitTwoArgumentFallback(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Lambda lambda) { const auto fn = static_cast*>(lambda); constexpr u32 stack_space = 3 * 16; @@ -168,7 +168,7 @@ void EmitX64::EmitVectorGetElement8(EmitContext& ctx, IR::Inst* inst) { if (index % 2 == 1) { code.shr(dest, 8); } else { - code.and_(dest, 0xFF); // TODO: Remove when zext handling is corrected + code.and_(dest, 0xFF); // TODO: Remove when zext handling is corrected } } @@ -441,8 +441,8 @@ void EmitX64::EmitVectorAnd(EmitContext& ctx, IR::Inst* inst) { static void ArithmeticShiftRightByte(EmitContext& ctx, BlockOfCode& code, const Xbyak::Xmm& result, u8 shift_amount) { if (code.HasHostFeature(HostFeature::AVX512VL | HostFeature::GFNI)) { const u64 shift_matrix = shift_amount < 8 - ? (0x0102040810204080 << (shift_amount * 8)) | (0x8080808080808080 >> (64 - shift_amount * 8)) - : 0x8080808080808080; + ? (0x0102040810204080 << (shift_amount * 8)) | (0x8080808080808080 >> (64 - shift_amount * 8)) + : 0x8080808080808080; code.vgf2p8affineqb(result, result, code.MConst(xword_b, shift_matrix), 0); return; } @@ -513,7 +513,7 @@ void EmitX64::EmitVectorArithmeticShiftRight64(EmitContext& ctx, IR::Inst* inst) ctx.reg_alloc.DefineValue(inst, result); } -template +template static constexpr T VShift(T x, T y) { const s8 shift_amount = static_cast(static_cast(y)); const s64 bit_size = static_cast(Common::BitSize()); @@ -740,7 +740,7 @@ void EmitX64::EmitVectorBroadcast64(EmitContext& ctx, IR::Inst* inst) { ctx.reg_alloc.DefineValue(inst, a); } -template +template static void EmitVectorCountLeadingZeros(VectorArray& result, const VectorArray& data) { for (size_t i = 0; i < result.size(); i++) { T element = data[i]; @@ -1875,7 +1875,7 @@ void EmitX64::EmitVectorMinS64(EmitContext& ctx, IR::Inst* inst) { return; } - EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray& result, const VectorArray& a, const VectorArray& b){ + EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray& result, const VectorArray& a, const VectorArray& b) { std::transform(a.begin(), a.end(), b.begin(), result.begin(), [](auto x, auto y) { return std::min(x, y); }); }); } @@ -1955,7 +1955,7 @@ void EmitX64::EmitVectorMinU64(EmitContext& ctx, IR::Inst* inst) { return; } - EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray& result, const VectorArray& a, const VectorArray& b){ + EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray& result, const VectorArray& a, const VectorArray& b) { std::transform(a.begin(), a.end(), b.begin(), result.begin(), [](auto x, auto y) { return std::min(x, y); }); }); } @@ -2184,7 +2184,7 @@ void EmitX64::EmitVectorPairedAddLower16(EmitContext& ctx, IR::Inst* inst) { code.paddd(xmm_a, tmp); code.pxor(tmp, tmp); code.psrad(xmm_a, 16); - code.packssdw(xmm_a, tmp); // Note: packusdw is SSE4.1, hence the arithmetic shift above. + code.packssdw(xmm_a, tmp); // Note: packusdw is SSE4.1, hence the arithmetic shift above. } ctx.reg_alloc.DefineValue(inst, xmm_a); @@ -2413,7 +2413,7 @@ void EmitX64::EmitVectorPairedAddUnsignedWiden32(EmitContext& ctx, IR::Inst* ins ctx.reg_alloc.DefineValue(inst, a); } -template +template static void PairedOperation(VectorArray& result, const VectorArray& x, const VectorArray& y, Function fn) { const size_t range = x.size() / 2; @@ -2426,12 +2426,12 @@ static void PairedOperation(VectorArray& result, const VectorArray& x, con } } -template +template static void PairedMax(VectorArray& result, const VectorArray& x, const VectorArray& y) { PairedOperation(result, x, y, [](auto a, auto b) { return std::max(a, b); }); } -template +template static void PairedMin(VectorArray& result, const VectorArray& x, const VectorArray& y) { PairedOperation(result, x, y, [](auto a, auto b) { return std::min(a, b); }); } @@ -2606,7 +2606,7 @@ void EmitX64::EmitVectorPairedMinU32(EmitContext& ctx, IR::Inst* inst) { } } -template +template static D PolynomialMultiply(T lhs, T rhs) { constexpr size_t bit_size = Common::BitSize(); const std::bitset operand(lhs); @@ -2762,8 +2762,8 @@ void EmitX64::EmitVectorPopulationCount(EmitContext& ctx, IR::Inst* inst) { code.movdqa(high_a, low_a); code.psrlw(high_a, 4); code.movdqa(tmp1, code.MConst(xword, 0x0F0F0F0F0F0F0F0F, 0x0F0F0F0F0F0F0F0F)); - code.pand(high_a, tmp1); // High nibbles - code.pand(low_a, tmp1); // Low nibbles + code.pand(high_a, tmp1); // High nibbles + code.pand(low_a, tmp1); // Low nibbles code.movdqa(tmp1, code.MConst(xword, 0x0302020102010100, 0x0403030203020201)); code.movdqa(tmp2, tmp1); @@ -2930,7 +2930,7 @@ void EmitX64::EmitVectorRoundingHalvingAddU32(EmitContext& ctx, IR::Inst* inst) EmitVectorRoundingHalvingAddUnsigned(32, ctx, inst, code); } -template +template static void RoundingShiftLeft(VectorArray& out, const VectorArray& lhs, const VectorArray& rhs) { using signed_type = std::make_signed_t; using unsigned_type = std::make_unsigned_t; @@ -2947,8 +2947,7 @@ static void RoundingShiftLeft(VectorArray& out, const VectorArray& lhs, co out[i] = static_cast(static_cast(lhs[i]) << extended_shift); } } else { - if ((std::is_unsigned_v && extended_shift < -bit_size) || - (std::is_signed_v && extended_shift <= -bit_size)) { + if ((std::is_unsigned_v && extended_shift < -bit_size) || (std::is_signed_v && extended_shift <= -bit_size)) { out[i] = 0; } else { const s64 shift_value = -extended_shift - 1; @@ -3350,7 +3349,6 @@ static void EmitVectorSignedSaturatedAbs(size_t esize, BlockOfCode& code, EmitCo ctx.reg_alloc.DefineValue(inst, data); } - void EmitX64::EmitVectorSignedSaturatedAbs8(EmitContext& ctx, IR::Inst* inst) { EmitVectorSignedSaturatedAbs(8, code, ctx, inst); } @@ -3869,7 +3867,7 @@ static void EmitVectorSignedSaturatedNarrowToUnsigned(size_t original_esize, Blo break; case 32: ASSERT(code.HasHostFeature(HostFeature::SSE41)); - code.packusdw(dest, dest); // SSE4.1 + code.packusdw(dest, dest); // SSE4.1 code.movdqa(reconstructed, dest); code.punpcklwd(reconstructed, zero); break; @@ -4024,10 +4022,10 @@ void EmitX64::EmitVectorSignedSaturatedNeg64(EmitContext& ctx, IR::Inst* inst) { // MSVC requires the capture within the saturate lambda, but it's // determined to be unnecessary via clang and GCC. #ifdef __clang__ -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wunused-lambda-capture" +# pragma clang diagnostic push +# pragma clang diagnostic ignored "-Wunused-lambda-capture" #endif -template > +template> static bool VectorSignedSaturatedShiftLeft(VectorArray& dst, const VectorArray& data, const VectorArray& shift_values) { static_assert(std::is_signed_v, "T must be signed."); @@ -4066,7 +4064,7 @@ static bool VectorSignedSaturatedShiftLeft(VectorArray& dst, const VectorArra return qc_flag; } #ifdef __clang__ -#pragma clang diagnostic pop +# pragma clang diagnostic pop #endif void EmitX64::EmitVectorSignedSaturatedShiftLeft8(EmitContext& ctx, IR::Inst* inst) { @@ -4085,7 +4083,7 @@ void EmitX64::EmitVectorSignedSaturatedShiftLeft64(EmitContext& ctx, IR::Inst* i EmitTwoArgumentFallbackWithSaturation(code, ctx, inst, VectorSignedSaturatedShiftLeft); } -template > +template> static bool VectorSignedSaturatedShiftLeftUnsigned(VectorArray& dst, const VectorArray& data, const VectorArray& shift_values) { static_assert(std::is_signed_v, "T must be signed."); @@ -4166,7 +4164,7 @@ void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst()); - const size_t table_size = std::count_if(table.begin(), table.end(), [](const auto& elem){ return !elem.IsVoid(); }); + const size_t table_size = std::count_if(table.begin(), table.end(), [](const auto& elem) { return !elem.IsVoid(); }); const bool is_defaults_zero = inst->GetArg(0).IsZero(); // TODO: AVX512VL implementation when available (VPERMB / VPERMI2B / VPERMT2B) @@ -4318,8 +4316,7 @@ void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) { result[i] = table[index][elem]; } } - } - ); + }); code.movq(result, qword[rsp + ABI_SHADOW_SPACE + 4 * 8]); ctx.reg_alloc.ReleaseStackSpace(stack_space + ABI_SHADOW_SPACE); @@ -4333,7 +4330,7 @@ void EmitX64::EmitVectorTableLookup128(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto table = ctx.reg_alloc.GetArgumentInfo(inst->GetArg(1).GetInst()); - const size_t table_size = std::count_if(table.begin(), table.end(), [](const auto& elem){ return !elem.IsVoid(); }); + const size_t table_size = std::count_if(table.begin(), table.end(), [](const auto& elem) { return !elem.IsVoid(); }); const bool is_defaults_zero = !inst->GetArg(0).IsImmediate() && inst->GetArg(0).GetInst()->GetOpcode() == IR::Opcode::ZeroVector; // TODO: AVX512VL implementation when available (VPERMB / VPERMI2B / VPERMT2B) @@ -4448,8 +4445,7 @@ void EmitX64::EmitVectorTableLookup128(EmitContext& ctx, IR::Inst* inst) { result[i] = table[index][elem]; } } - } - ); + }); code.movaps(result, xword[rsp + ABI_SHADOW_SPACE + (table_size + 0) * 16]); ctx.reg_alloc.ReleaseStackSpace(stack_space + ABI_SHADOW_SPACE); @@ -4732,7 +4728,7 @@ void EmitX64::EmitVectorUnsignedRecipSqrtEstimate(EmitContext& ctx, IR::Inst* in // Simple generic case for 8, 16, and 32-bit values. 64-bit values // will need to be special-cased as we can't simply use a larger integral size. -template > +template> static bool EmitVectorUnsignedSaturatedAccumulateSigned(VectorArray& result, const VectorArray& lhs, const VectorArray& rhs) { static_assert(std::is_signed_v, "T must be signed."); static_assert(Common::BitSize() < 64, "T must be less than 64 bits in size."); @@ -4833,7 +4829,7 @@ void EmitX64::EmitVectorUnsignedSaturatedNarrow64(EmitContext& ctx, IR::Inst* in }); } -template > +template> static bool VectorUnsignedSaturatedShiftLeft(VectorArray& dst, const VectorArray& data, const VectorArray& shift_values) { static_assert(std::is_unsigned_v, "T must be an unsigned type."); @@ -4937,7 +4933,7 @@ void EmitX64::EmitVectorZeroUpper(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]); - code.movq(a, a); // TODO: !IsLastUse + code.movq(a, a); // TODO: !IsLastUse ctx.reg_alloc.DefineValue(inst, a); } @@ -4948,4 +4944,4 @@ void EmitX64::EmitZeroVector(EmitContext& ctx, IR::Inst* inst) { ctx.reg_alloc.DefineValue(inst, a); } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp b/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp index 64075fd1..e4f77d6d 100644 --- a/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp +++ b/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp @@ -36,21 +36,21 @@ using namespace Xbyak::util; namespace { -#define FCODE(NAME) \ - [&code](auto... args){ \ - if constexpr (fsize == 32) { \ - code.NAME##s(args...); \ - } else { \ - code.NAME##d(args...); \ - } \ +#define FCODE(NAME) \ + [&code](auto... args) { \ + if constexpr (fsize == 32) { \ + code.NAME##s(args...); \ + } else { \ + code.NAME##d(args...); \ + } \ } -#define ICODE(NAME) \ - [&code](auto... args){ \ - if constexpr (fsize == 32) { \ - code.NAME##d(args...); \ - } else { \ - code.NAME##q(args...); \ - } \ +#define ICODE(NAME) \ + [&code](auto... args) { \ + if constexpr (fsize == 32) { \ + code.NAME##d(args...); \ + } else { \ + code.NAME##q(args...); \ + } \ } template @@ -71,7 +71,7 @@ struct NaNHandler { public: using FPT = mp::unsigned_integer_of_size; - using function_type = void(*)(std::array, narg>&, FP::FPCR); + using function_type = void (*)(std::array, narg>&, FP::FPCR); static function_type GetDefault() { return GetDefaultImpl(std::make_index_sequence{}); @@ -294,13 +294,13 @@ void EmitTwoOpVectorOperation(BlockOfCode& code, EmitContext& ctx, IR::Inst* ins if constexpr (std::is_member_function_pointer_v) { result = ctx.reg_alloc.UseScratchXmm(args[0]); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { (code.*fn)(result); }); } else { const Xbyak::Xmm xmm_a = ctx.reg_alloc.UseXmm(args[0]); result = ctx.reg_alloc.ScratchXmm(); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { fn(result, xmm_a); }); } @@ -337,7 +337,8 @@ void EmitTwoOpVectorOperation(BlockOfCode& code, EmitContext& ctx, IR::Inst* ins } enum CheckInputNaN { - Yes, No, + Yes, + No, }; template class Indexer, typename Function> @@ -352,11 +353,11 @@ void EmitThreeOpVectorOperation(BlockOfCode& code, EmitContext& ctx, IR::Inst* i const Xbyak::Xmm xmm_b = ctx.reg_alloc.UseXmm(args[1]); if constexpr (std::is_member_function_pointer_v) { - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { (code.*fn)(xmm_a, xmm_b); }); } else { - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { fn(xmm_a, xmm_b); }); } @@ -549,7 +550,7 @@ void EmitFourOpFallback(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Lam ctx.reg_alloc.DefineValue(inst, result); } -} // anonymous namespace +} // anonymous namespace void EmitX64::EmitFPVectorAbs16(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); @@ -614,7 +615,7 @@ void EmitX64::EmitFPVectorEqual32(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]); const Xbyak::Xmm b = ctx.FPCR(fpcr_controlled).FZ() ? ctx.reg_alloc.UseScratchXmm(args[1]) : ctx.reg_alloc.UseXmm(args[1]); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { DenormalsAreZero<32>(code, ctx.FPCR(fpcr_controlled), {a, b}, xmm0); code.cmpeqps(a, b); }); @@ -628,7 +629,7 @@ void EmitX64::EmitFPVectorEqual64(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]); const Xbyak::Xmm b = ctx.FPCR(fpcr_controlled).FZ() ? ctx.reg_alloc.UseScratchXmm(args[1]) : ctx.reg_alloc.UseXmm(args[1]); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { DenormalsAreZero<64>(code, ctx.FPCR(fpcr_controlled), {a, b}, xmm0); code.cmpeqpd(a, b); }); @@ -644,7 +645,7 @@ void EmitX64::EmitFPVectorFromSignedFixed32(EmitContext& ctx, IR::Inst* inst) { const bool fpcr_controlled = args[3].GetImmediateU1(); ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode()); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { code.cvtdq2ps(xmm, xmm); if (fbits != 0) { code.mulps(xmm, GetVectorOf<32>(code, static_cast(127 - fbits) << 23)); @@ -662,7 +663,7 @@ void EmitX64::EmitFPVectorFromSignedFixed64(EmitContext& ctx, IR::Inst* inst) { const bool fpcr_controlled = args[3].GetImmediateU1(); ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode()); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { if (code.HasHostFeature(HostFeature::AVX512_OrthoFloat)) { code.vcvtqq2pd(xmm, xmm); } else if (code.HasHostFeature(HostFeature::SSE41)) { @@ -713,7 +714,7 @@ void EmitX64::EmitFPVectorFromUnsignedFixed32(EmitContext& ctx, IR::Inst* inst) const bool fpcr_controlled = args[3].GetImmediateU1(); ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode()); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { if (code.HasHostFeature(HostFeature::AVX512_Ortho)) { code.vcvtudq2ps(xmm, xmm); } else { @@ -763,7 +764,7 @@ void EmitX64::EmitFPVectorFromUnsignedFixed64(EmitContext& ctx, IR::Inst* inst) const bool fpcr_controlled = args[3].GetImmediateU1(); ASSERT(rounding_mode == ctx.FPCR(fpcr_controlled).RMode()); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { if (code.HasHostFeature(HostFeature::AVX512_OrthoFloat)) { code.vcvtuqq2pd(xmm, xmm); } else { @@ -828,7 +829,7 @@ void EmitX64::EmitFPVectorGreater32(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Xmm a = ctx.FPCR(fpcr_controlled).FZ() ? ctx.reg_alloc.UseScratchXmm(args[0]) : ctx.reg_alloc.UseXmm(args[0]); const Xbyak::Xmm b = ctx.reg_alloc.UseScratchXmm(args[1]); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { DenormalsAreZero<32>(code, ctx.FPCR(fpcr_controlled), {a, b}, xmm0); code.cmpltps(b, a); }); @@ -842,7 +843,7 @@ void EmitX64::EmitFPVectorGreater64(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Xmm a = ctx.FPCR(fpcr_controlled).FZ() ? ctx.reg_alloc.UseScratchXmm(args[0]) : ctx.reg_alloc.UseXmm(args[0]); const Xbyak::Xmm b = ctx.reg_alloc.UseScratchXmm(args[1]); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { DenormalsAreZero<64>(code, ctx.FPCR(fpcr_controlled), {a, b}, xmm0); code.cmpltpd(b, a); }); @@ -856,7 +857,7 @@ void EmitX64::EmitFPVectorGreaterEqual32(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Xmm a = ctx.FPCR(fpcr_controlled).FZ() ? ctx.reg_alloc.UseScratchXmm(args[0]) : ctx.reg_alloc.UseXmm(args[0]); const Xbyak::Xmm b = ctx.reg_alloc.UseScratchXmm(args[1]); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { DenormalsAreZero<32>(code, ctx.FPCR(fpcr_controlled), {a, b}, xmm0); code.cmpleps(b, a); }); @@ -870,7 +871,7 @@ void EmitX64::EmitFPVectorGreaterEqual64(EmitContext& ctx, IR::Inst* inst) { const Xbyak::Xmm a = ctx.FPCR(fpcr_controlled).FZ() ? ctx.reg_alloc.UseScratchXmm(args[0]) : ctx.reg_alloc.UseXmm(args[0]); const Xbyak::Xmm b = ctx.reg_alloc.UseScratchXmm(args[1]); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { DenormalsAreZero<64>(code, ctx.FPCR(fpcr_controlled), {a, b}, xmm0); code.cmplepd(b, a); }); @@ -891,7 +892,7 @@ static void EmitFPVectorMinMax(BlockOfCode& code, EmitContext& ctx, IR::Inst* in const Xbyak::Xmm eq = ctx.reg_alloc.ScratchXmm(); const Xbyak::Xmm nan_mask = ctx.reg_alloc.ScratchXmm(); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { DenormalsAreZero(code, ctx.FPCR(fpcr_controlled), {result, xmm_b}, mask); if (code.HasHostFeature(HostFeature::AVX)) { @@ -936,49 +937,51 @@ static void EmitFPVectorMinMax(BlockOfCode& code, EmitContext& ctx, IR::Inst* in return; } - EmitThreeOpVectorOperation(code, ctx, inst, [&](const Xbyak::Xmm& result, Xbyak::Xmm xmm_b){ - const Xbyak::Xmm mask = xmm0; - const Xbyak::Xmm eq = ctx.reg_alloc.ScratchXmm(); + EmitThreeOpVectorOperation( + code, ctx, inst, [&](const Xbyak::Xmm& result, Xbyak::Xmm xmm_b) { + const Xbyak::Xmm mask = xmm0; + const Xbyak::Xmm eq = ctx.reg_alloc.ScratchXmm(); - if (ctx.FPCR(fpcr_controlled).FZ()) { - const Xbyak::Xmm prev_xmm_b = xmm_b; - xmm_b = ctx.reg_alloc.ScratchXmm(); - code.movaps(xmm_b, prev_xmm_b); - DenormalsAreZero(code, ctx.FPCR(fpcr_controlled), {result, xmm_b}, mask); - } - - // What we are doing here is handling the case when the inputs are differently signed zeros. - // x86-64 treats differently signed zeros as equal while ARM does not. - // Thus if we AND together things that x86-64 thinks are equal we'll get the positive zero. - - if (code.HasHostFeature(HostFeature::AVX)) { - FCODE(vcmpeqp)(mask, result, xmm_b); - if constexpr (is_max) { - FCODE(vandp)(eq, result, xmm_b); - FCODE(vmaxp)(result, result, xmm_b); - } else { - FCODE(vorp)(eq, result, xmm_b); - FCODE(vminp)(result, result, xmm_b); - } - FCODE(blendvp)(result, eq); - } else { - code.movaps(mask, result); - code.movaps(eq, result); - FCODE(cmpneqp)(mask, xmm_b); - - if constexpr (is_max) { - code.andps(eq, xmm_b); - FCODE(maxp)(result, xmm_b); - } else { - code.orps(eq, xmm_b); - FCODE(minp)(result, xmm_b); + if (ctx.FPCR(fpcr_controlled).FZ()) { + const Xbyak::Xmm prev_xmm_b = xmm_b; + xmm_b = ctx.reg_alloc.ScratchXmm(); + code.movaps(xmm_b, prev_xmm_b); + DenormalsAreZero(code, ctx.FPCR(fpcr_controlled), {result, xmm_b}, mask); } - code.andps(result, mask); - code.andnps(mask, eq); - code.orps(result, mask); - } - }, CheckInputNaN::Yes); + // What we are doing here is handling the case when the inputs are differently signed zeros. + // x86-64 treats differently signed zeros as equal while ARM does not. + // Thus if we AND together things that x86-64 thinks are equal we'll get the positive zero. + + if (code.HasHostFeature(HostFeature::AVX)) { + FCODE(vcmpeqp)(mask, result, xmm_b); + if constexpr (is_max) { + FCODE(vandp)(eq, result, xmm_b); + FCODE(vmaxp)(result, result, xmm_b); + } else { + FCODE(vorp)(eq, result, xmm_b); + FCODE(vminp)(result, result, xmm_b); + } + FCODE(blendvp)(result, eq); + } else { + code.movaps(mask, result); + code.movaps(eq, result); + FCODE(cmpneqp)(mask, xmm_b); + + if constexpr (is_max) { + code.andps(eq, xmm_b); + FCODE(maxp)(result, xmm_b); + } else { + code.orps(eq, xmm_b); + FCODE(minp)(result, xmm_b); + } + + code.andps(result, mask); + code.andnps(mask, eq); + code.orps(result, mask); + } + }, + CheckInputNaN::Yes); } void EmitX64::EmitFPVectorMax32(EmitContext& ctx, IR::Inst* inst) { @@ -1024,7 +1027,7 @@ void EmitFPVectorMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { const Xbyak::Xmm xmm_b = ctx.reg_alloc.UseXmm(args[1]); const Xbyak::Xmm xmm_c = ctx.reg_alloc.UseXmm(args[2]); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { FCODE(vfmadd231p)(result, xmm_b, xmm_c); }); @@ -1044,7 +1047,7 @@ void EmitFPVectorMulAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { Xbyak::Label end, fallback; - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { code.movaps(result, xmm_a); FCODE(vfmadd231p)(result, xmm_b, xmm_c); @@ -1113,7 +1116,7 @@ static void EmitFPVectorMulX(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm(); const Xbyak::Xmm twos = ctx.reg_alloc.ScratchXmm(); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { FCODE(vcmpunordp)(xmm0, result, operand); FCODE(vxorp)(twos, result, operand); FCODE(mulp)(result, operand); @@ -1151,8 +1154,7 @@ static void EmitFPVectorMulX(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst result[elementi] = sign | FP::FPValue(); } } - } - ); + }); HandleNaNs(code, ctx, fpcr_controlled, {result, xmm_a, xmm_b}, nan_mask, nan_handler); @@ -1287,7 +1289,7 @@ static void EmitRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in const Xbyak::Xmm operand1 = ctx.reg_alloc.UseXmm(args[0]); const Xbyak::Xmm operand2 = ctx.reg_alloc.UseXmm(args[1]); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { code.movaps(result, GetVectorOf(code)); FCODE(vfnmadd231p)(result, operand1, operand2); }); @@ -1307,7 +1309,7 @@ static void EmitRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in Xbyak::Label end, fallback; - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { code.movaps(result, GetVectorOf(code)); FCODE(vfnmadd231p)(result, operand1, operand2); @@ -1386,7 +1388,7 @@ void EmitFPVectorRoundInt(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { } }(); - EmitTwoOpVectorOperation(code, ctx, inst, [&](const Xbyak::Xmm& result, const Xbyak::Xmm& xmm_a){ + EmitTwoOpVectorOperation(code, ctx, inst, [&](const Xbyak::Xmm& result, const Xbyak::Xmm& xmm_a) { FCODE(roundp)(result, xmm_a, round_imm); }); @@ -1399,8 +1401,7 @@ void EmitFPVectorRoundInt(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { mp::lift_value, mp::lift_value, mp::lift_value, - mp::lift_value - >; + mp::lift_value>; using exact_list = mp::list; static const auto lut = Common::GenerateLookupTableFromList( @@ -1416,12 +1417,9 @@ void EmitFPVectorRoundInt(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { for (size_t i = 0; i < output.size(); ++i) { output[i] = static_cast(FP::FPRoundInt(input[i], fpcr, rounding_mode, exact, fpsr)); } - } - ) - }; + })}; }, - mp::cartesian_product{} - ); + mp::cartesian_product{}); EmitTwoOpFallback<3>(code, ctx, inst, lut.at(std::make_tuple(rounding, exact))); } @@ -1501,7 +1499,7 @@ static void EmitRSqrtStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in const Xbyak::Xmm operand1 = ctx.reg_alloc.UseXmm(args[0]); const Xbyak::Xmm operand2 = ctx.reg_alloc.UseXmm(args[1]); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { code.vmovaps(result, GetVectorOf(code)); FCODE(vfnmadd231p)(result, operand1, operand2); FCODE(vmulp)(result, result, GetVectorOf(code)); @@ -1523,12 +1521,12 @@ static void EmitRSqrtStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in Xbyak::Label end, fallback; - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { code.vmovaps(result, GetVectorOf(code)); FCODE(vfnmadd231p)(result, operand1, operand2); // An explanation for this is given in EmitFPRSqrtStepFused. - code.vmovaps(mask, GetVectorOf(code)); + code.vmovaps(mask, GetVectorOf(code)); FCODE(vandp)(tmp, result, mask); ICODE(vpcmpeq)(tmp, tmp, mask); code.ptest(tmp, tmp); @@ -1620,9 +1618,8 @@ void EmitFPVectorToFixed(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { const Xbyak::Xmm src = ctx.reg_alloc.UseScratchXmm(args[0]); - MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ - - const int round_imm = [&]{ + MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&] { + const int round_imm = [&] { switch (rounding) { case FP::RoundingMode::ToNearest_TieEven: default: @@ -1659,8 +1656,8 @@ void EmitFPVectorToFixed(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { if (fbits != 0) { const u64 scale_factor = fsize == 32 - ? static_cast(fbits + 127) << 23 - : static_cast(fbits + 1023) << 52; + ? static_cast(fbits + 127) << 23 + : static_cast(fbits + 1023) << 52; FCODE(mulp)(src, GetVectorOf(code, scale_factor)); } @@ -1702,7 +1699,6 @@ void EmitFPVectorToFixed(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { perform_conversion(src); FCODE(blendvp)(src, GetVectorOf(code)); } - }); ctx.reg_alloc.DefineValue(inst, src); @@ -1716,8 +1712,7 @@ void EmitFPVectorToFixed(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { mp::lift_value, mp::lift_value, mp::lift_value, - mp::lift_value - >; + mp::lift_value>; static const auto lut = Common::GenerateLookupTableFromList( [](auto arg) { @@ -1732,12 +1727,9 @@ void EmitFPVectorToFixed(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { for (size_t i = 0; i < output.size(); ++i) { output[i] = static_cast(FP::FPToFixed(fsize, input[i], fbits, unsigned_, fpcr, rounding_mode, fpsr)); } - } - ) - }; + })}; }, - mp::cartesian_product{} - ); + mp::cartesian_product{}); EmitTwoOpFallback<3>(code, ctx, inst, lut.at(std::make_tuple(fbits, rounding))); } @@ -1766,4 +1758,4 @@ void EmitX64::EmitFPVectorToUnsignedFixed64(EmitContext& ctx, IR::Inst* inst) { EmitFPVectorToFixed<64, true>(code, ctx, inst); } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/emit_x64_vector_saturation.cpp b/src/dynarmic/backend/x64/emit_x64_vector_saturation.cpp index a3726ae0..62b2a294 100644 --- a/src/dynarmic/backend/x64/emit_x64_vector_saturation.cpp +++ b/src/dynarmic/backend/x64/emit_x64_vector_saturation.cpp @@ -131,7 +131,7 @@ void EmitVectorSignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst* in } } -} // anonymous namespace +} // anonymous namespace void EmitX64::EmitVectorSignedSaturatedAdd8(EmitContext& ctx, IR::Inst* inst) { EmitVectorSaturatedNative(code, ctx, inst, &Xbyak::CodeGenerator::paddsb, &Xbyak::CodeGenerator::paddb, &Xbyak::CodeGenerator::psubb); @@ -321,4 +321,4 @@ void EmitX64::EmitVectorUnsignedSaturatedSub64(EmitContext& ctx, IR::Inst* inst) ctx.reg_alloc.DefineValue(inst, tmp); } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/exception_handler.h b/src/dynarmic/backend/x64/exception_handler.h index f4faf080..0e361ced 100644 --- a/src/dynarmic/backend/x64/exception_handler.h +++ b/src/dynarmic/backend/x64/exception_handler.h @@ -34,4 +34,4 @@ private: std::unique_ptr impl; }; -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/exception_handler_generic.cpp b/src/dynarmic/backend/x64/exception_handler_generic.cpp index f6885080..1bbf4e54 100644 --- a/src/dynarmic/backend/x64/exception_handler_generic.cpp +++ b/src/dynarmic/backend/x64/exception_handler_generic.cpp @@ -25,4 +25,4 @@ void ExceptionHandler::SetFastmemCallback(std::function) { // Do nothing } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/exception_handler_macos.cpp b/src/dynarmic/backend/x64/exception_handler_macos.cpp index 8899fd1e..21b928d8 100644 --- a/src/dynarmic/backend/x64/exception_handler_macos.cpp +++ b/src/dynarmic/backend/x64/exception_handler_macos.cpp @@ -3,8 +3,6 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/backend/x64/exception_handler.h" - #include #include @@ -18,6 +16,7 @@ #include #include "dynarmic/backend/x64/block_of_code.h" +#include "dynarmic/backend/x64/exception_handler.h" #include "dynarmic/common/assert.h" #include "dynarmic/common/cast_util.h" #include "dynarmic/common/common_types.h" @@ -36,7 +35,7 @@ struct CodeBlockInfo { struct MachMessage { mach_msg_header_t head; - char data[2048]; ///< Arbitrary size + char data[2048]; ///< Arbitrary size }; class MachHandler final { @@ -64,7 +63,7 @@ private: }; MachHandler::MachHandler() { - #define KCHECK(x) ASSERT_MSG((x) == KERN_SUCCESS, "dynarmic: macOS MachHandler: init failure at {}", #x) +#define KCHECK(x) ASSERT_MSG((x) == KERN_SUCCESS, "dynarmic: macOS MachHandler: init failure at {}", #x) KCHECK(mach_port_allocate(mach_task_self(), MACH_PORT_RIGHT_RECEIVE, &server_port)); KCHECK(mach_port_insert_right(mach_task_self(), server_port, server_port, MACH_MSG_TYPE_MAKE_SEND)); @@ -74,7 +73,7 @@ MachHandler::MachHandler() { mach_port_t prev; KCHECK(mach_port_request_notification(mach_task_self(), server_port, MACH_NOTIFY_PORT_DESTROYED, 0, server_port, MACH_MSG_TYPE_MAKE_SEND_ONCE, &prev)); - #undef KCHECK +#undef KCHECK thread = std::thread(&MachHandler::MessagePump, this); } @@ -102,7 +101,7 @@ void MachHandler::MessagePump() { } mr = mach_msg(&reply.head, MACH_SEND_MSG, reply.head.msgh_size, 0, MACH_PORT_NULL, MACH_MSG_TIMEOUT_NONE, MACH_PORT_NULL); - if (mr != MACH_MSG_SUCCESS){ + if (mr != MACH_MSG_SUCCESS) { fmt::print(stderr, "dynarmic: macOS MachHandler: Failed to send mach message. error: {:#08x} ({})\n", mr, mach_error_string(mr)); return; } @@ -146,7 +145,7 @@ void MachHandler::RemoveCodeBlock(u64 rip) { MachHandler mach_handler; -} // anonymous namespace +} // anonymous namespace mig_external kern_return_t catch_mach_exception_raise(mach_port_t, mach_port_t, mach_port_t, exception_type_t, mach_exception_data_t, mach_msg_type_number_t) { fmt::print(stderr, "dynarmic: Unexpected mach message: mach_exception_raise\n"); @@ -161,14 +160,13 @@ mig_external kern_return_t catch_mach_exception_raise_state_identity(mach_port_t mig_external kern_return_t catch_mach_exception_raise_state( mach_port_t /*exception_port*/, exception_type_t exception, - const mach_exception_data_t /*code*/, // code[0] is as per kern_return.h, code[1] is rip. + const mach_exception_data_t /*code*/, // code[0] is as per kern_return.h, code[1] is rip. mach_msg_type_number_t /*codeCnt*/, int* flavor, const thread_state_t old_state, mach_msg_type_number_t old_stateCnt, thread_state_t new_state, - mach_msg_type_number_t* new_stateCnt -) { + mach_msg_type_number_t* new_stateCnt) { if (!flavor || !new_stateCnt) { fmt::print(stderr, "dynarmic: catch_mach_exception_raise_state: Invalid arguments.\n"); return KERN_INVALID_ARGUMENT; @@ -191,9 +189,8 @@ mig_external kern_return_t catch_mach_exception_raise_state( struct ExceptionHandler::Impl final { Impl(BlockOfCode& code) - : code_begin(Common::BitCast(code.getCode())) - , code_end(code_begin + code.GetTotalCodeSize()) - {} + : code_begin(Common::BitCast(code.getCode())) + , code_end(code_begin + code.GetTotalCodeSize()) {} void SetCallback(std::function cb) { CodeBlockInfo cbi; @@ -227,4 +224,4 @@ void ExceptionHandler::SetFastmemCallback(std::function cb) { impl->SetCallback(cb); } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/exception_handler_posix.cpp b/src/dynarmic/backend/x64/exception_handler_posix.cpp index ea08703a..37832c79 100644 --- a/src/dynarmic/backend/x64/exception_handler_posix.cpp +++ b/src/dynarmic/backend/x64/exception_handler_posix.cpp @@ -5,19 +5,20 @@ #include "dynarmic/backend/x64/exception_handler.h" +#ifdef __APPLE__ +# include +# include +#else +# include +# include +#endif + #include #include #include #include #include -#include -#ifdef __APPLE__ -#include -#else -#include -#endif - #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/common/assert.h" #include "dynarmic/common/cast_util.h" @@ -121,16 +122,16 @@ void SigHandler::SigAction(int sig, siginfo_t* info, void* raw_context) { ASSERT(sig == SIGSEGV || sig == SIGBUS); #if defined(__APPLE__) - #define CTX_RIP (((ucontext_t*)raw_context)->uc_mcontext->__ss.__rip) - #define CTX_RSP (((ucontext_t*)raw_context)->uc_mcontext->__ss.__rsp) +# define CTX_RIP (((ucontext_t*)raw_context)->uc_mcontext->__ss.__rip) +# define CTX_RSP (((ucontext_t*)raw_context)->uc_mcontext->__ss.__rsp) #elif defined(__linux__) - #define CTX_RIP (((ucontext_t*)raw_context)->uc_mcontext.gregs[REG_RIP]) - #define CTX_RSP (((ucontext_t*)raw_context)->uc_mcontext.gregs[REG_RSP]) +# define CTX_RIP (((ucontext_t*)raw_context)->uc_mcontext.gregs[REG_RIP]) +# define CTX_RSP (((ucontext_t*)raw_context)->uc_mcontext.gregs[REG_RSP]) #elif defined(__FreeBSD__) - #define CTX_RIP (((ucontext_t*)raw_context)->uc_mcontext.mc_rip) - #define CTX_RSP (((ucontext_t*)raw_context)->uc_mcontext.mc_rsp) +# define CTX_RIP (((ucontext_t*)raw_context)->uc_mcontext.mc_rip) +# define CTX_RSP (((ucontext_t*)raw_context)->uc_mcontext.mc_rsp) #else - #error "Unknown platform" +# error "Unknown platform" #endif { @@ -152,26 +153,25 @@ void SigHandler::SigAction(int sig, siginfo_t* info, void* raw_context) { struct sigaction* retry_sa = sig == SIGSEGV ? &sig_handler.old_sa_segv : &sig_handler.old_sa_bus; if (retry_sa->sa_flags & SA_SIGINFO) { - retry_sa->sa_sigaction(sig, info, raw_context); - return; + retry_sa->sa_sigaction(sig, info, raw_context); + return; } if (retry_sa->sa_handler == SIG_DFL) { - signal(sig, SIG_DFL); - return; + signal(sig, SIG_DFL); + return; } if (retry_sa->sa_handler == SIG_IGN) { - return; + return; } retry_sa->sa_handler(sig); } -} // anonymous namespace +} // anonymous namespace struct ExceptionHandler::Impl final { Impl(BlockOfCode& code) - : code_begin(Common::BitCast(code.getCode())) - , code_end(code_begin + code.GetTotalCodeSize()) - {} + : code_begin(Common::BitCast(code.getCode())) + , code_end(code_begin + code.GetTotalCodeSize()) {} void SetCallback(std::function cb) { CodeBlockInfo cbi; @@ -204,4 +204,4 @@ void ExceptionHandler::SetFastmemCallback(std::function cb) { impl->SetCallback(cb); } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/exception_handler_windows.cpp b/src/dynarmic/backend/x64/exception_handler_windows.cpp index 015ce2e4..cb746eb2 100644 --- a/src/dynarmic/backend/x64/exception_handler_windows.cpp +++ b/src/dynarmic/backend/x64/exception_handler_windows.cpp @@ -3,12 +3,12 @@ * SPDX-License-Identifier: 0BSD */ -#include -#include - #define WIN32_LEAN_AND_MEAN #include +#include +#include + #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/exception_handler.h" #include "dynarmic/common/assert.h" @@ -187,14 +187,13 @@ struct ExceptionHandler::Impl final { code.mov(code.ABI_PARAM1, Common::BitCast(&cb)); code.mov(code.ABI_PARAM2, code.ABI_PARAM3); code.CallLambda( - [](const std::function& cb_, PCONTEXT ctx){ + [](const std::function& cb_, PCONTEXT ctx) { FakeCall fc = cb_(ctx->Rip); ctx->Rsp -= sizeof(u64); *Common::BitCast(ctx->Rsp) = fc.ret_rip; ctx->Rip = fc.call_rip; - } - ); + }); code.add(code.rsp, 8); code.mov(code.eax, static_cast(ExceptionContinueExecution)); code.ret(); @@ -208,8 +207,8 @@ struct ExceptionHandler::Impl final { unwind_info->Flags = UNW_FLAG_EHANDLER; unwind_info->SizeOfProlog = prolog_info.prolog_size; unwind_info->CountOfCodes = static_cast(prolog_info.number_of_unwind_code_entries); - unwind_info->FrameRegister = 0; // No frame register present - unwind_info->FrameOffset = 0; // Unused because FrameRegister == 0 + unwind_info->FrameRegister = 0; // No frame register present + unwind_info->FrameOffset = 0; // Unused because FrameRegister == 0 // UNWIND_INFO::UnwindCode field: const size_t size_of_unwind_code = sizeof(UNWIND_CODE) * prolog_info.unwind_code.size(); UNWIND_CODE* unwind_code = static_cast(code.AllocateFromCodeSpace(size_of_unwind_code)); @@ -259,4 +258,4 @@ void ExceptionHandler::SetFastmemCallback(std::function cb) { impl->SetCallback(cb); } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/exclusive_monitor.cpp b/src/dynarmic/backend/x64/exclusive_monitor.cpp index 5a2d8082..0f66270f 100644 --- a/src/dynarmic/backend/x64/exclusive_monitor.cpp +++ b/src/dynarmic/backend/x64/exclusive_monitor.cpp @@ -3,15 +3,16 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/interface/exclusive_monitor.h" + #include #include "dynarmic/common/assert.h" -#include "dynarmic/interface/exclusive_monitor.h" namespace Dynarmic { -ExclusiveMonitor::ExclusiveMonitor(size_t processor_count) : - exclusive_addresses(processor_count, INVALID_EXCLUSIVE_ADDRESS), exclusive_values(processor_count) { +ExclusiveMonitor::ExclusiveMonitor(size_t processor_count) + : exclusive_addresses(processor_count, INVALID_EXCLUSIVE_ADDRESS), exclusive_values(processor_count) { Unlock(); } @@ -56,4 +57,4 @@ void ExclusiveMonitor::ClearProcessor(size_t processor_id) { Unlock(); } -} // namespace Dynarmic +} // namespace Dynarmic diff --git a/src/dynarmic/backend/x64/host_feature.h b/src/dynarmic/backend/x64/host_feature.h index 8d5ee9a8..135a4906 100644 --- a/src/dynarmic/backend/x64/host_feature.h +++ b/src/dynarmic/backend/x64/host_feature.h @@ -10,35 +10,35 @@ namespace Dynarmic::Backend::X64 { enum class HostFeature : u64 { - SSSE3 = 1ULL << 0, - SSE41 = 1ULL << 1, - SSE42 = 1ULL << 2, - AVX = 1ULL << 3, - AVX2 = 1ULL << 4, - AVX512F = 1ULL << 5, - AVX512CD = 1ULL << 6, - AVX512VL = 1ULL << 7, - AVX512BW = 1ULL << 8, - AVX512DQ = 1ULL << 9, - AVX512BITALG = 1ULL << 10, - PCLMULQDQ = 1ULL << 11, - F16C = 1ULL << 12, - FMA = 1ULL << 13, - AES = 1ULL << 14, - POPCNT = 1ULL << 15, - BMI1 = 1ULL << 16, - BMI2 = 1ULL << 17, - LZCNT = 1ULL << 18, - GFNI = 1ULL << 19, + SSSE3 = 1ULL << 0, + SSE41 = 1ULL << 1, + SSE42 = 1ULL << 2, + AVX = 1ULL << 3, + AVX2 = 1ULL << 4, + AVX512F = 1ULL << 5, + AVX512CD = 1ULL << 6, + AVX512VL = 1ULL << 7, + AVX512BW = 1ULL << 8, + AVX512DQ = 1ULL << 9, + AVX512BITALG = 1ULL << 10, + PCLMULQDQ = 1ULL << 11, + F16C = 1ULL << 12, + FMA = 1ULL << 13, + AES = 1ULL << 14, + POPCNT = 1ULL << 15, + BMI1 = 1ULL << 16, + BMI2 = 1ULL << 17, + LZCNT = 1ULL << 18, + GFNI = 1ULL << 19, // Zen-based BMI2 - FastBMI2 = 1ULL << 20, + FastBMI2 = 1ULL << 20, // Orthographic AVX512 features on 128 and 256 vectors - AVX512_Ortho = AVX512F | AVX512VL, + AVX512_Ortho = AVX512F | AVX512VL, // Orthographic AVX512 features for both 32-bit and 64-bit floats - AVX512_OrthoFloat = AVX512_Ortho | AVX512DQ, + AVX512_OrthoFloat = AVX512_Ortho | AVX512DQ, }; constexpr HostFeature operator~(HostFeature f) { @@ -61,4 +61,4 @@ constexpr HostFeature operator&=(HostFeature& result, HostFeature f) { return result = (result & f); } -} +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/hostloc.cpp b/src/dynarmic/backend/x64/hostloc.cpp index 846fc77b..53b7a83b 100644 --- a/src/dynarmic/backend/x64/hostloc.cpp +++ b/src/dynarmic/backend/x64/hostloc.cpp @@ -3,10 +3,11 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/backend/x64/hostloc.h" + #include #include "dynarmic/backend/x64/abi.h" -#include "dynarmic/backend/x64/hostloc.h" #include "dynarmic/backend/x64/stack_layout.h" namespace Dynarmic::Backend::X64 { @@ -21,4 +22,4 @@ Xbyak::Xmm HostLocToXmm(HostLoc loc) { return Xbyak::Xmm(static_cast(loc) - static_cast(HostLoc::XMM0)); } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/hostloc.h b/src/dynarmic/backend/x64/hostloc.h index 41e962df..ee704bbb 100644 --- a/src/dynarmic/backend/x64/hostloc.h +++ b/src/dynarmic/backend/x64/hostloc.h @@ -13,10 +13,44 @@ namespace Dynarmic::Backend::X64 { enum class HostLoc { // Ordering of the registers is intentional. See also: HostLocToX64. - RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI, R8, R9, R10, R11, R12, R13, R14, R15, - XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, - XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, - CF, PF, AF, ZF, SF, OF, + RAX, + RCX, + RDX, + RBX, + RSP, + RBP, + RSI, + RDI, + R8, + R9, + R10, + R11, + R12, + R13, + R14, + R15, + XMM0, + XMM1, + XMM2, + XMM3, + XMM4, + XMM5, + XMM6, + XMM7, + XMM8, + XMM9, + XMM10, + XMM11, + XMM12, + XMM13, + XMM14, + XMM15, + CF, + PF, + AF, + ZF, + SF, + OF, FirstSpill, }; @@ -111,4 +145,4 @@ const HostLocList any_xmm = { Xbyak::Reg64 HostLocToReg64(HostLoc loc); Xbyak::Xmm HostLocToXmm(HostLoc loc); -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/jitstate_info.h b/src/dynarmic/backend/x64/jitstate_info.h index 1e077055..e8718886 100644 --- a/src/dynarmic/backend/x64/jitstate_info.h +++ b/src/dynarmic/backend/x64/jitstate_info.h @@ -10,18 +10,17 @@ namespace Dynarmic::Backend::X64 { struct JitStateInfo { - template + template JitStateInfo(const JitStateType&) - : offsetof_guest_MXCSR(offsetof(JitStateType, guest_MXCSR)) - , offsetof_asimd_MXCSR(offsetof(JitStateType, asimd_MXCSR)) - , offsetof_rsb_ptr(offsetof(JitStateType, rsb_ptr)) - , rsb_ptr_mask(JitStateType::RSBPtrMask) - , offsetof_rsb_location_descriptors(offsetof(JitStateType, rsb_location_descriptors)) - , offsetof_rsb_codeptrs(offsetof(JitStateType, rsb_codeptrs)) - , offsetof_cpsr_nzcv(offsetof(JitStateType, cpsr_nzcv)) - , offsetof_fpsr_exc(offsetof(JitStateType, fpsr_exc)) - , offsetof_fpsr_qc(offsetof(JitStateType, fpsr_qc)) - {} + : offsetof_guest_MXCSR(offsetof(JitStateType, guest_MXCSR)) + , offsetof_asimd_MXCSR(offsetof(JitStateType, asimd_MXCSR)) + , offsetof_rsb_ptr(offsetof(JitStateType, rsb_ptr)) + , rsb_ptr_mask(JitStateType::RSBPtrMask) + , offsetof_rsb_location_descriptors(offsetof(JitStateType, rsb_location_descriptors)) + , offsetof_rsb_codeptrs(offsetof(JitStateType, rsb_codeptrs)) + , offsetof_cpsr_nzcv(offsetof(JitStateType, cpsr_nzcv)) + , offsetof_fpsr_exc(offsetof(JitStateType, fpsr_exc)) + , offsetof_fpsr_qc(offsetof(JitStateType, fpsr_qc)) {} const size_t offsetof_guest_MXCSR; const size_t offsetof_asimd_MXCSR; @@ -34,4 +33,4 @@ struct JitStateInfo { const size_t offsetof_fpsr_qc; }; -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/nzcv_util.h b/src/dynarmic/backend/x64/nzcv_util.h index 8467aad2..389723a8 100644 --- a/src/dynarmic/backend/x64/nzcv_util.h +++ b/src/dynarmic/backend/x64/nzcv_util.h @@ -5,8 +5,8 @@ #pragma once -#include "dynarmic/common/common_types.h" #include "dynarmic/common/bit_util.h" +#include "dynarmic/common/common_types.h" namespace Dynarmic::Backend::X64::NZCV { @@ -50,4 +50,4 @@ inline u32 FromX64(u32 x64_flags) { return ((x64_flags & x64_mask) * from_x64_multiplier) & arm_mask; } -} // namespace Dynarmic::Backend::X64::NZCV +} // namespace Dynarmic::Backend::X64::NZCV diff --git a/src/dynarmic/backend/x64/oparg.h b/src/dynarmic/backend/x64/oparg.h index 88b6fdd6..5a598e54 100644 --- a/src/dynarmic/backend/x64/oparg.h +++ b/src/dynarmic/backend/x64/oparg.h @@ -12,9 +12,12 @@ namespace Dynarmic::Backend::X64 { struct OpArg { - OpArg() : type(Type::Operand), inner_operand() {} - /* implicit */ OpArg(const Xbyak::Address& address) : type(Type::Address), inner_address(address) {} - /* implicit */ OpArg(const Xbyak::Reg& reg) : type(Type::Reg), inner_reg(reg) {} + OpArg() + : type(Type::Operand), inner_operand() {} + /* implicit */ OpArg(const Xbyak::Address& address) + : type(Type::Address), inner_address(address) {} + /* implicit */ OpArg(const Xbyak::Reg& reg) + : type(Type::Reg), inner_reg(reg) {} Xbyak::Operand& operator*() { switch (type) { @@ -74,4 +77,4 @@ private: }; }; -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/perf_map.cpp b/src/dynarmic/backend/x64/perf_map.cpp index 56dedad7..4a74081f 100644 --- a/src/dynarmic/backend/x64/perf_map.cpp +++ b/src/dynarmic/backend/x64/perf_map.cpp @@ -3,22 +3,22 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/backend/x64/perf_map.h" + #include #include -#include "dynarmic/backend/x64/perf_map.h" - #ifdef __linux__ -#include -#include -#include -#include -#include +# include +# include +# include -#include +# include +# include +# include -#include "dynarmic/common/common_types.h" +# include "dynarmic/common/common_types.h" namespace Dynarmic::Backend::X64 { @@ -43,7 +43,7 @@ void OpenFile() { std::setvbuf(file, nullptr, _IONBF, 0); } -} // anonymous namespace +} // anonymous namespace namespace detail { void PerfMapRegister(const void* start, const void* end, std::string_view friendly_name) { @@ -64,7 +64,7 @@ void PerfMapRegister(const void* start, const void* end, std::string_view friend const std::string line = fmt::format("{:016x} {:016x} {:s}\n", reinterpret_cast(start), reinterpret_cast(end) - reinterpret_cast(start), friendly_name); std::fwrite(line.data(), sizeof *line.data(), line.size(), file); } -} // namespace detail +} // namespace detail void PerfMapClear() { std::lock_guard guard{mutex}; @@ -78,7 +78,7 @@ void PerfMapClear() { OpenFile(); } -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 #else @@ -86,10 +86,10 @@ namespace Dynarmic::Backend::X64 { namespace detail { void PerfMapRegister(const void*, const void*, std::string_view) {} -} // namespace detail +} // namespace detail void PerfMapClear() {} -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 #endif diff --git a/src/dynarmic/backend/x64/perf_map.h b/src/dynarmic/backend/x64/perf_map.h index 4a38cf79..02cd0b85 100644 --- a/src/dynarmic/backend/x64/perf_map.h +++ b/src/dynarmic/backend/x64/perf_map.h @@ -13,7 +13,7 @@ namespace Dynarmic::Backend::X64 { namespace detail { void PerfMapRegister(const void* start, const void* end, std::string_view friendly_name); -} // namespace detail +} // namespace detail template void PerfMapRegister(T start, const void* end, std::string_view friendly_name) { @@ -22,4 +22,4 @@ void PerfMapRegister(T start, const void* end, std::string_view friendly_name) { void PerfMapClear(); -} // namespace Dynarmic::Backend::X64 +} // namespace Dynarmic::Backend::X64 diff --git a/src/dynarmic/backend/x64/reg_alloc.cpp b/src/dynarmic/backend/x64/reg_alloc.cpp index 61c48b55..aea61a17 100644 --- a/src/dynarmic/backend/x64/reg_alloc.cpp +++ b/src/dynarmic/backend/x64/reg_alloc.cpp @@ -3,6 +3,8 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/backend/x64/reg_alloc.h" + #include #include #include @@ -11,19 +13,18 @@ #include #include "dynarmic/backend/x64/abi.h" -#include "dynarmic/backend/x64/reg_alloc.h" #include "dynarmic/backend/x64/stack_layout.h" #include "dynarmic/common/assert.h" namespace Dynarmic::Backend::X64 { -#define MAYBE_AVX(OPCODE, ...) \ - [&] { \ - if (code.HasHostFeature(HostFeature::AVX)) { \ - code.v##OPCODE(__VA_ARGS__); \ - } else { \ - code.OPCODE(__VA_ARGS__); \ - } \ +#define MAYBE_AVX(OPCODE, ...) \ + [&] { \ + if (code.HasHostFeature(HostFeature::AVX)) { \ + code.v##OPCODE(__VA_ARGS__); \ + } else { \ + code.OPCODE(__VA_ARGS__); \ + } \ }() static bool CanExchange(HostLoc a, HostLoc b) { @@ -57,7 +58,7 @@ static size_t GetBitWidth(IR::Type type) { case IR::Type::U128: return 128; case IR::Type::NZCVFlags: - return 32; // TODO: Update to 16 when flags optimization is done + return 32; // TODO: Update to 16 when flags optimization is done } UNREACHABLE(); } @@ -225,11 +226,10 @@ bool Argument::IsInMemory() const { } RegAlloc::RegAlloc(BlockOfCode& code, std::vector gpr_order, std::vector xmm_order) - : gpr_order(gpr_order) - , xmm_order(xmm_order) - , hostloc_info(NonSpillHostLocCount + SpillCount) - , code(code) -{} + : gpr_order(gpr_order) + , xmm_order(xmm_order) + , hostloc_info(NonSpillHostLocCount + SpillCount) + , code(code) {} RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) { ArgumentInfo ret = {Argument{*this}, Argument{*this}, Argument{*this}, Argument{*this}}; @@ -382,13 +382,14 @@ HostLoc RegAlloc::ScratchImpl(const std::vector& desired_locations) { return location; } -void RegAlloc::HostCall(IR::Inst* result_def, std::optional arg0, +void RegAlloc::HostCall(IR::Inst* result_def, + std::optional arg0, std::optional arg1, std::optional arg2, std::optional arg3) { constexpr size_t args_count = 4; - constexpr std::array args_hostloc = { ABI_PARAM1, ABI_PARAM2, ABI_PARAM3, ABI_PARAM4 }; - const std::array, args_count> args = { arg0, arg1, arg2, arg3 }; + constexpr std::array args_hostloc = {ABI_PARAM1, ABI_PARAM2, ABI_PARAM3, ABI_PARAM4}; + const std::array, args_count> args = {arg0, arg1, arg2, arg3}; static const std::vector other_caller_save = [args_hostloc]() { std::vector ret(ABI_ALL_CALLER_SAVE.begin(), ABI_ALL_CALLER_SAVE.end()); @@ -420,7 +421,7 @@ void RegAlloc::HostCall(IR::Inst* result_def, std::optional #include #include -#include "dynarmic/common/assert.h" - namespace Dynarmic::Common { [[noreturn]] void Terminate(fmt::string_view msg, fmt::format_args args) { @@ -18,4 +18,4 @@ namespace Dynarmic::Common { std::terminate(); } -} // namespace Dynarmic::Common +} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/assert.h b/src/dynarmic/common/assert.h index bf241ad7..5df3c4d2 100644 --- a/src/dynarmic/common/assert.h +++ b/src/dynarmic/common/assert.h @@ -15,57 +15,57 @@ namespace Dynarmic::Common { namespace detail { -template +template [[noreturn]] void TerminateHelper(fmt::string_view msg, Ts... args) { Terminate(msg, fmt::make_format_args(args...)); } -} // namespace detail +} // namespace detail -} // namespace Dynarmic::Common +} // namespace Dynarmic::Common #if defined(__clang) || defined(__GNUC__) - #define ASSUME(expr) [&]{ if (!(expr)) __builtin_unreachable(); }() +# define ASSUME(expr) [&] { if (!(expr)) __builtin_unreachable(); }() #elif defined(_MSC_VER) - #define ASSUME(expr) __assume(expr) +# define ASSUME(expr) __assume(expr) #else - #define ASSUME(expr) +# define ASSUME(expr) #endif #ifdef DYNARMIC_IGNORE_ASSERTS - #if defined(__clang) || defined(__GNUC__) - #define UNREACHABLE() __builtin_unreachable() - #elif defined(_MSC_VER) - #define UNREACHABLE() __assume(0) - #else - #define UNREACHABLE() - #endif +# if defined(__clang) || defined(__GNUC__) +# define UNREACHABLE() __builtin_unreachable() +# elif defined(_MSC_VER) +# define UNREACHABLE() __assume(0) +# else +# define UNREACHABLE() +# endif - #define ASSERT(expr) ASSUME(expr) - #define ASSERT_MSG(expr, ...) ASSUME(expr) - #define ASSERT_FALSE(...) UNREACHABLE() +# define ASSERT(expr) ASSUME(expr) +# define ASSERT_MSG(expr, ...) ASSUME(expr) +# define ASSERT_FALSE(...) UNREACHABLE() #else - #define UNREACHABLE() ASSERT_FALSE("Unreachable code!") +# define UNREACHABLE() ASSERT_FALSE("Unreachable code!") - #define ASSERT(expr) \ - [&]{ \ - if (UNLIKELY(!(expr))) { \ - ::Dynarmic::Common::detail::TerminateHelper(#expr); \ - } \ +# define ASSERT(expr) \ + [&] { \ + if (UNLIKELY(!(expr))) { \ + ::Dynarmic::Common::detail::TerminateHelper(#expr); \ + } \ }() - #define ASSERT_MSG(expr, ...) \ - [&]{ \ - if (UNLIKELY(!(expr))) { \ - ::Dynarmic::Common::detail::TerminateHelper(#expr "\nMessage: " __VA_ARGS__); \ - } \ +# define ASSERT_MSG(expr, ...) \ + [&] { \ + if (UNLIKELY(!(expr))) { \ + ::Dynarmic::Common::detail::TerminateHelper(#expr "\nMessage: " __VA_ARGS__); \ + } \ }() - #define ASSERT_FALSE(...) ::Dynarmic::Common::detail::TerminateHelper("false\nMessage: " __VA_ARGS__) +# define ASSERT_FALSE(...) ::Dynarmic::Common::detail::TerminateHelper("false\nMessage: " __VA_ARGS__) #endif #if defined(NDEBUG) || defined(DYNARMIC_IGNORE_ASSERTS) - #define DEBUG_ASSERT(expr) ASSUME(expr) - #define DEBUG_ASSERT_MSG(expr, ...) ASSUME(expr) +# define DEBUG_ASSERT(expr) ASSUME(expr) +# define DEBUG_ASSERT_MSG(expr, ...) ASSUME(expr) #else - #define DEBUG_ASSERT(expr) ASSERT(expr) - #define DEBUG_ASSERT_MSG(expr, ...) ASSERT_MSG(expr, __VA_ARGS__) +# define DEBUG_ASSERT(expr) ASSERT(expr) +# define DEBUG_ASSERT_MSG(expr, ...) ASSERT_MSG(expr, __VA_ARGS__) #endif diff --git a/src/dynarmic/common/bit_util.h b/src/dynarmic/common/bit_util.h index 27c039f7..bb3cfae6 100644 --- a/src/dynarmic/common/bit_util.h +++ b/src/dynarmic/common/bit_util.h @@ -21,7 +21,7 @@ constexpr size_t BitSize() { return sizeof(T) * CHAR_BIT; } -template +template constexpr T Ones(size_t count) { ASSERT_MSG(count <= BitSize(), "count larger than bitsize of T"); if (count == BitSize()) @@ -72,8 +72,8 @@ constexpr T ModifyBits(const T value, const T new_bits) { } #ifdef _MSC_VER -#pragma warning(push) -#pragma warning(disable:4554) +# pragma warning(push) +# pragma warning(disable : 4554) #endif /// Extracts a single bit at bit_position from value of type T. template @@ -123,7 +123,7 @@ constexpr T ModifyBit(const T value, bool new_bit) { return ModifyBit(bit_position, value, new_bit); } #ifdef _MSC_VER -#pragma warning(pop) +# pragma warning(pop) #endif /// Sign-extends a value that has bit_count bits to the full bitwidth of type T. @@ -152,12 +152,12 @@ inline T SignExtend(const size_t bit_count, const T value) { return value; } -template +template inline size_t BitCount(Integral value) { return std::bitset()>(value).count(); } -template +template constexpr size_t CountLeadingZeros(T value) { auto x = static_cast>(value); size_t result = BitSize(); @@ -168,7 +168,7 @@ constexpr size_t CountLeadingZeros(T value) { return result; } -template +template constexpr int HighestSetBit(T value) { auto x = static_cast>(value); int result = -1; @@ -179,7 +179,7 @@ constexpr int HighestSetBit(T value) { return result; } -template +template constexpr size_t LowestSetBit(T value) { auto x = static_cast>(value); if (x == 0) @@ -193,12 +193,12 @@ constexpr size_t LowestSetBit(T value) { return result; } -template +template constexpr bool MostSignificantBit(T value) { return Bit() - 1, T>(value); } -template +template inline T Replicate(T value, size_t element_size) { ASSERT_MSG(BitSize() % element_size == 0, "bitsize of T not divisible by element_size"); if (element_size == BitSize()) @@ -206,7 +206,7 @@ inline T Replicate(T value, size_t element_size) { return Replicate(value | (value << element_size), element_size * 2); } -template +template constexpr T RotateRight(T value, size_t amount) { amount %= BitSize(); @@ -219,8 +219,8 @@ constexpr T RotateRight(T value, size_t amount) { } constexpr u32 SwapHalves32(u32 value) { - return ((value & 0xFFFF0000U) >> 16) | - ((value & 0x0000FFFFU) << 16); + return ((value & 0xFFFF0000U) >> 16) + | ((value & 0x0000FFFFU) << 16); } constexpr u16 SwapBytes16(u16 value) { @@ -228,21 +228,21 @@ constexpr u16 SwapBytes16(u16 value) { } constexpr u32 SwapBytes32(u32 value) { - return ((value & 0xFF000000U) >> 24) | - ((value & 0x00FF0000U) >> 8) | - ((value & 0x0000FF00U) << 8) | - ((value & 0x000000FFU) << 24); + return ((value & 0xFF000000U) >> 24) + | ((value & 0x00FF0000U) >> 8) + | ((value & 0x0000FF00U) << 8) + | ((value & 0x000000FFU) << 24); } constexpr u64 SwapBytes64(u64 value) { - return ((value & 0xFF00000000000000ULL) >> 56) | - ((value & 0x00FF000000000000ULL) >> 40) | - ((value & 0x0000FF0000000000ULL) >> 24) | - ((value & 0x000000FF00000000ULL) >> 8) | - ((value & 0x00000000FF000000ULL) << 8) | - ((value & 0x0000000000FF0000ULL) << 24) | - ((value & 0x000000000000FF00ULL) << 40) | - ((value & 0x00000000000000FFULL) << 56); + return ((value & 0xFF00000000000000ULL) >> 56) + | ((value & 0x00FF000000000000ULL) >> 40) + | ((value & 0x0000FF0000000000ULL) >> 24) + | ((value & 0x000000FF00000000ULL) >> 8) + | ((value & 0x00000000FF000000ULL) << 8) + | ((value & 0x0000000000FF0000ULL) << 24) + | ((value & 0x000000000000FF00ULL) << 40) + | ((value & 0x00000000000000FFULL) << 56); } -} // namespace Dynarmic::Common +} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/cast_util.h b/src/dynarmic/common/cast_util.h index 86004382..1098b51c 100644 --- a/src/dynarmic/common/cast_util.h +++ b/src/dynarmic/common/cast_util.h @@ -13,7 +13,7 @@ namespace Dynarmic::Common { /// Reinterpret objects of one type as another by bit-casting between object representations. -template +template inline Dest BitCast(const Source& source) noexcept { static_assert(sizeof(Dest) == sizeof(Source), "size of destination and source objects must be equal"); static_assert(std::is_trivially_copyable_v, "destination type must be trivially copyable."); @@ -26,7 +26,7 @@ inline Dest BitCast(const Source& source) noexcept { /// Reinterpret objects of any arbitrary type as another type by bit-casting between object representations. /// Note that here we do not verify if source has enough bytes to read from. -template +template inline Dest BitCastPointee(const SourcePtr source) noexcept { static_assert(sizeof(SourcePtr) == sizeof(void*), "source pointer must have size of a pointer"); static_assert(std::is_trivially_copyable_v, "destination type must be trivially copyable."); @@ -37,9 +37,9 @@ inline Dest BitCastPointee(const SourcePtr source) noexcept { } /// Cast a lambda into an equivalent function pointer. -template +template inline auto FptrCast(Function f) noexcept { return static_cast*>(f); } -} // namespace Dynarmic::Common +} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/crypto/aes.cpp b/src/dynarmic/common/crypto/aes.cpp index 355aa6e4..3f67dbac 100644 --- a/src/dynarmic/common/crypto/aes.cpp +++ b/src/dynarmic/common/crypto/aes.cpp @@ -3,56 +3,55 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/common/crypto/aes.h" + #include #include "dynarmic/common/common_types.h" -#include "dynarmic/common/crypto/aes.h" namespace Dynarmic::Common::Crypto::AES { using SubstitutionTable = std::array; // See section 5.1.1 Figure 7 in FIPS 197 -constexpr SubstitutionTable substitution_box{{ - // 0 1 2 3 4 5 6 7 8 9 A B C D E F - 0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76, - 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0, 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0, - 0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15, - 0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75, - 0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0, 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84, - 0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B, 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF, - 0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8, - 0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5, 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2, - 0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17, 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73, - 0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, 0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB, - 0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C, 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79, - 0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9, 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08, - 0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6, 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A, - 0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E, 0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E, - 0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94, 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF, - 0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16 -}}; +constexpr SubstitutionTable substitution_box{ + {// 0 1 2 3 4 5 6 7 8 9 A B C D E F + 0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76, + 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0, 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0, + 0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15, + 0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75, + 0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0, 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84, + 0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B, 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF, + 0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8, + 0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5, 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2, + 0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17, 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73, + 0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, 0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB, + 0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C, 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79, + 0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9, 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08, + 0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6, 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A, + 0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E, 0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E, + 0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94, 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF, + 0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16}}; // See section 5.3.2 Figure 14 in FIPS 197 -constexpr SubstitutionTable inverse_substitution_box{{ - // 0 1 2 3 4 5 6 7 8 9 A B C D E F - 0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38, 0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB, - 0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87, 0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB, - 0x54, 0x7B, 0x94, 0x32, 0xA6, 0xC2, 0x23, 0x3D, 0xEE, 0x4C, 0x95, 0x0B, 0x42, 0xFA, 0xC3, 0x4E, - 0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2, 0x76, 0x5B, 0xA2, 0x49, 0x6D, 0x8B, 0xD1, 0x25, - 0x72, 0xF8, 0xF6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xD4, 0xA4, 0x5C, 0xCC, 0x5D, 0x65, 0xB6, 0x92, - 0x6C, 0x70, 0x48, 0x50, 0xFD, 0xED, 0xB9, 0xDA, 0x5E, 0x15, 0x46, 0x57, 0xA7, 0x8D, 0x9D, 0x84, - 0x90, 0xD8, 0xAB, 0x00, 0x8C, 0xBC, 0xD3, 0x0A, 0xF7, 0xE4, 0x58, 0x05, 0xB8, 0xB3, 0x45, 0x06, - 0xD0, 0x2C, 0x1E, 0x8F, 0xCA, 0x3F, 0x0F, 0x02, 0xC1, 0xAF, 0xBD, 0x03, 0x01, 0x13, 0x8A, 0x6B, - 0x3A, 0x91, 0x11, 0x41, 0x4F, 0x67, 0xDC, 0xEA, 0x97, 0xF2, 0xCF, 0xCE, 0xF0, 0xB4, 0xE6, 0x73, - 0x96, 0xAC, 0x74, 0x22, 0xE7, 0xAD, 0x35, 0x85, 0xE2, 0xF9, 0x37, 0xE8, 0x1C, 0x75, 0xDF, 0x6E, - 0x47, 0xF1, 0x1A, 0x71, 0x1D, 0x29, 0xC5, 0x89, 0x6F, 0xB7, 0x62, 0x0E, 0xAA, 0x18, 0xBE, 0x1B, - 0xFC, 0x56, 0x3E, 0x4B, 0xC6, 0xD2, 0x79, 0x20, 0x9A, 0xDB, 0xC0, 0xFE, 0x78, 0xCD, 0x5A, 0xF4, - 0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, 0xC7, 0x31, 0xB1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xEC, 0x5F, - 0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D, 0x2D, 0xE5, 0x7A, 0x9F, 0x93, 0xC9, 0x9C, 0xEF, - 0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0, 0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61, - 0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26, 0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D -}}; +constexpr SubstitutionTable inverse_substitution_box{ + {// 0 1 2 3 4 5 6 7 8 9 A B C D E F + 0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38, 0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB, + 0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87, 0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB, + 0x54, 0x7B, 0x94, 0x32, 0xA6, 0xC2, 0x23, 0x3D, 0xEE, 0x4C, 0x95, 0x0B, 0x42, 0xFA, 0xC3, 0x4E, + 0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2, 0x76, 0x5B, 0xA2, 0x49, 0x6D, 0x8B, 0xD1, 0x25, + 0x72, 0xF8, 0xF6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xD4, 0xA4, 0x5C, 0xCC, 0x5D, 0x65, 0xB6, 0x92, + 0x6C, 0x70, 0x48, 0x50, 0xFD, 0xED, 0xB9, 0xDA, 0x5E, 0x15, 0x46, 0x57, 0xA7, 0x8D, 0x9D, 0x84, + 0x90, 0xD8, 0xAB, 0x00, 0x8C, 0xBC, 0xD3, 0x0A, 0xF7, 0xE4, 0x58, 0x05, 0xB8, 0xB3, 0x45, 0x06, + 0xD0, 0x2C, 0x1E, 0x8F, 0xCA, 0x3F, 0x0F, 0x02, 0xC1, 0xAF, 0xBD, 0x03, 0x01, 0x13, 0x8A, 0x6B, + 0x3A, 0x91, 0x11, 0x41, 0x4F, 0x67, 0xDC, 0xEA, 0x97, 0xF2, 0xCF, 0xCE, 0xF0, 0xB4, 0xE6, 0x73, + 0x96, 0xAC, 0x74, 0x22, 0xE7, 0xAD, 0x35, 0x85, 0xE2, 0xF9, 0x37, 0xE8, 0x1C, 0x75, 0xDF, 0x6E, + 0x47, 0xF1, 0x1A, 0x71, 0x1D, 0x29, 0xC5, 0x89, 0x6F, 0xB7, 0x62, 0x0E, 0xAA, 0x18, 0xBE, 0x1B, + 0xFC, 0x56, 0x3E, 0x4B, 0xC6, 0xD2, 0x79, 0x20, 0x9A, 0xDB, 0xC0, 0xFE, 0x78, 0xCD, 0x5A, 0xF4, + 0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, 0xC7, 0x31, 0xB1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xEC, 0x5F, + 0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D, 0x2D, 0xE5, 0x7A, 0x9F, 0x93, 0xC9, 0x9C, 0xEF, + 0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0, 0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61, + 0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26, 0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D}}; // See section 4.2.1 in FIPS 197. static constexpr u8 xtime(u8 x) { @@ -61,11 +60,11 @@ static constexpr u8 xtime(u8 x) { // Galois Field multiplication. static constexpr u8 Multiply(u8 x, u8 y) { - return static_cast(((y & 1) * x) ^ - ((y >> 1 & 1) * xtime(x)) ^ - ((y >> 2 & 1) * xtime(xtime(x))) ^ - ((y >> 3 & 1) * xtime(xtime(xtime(x)))) ^ - ((y >> 4 & 1) * xtime(xtime(xtime(xtime(x)))))); + return static_cast(((y & 1) * x) + ^ ((y >> 1 & 1) * xtime(x)) + ^ ((y >> 2 & 1) * xtime(xtime(x))) + ^ ((y >> 3 & 1) * xtime(xtime(xtime(x)))) + ^ ((y >> 4 & 1) * xtime(xtime(xtime(xtime(x)))))); } static void ShiftRows(State& out_state, const State& state) { @@ -178,4 +177,4 @@ void InverseMixColumns(State& out_state, const State& state) { } } -} // namespace Dynarmic::Common::Crypto::AES +} // namespace Dynarmic::Common::Crypto::AES diff --git a/src/dynarmic/common/crypto/aes.h b/src/dynarmic/common/crypto/aes.h index 0ab836aa..8e1e76fe 100644 --- a/src/dynarmic/common/crypto/aes.h +++ b/src/dynarmic/common/crypto/aes.h @@ -6,6 +6,7 @@ #pragma once #include + #include "dynarmic/common/common_types.h" namespace Dynarmic::Common::Crypto::AES { @@ -19,4 +20,4 @@ void EncryptSingleRound(State& out_state, const State& state); void MixColumns(State& out_state, const State& state); void InverseMixColumns(State& out_state, const State& state); -} // namespace Dynarmic::Common::Crypto::AES +} // namespace Dynarmic::Common::Crypto::AES diff --git a/src/dynarmic/common/crypto/crc32.cpp b/src/dynarmic/common/crypto/crc32.cpp index 60ccc690..6b33a88c 100644 --- a/src/dynarmic/common/crypto/crc32.cpp +++ b/src/dynarmic/common/crypto/crc32.cpp @@ -3,150 +3,149 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/common/crypto/crc32.h" + #include #include "dynarmic/common/common_types.h" -#include "dynarmic/common/crypto/crc32.h" namespace Dynarmic::Common::Crypto::CRC32 { using CRC32Table = std::array; // CRC32 algorithm that uses polynomial 0x1EDC6F41 -constexpr CRC32Table castagnoli_table{{ - 0x00000000, 0xF26B8303, 0xE13B70F7, 0x1350F3F4, - 0xC79A971F, 0x35F1141C, 0x26A1E7E8, 0xD4CA64EB, - 0x8AD958CF, 0x78B2DBCC, 0x6BE22838, 0x9989AB3B, - 0x4D43CFD0, 0xBF284CD3, 0xAC78BF27, 0x5E133C24, - 0x105EC76F, 0xE235446C, 0xF165B798, 0x030E349B, - 0xD7C45070, 0x25AFD373, 0x36FF2087, 0xC494A384, - 0x9A879FA0, 0x68EC1CA3, 0x7BBCEF57, 0x89D76C54, - 0x5D1D08BF, 0xAF768BBC, 0xBC267848, 0x4E4DFB4B, - 0x20BD8EDE, 0xD2D60DDD, 0xC186FE29, 0x33ED7D2A, - 0xE72719C1, 0x154C9AC2, 0x061C6936, 0xF477EA35, - 0xAA64D611, 0x580F5512, 0x4B5FA6E6, 0xB93425E5, - 0x6DFE410E, 0x9F95C20D, 0x8CC531F9, 0x7EAEB2FA, - 0x30E349B1, 0xC288CAB2, 0xD1D83946, 0x23B3BA45, - 0xF779DEAE, 0x05125DAD, 0x1642AE59, 0xE4292D5A, - 0xBA3A117E, 0x4851927D, 0x5B016189, 0xA96AE28A, - 0x7DA08661, 0x8FCB0562, 0x9C9BF696, 0x6EF07595, - 0x417B1DBC, 0xB3109EBF, 0xA0406D4B, 0x522BEE48, - 0x86E18AA3, 0x748A09A0, 0x67DAFA54, 0x95B17957, - 0xCBA24573, 0x39C9C670, 0x2A993584, 0xD8F2B687, - 0x0C38D26C, 0xFE53516F, 0xED03A29B, 0x1F682198, - 0x5125DAD3, 0xA34E59D0, 0xB01EAA24, 0x42752927, - 0x96BF4DCC, 0x64D4CECF, 0x77843D3B, 0x85EFBE38, - 0xDBFC821C, 0x2997011F, 0x3AC7F2EB, 0xC8AC71E8, - 0x1C661503, 0xEE0D9600, 0xFD5D65F4, 0x0F36E6F7, - 0x61C69362, 0x93AD1061, 0x80FDE395, 0x72966096, - 0xA65C047D, 0x5437877E, 0x4767748A, 0xB50CF789, - 0xEB1FCBAD, 0x197448AE, 0x0A24BB5A, 0xF84F3859, - 0x2C855CB2, 0xDEEEDFB1, 0xCDBE2C45, 0x3FD5AF46, - 0x7198540D, 0x83F3D70E, 0x90A324FA, 0x62C8A7F9, - 0xB602C312, 0x44694011, 0x5739B3E5, 0xA55230E6, - 0xFB410CC2, 0x092A8FC1, 0x1A7A7C35, 0xE811FF36, - 0x3CDB9BDD, 0xCEB018DE, 0xDDE0EB2A, 0x2F8B6829, - 0x82F63B78, 0x709DB87B, 0x63CD4B8F, 0x91A6C88C, - 0x456CAC67, 0xB7072F64, 0xA457DC90, 0x563C5F93, - 0x082F63B7, 0xFA44E0B4, 0xE9141340, 0x1B7F9043, - 0xCFB5F4A8, 0x3DDE77AB, 0x2E8E845F, 0xDCE5075C, - 0x92A8FC17, 0x60C37F14, 0x73938CE0, 0x81F80FE3, - 0x55326B08, 0xA759E80B, 0xB4091BFF, 0x466298FC, - 0x1871A4D8, 0xEA1A27DB, 0xF94AD42F, 0x0B21572C, - 0xDFEB33C7, 0x2D80B0C4, 0x3ED04330, 0xCCBBC033, - 0xA24BB5A6, 0x502036A5, 0x4370C551, 0xB11B4652, - 0x65D122B9, 0x97BAA1BA, 0x84EA524E, 0x7681D14D, - 0x2892ED69, 0xDAF96E6A, 0xC9A99D9E, 0x3BC21E9D, - 0xEF087A76, 0x1D63F975, 0x0E330A81, 0xFC588982, - 0xB21572C9, 0x407EF1CA, 0x532E023E, 0xA145813D, - 0x758FE5D6, 0x87E466D5, 0x94B49521, 0x66DF1622, - 0x38CC2A06, 0xCAA7A905, 0xD9F75AF1, 0x2B9CD9F2, - 0xFF56BD19, 0x0D3D3E1A, 0x1E6DCDEE, 0xEC064EED, - 0xC38D26C4, 0x31E6A5C7, 0x22B65633, 0xD0DDD530, - 0x0417B1DB, 0xF67C32D8, 0xE52CC12C, 0x1747422F, - 0x49547E0B, 0xBB3FFD08, 0xA86F0EFC, 0x5A048DFF, - 0x8ECEE914, 0x7CA56A17, 0x6FF599E3, 0x9D9E1AE0, - 0xD3D3E1AB, 0x21B862A8, 0x32E8915C, 0xC083125F, - 0x144976B4, 0xE622F5B7, 0xF5720643, 0x07198540, - 0x590AB964, 0xAB613A67, 0xB831C993, 0x4A5A4A90, - 0x9E902E7B, 0x6CFBAD78, 0x7FAB5E8C, 0x8DC0DD8F, - 0xE330A81A, 0x115B2B19, 0x020BD8ED, 0xF0605BEE, - 0x24AA3F05, 0xD6C1BC06, 0xC5914FF2, 0x37FACCF1, - 0x69E9F0D5, 0x9B8273D6, 0x88D28022, 0x7AB90321, - 0xAE7367CA, 0x5C18E4C9, 0x4F48173D, 0xBD23943E, - 0xF36E6F75, 0x0105EC76, 0x12551F82, 0xE03E9C81, - 0x34F4F86A, 0xC69F7B69, 0xD5CF889D, 0x27A40B9E, - 0x79B737BA, 0x8BDCB4B9, 0x988C474D, 0x6AE7C44E, - 0xBE2DA0A5, 0x4C4623A6, 0x5F16D052, 0xAD7D5351 -}}; +constexpr CRC32Table castagnoli_table{ + {0x00000000, 0xF26B8303, 0xE13B70F7, 0x1350F3F4, + 0xC79A971F, 0x35F1141C, 0x26A1E7E8, 0xD4CA64EB, + 0x8AD958CF, 0x78B2DBCC, 0x6BE22838, 0x9989AB3B, + 0x4D43CFD0, 0xBF284CD3, 0xAC78BF27, 0x5E133C24, + 0x105EC76F, 0xE235446C, 0xF165B798, 0x030E349B, + 0xD7C45070, 0x25AFD373, 0x36FF2087, 0xC494A384, + 0x9A879FA0, 0x68EC1CA3, 0x7BBCEF57, 0x89D76C54, + 0x5D1D08BF, 0xAF768BBC, 0xBC267848, 0x4E4DFB4B, + 0x20BD8EDE, 0xD2D60DDD, 0xC186FE29, 0x33ED7D2A, + 0xE72719C1, 0x154C9AC2, 0x061C6936, 0xF477EA35, + 0xAA64D611, 0x580F5512, 0x4B5FA6E6, 0xB93425E5, + 0x6DFE410E, 0x9F95C20D, 0x8CC531F9, 0x7EAEB2FA, + 0x30E349B1, 0xC288CAB2, 0xD1D83946, 0x23B3BA45, + 0xF779DEAE, 0x05125DAD, 0x1642AE59, 0xE4292D5A, + 0xBA3A117E, 0x4851927D, 0x5B016189, 0xA96AE28A, + 0x7DA08661, 0x8FCB0562, 0x9C9BF696, 0x6EF07595, + 0x417B1DBC, 0xB3109EBF, 0xA0406D4B, 0x522BEE48, + 0x86E18AA3, 0x748A09A0, 0x67DAFA54, 0x95B17957, + 0xCBA24573, 0x39C9C670, 0x2A993584, 0xD8F2B687, + 0x0C38D26C, 0xFE53516F, 0xED03A29B, 0x1F682198, + 0x5125DAD3, 0xA34E59D0, 0xB01EAA24, 0x42752927, + 0x96BF4DCC, 0x64D4CECF, 0x77843D3B, 0x85EFBE38, + 0xDBFC821C, 0x2997011F, 0x3AC7F2EB, 0xC8AC71E8, + 0x1C661503, 0xEE0D9600, 0xFD5D65F4, 0x0F36E6F7, + 0x61C69362, 0x93AD1061, 0x80FDE395, 0x72966096, + 0xA65C047D, 0x5437877E, 0x4767748A, 0xB50CF789, + 0xEB1FCBAD, 0x197448AE, 0x0A24BB5A, 0xF84F3859, + 0x2C855CB2, 0xDEEEDFB1, 0xCDBE2C45, 0x3FD5AF46, + 0x7198540D, 0x83F3D70E, 0x90A324FA, 0x62C8A7F9, + 0xB602C312, 0x44694011, 0x5739B3E5, 0xA55230E6, + 0xFB410CC2, 0x092A8FC1, 0x1A7A7C35, 0xE811FF36, + 0x3CDB9BDD, 0xCEB018DE, 0xDDE0EB2A, 0x2F8B6829, + 0x82F63B78, 0x709DB87B, 0x63CD4B8F, 0x91A6C88C, + 0x456CAC67, 0xB7072F64, 0xA457DC90, 0x563C5F93, + 0x082F63B7, 0xFA44E0B4, 0xE9141340, 0x1B7F9043, + 0xCFB5F4A8, 0x3DDE77AB, 0x2E8E845F, 0xDCE5075C, + 0x92A8FC17, 0x60C37F14, 0x73938CE0, 0x81F80FE3, + 0x55326B08, 0xA759E80B, 0xB4091BFF, 0x466298FC, + 0x1871A4D8, 0xEA1A27DB, 0xF94AD42F, 0x0B21572C, + 0xDFEB33C7, 0x2D80B0C4, 0x3ED04330, 0xCCBBC033, + 0xA24BB5A6, 0x502036A5, 0x4370C551, 0xB11B4652, + 0x65D122B9, 0x97BAA1BA, 0x84EA524E, 0x7681D14D, + 0x2892ED69, 0xDAF96E6A, 0xC9A99D9E, 0x3BC21E9D, + 0xEF087A76, 0x1D63F975, 0x0E330A81, 0xFC588982, + 0xB21572C9, 0x407EF1CA, 0x532E023E, 0xA145813D, + 0x758FE5D6, 0x87E466D5, 0x94B49521, 0x66DF1622, + 0x38CC2A06, 0xCAA7A905, 0xD9F75AF1, 0x2B9CD9F2, + 0xFF56BD19, 0x0D3D3E1A, 0x1E6DCDEE, 0xEC064EED, + 0xC38D26C4, 0x31E6A5C7, 0x22B65633, 0xD0DDD530, + 0x0417B1DB, 0xF67C32D8, 0xE52CC12C, 0x1747422F, + 0x49547E0B, 0xBB3FFD08, 0xA86F0EFC, 0x5A048DFF, + 0x8ECEE914, 0x7CA56A17, 0x6FF599E3, 0x9D9E1AE0, + 0xD3D3E1AB, 0x21B862A8, 0x32E8915C, 0xC083125F, + 0x144976B4, 0xE622F5B7, 0xF5720643, 0x07198540, + 0x590AB964, 0xAB613A67, 0xB831C993, 0x4A5A4A90, + 0x9E902E7B, 0x6CFBAD78, 0x7FAB5E8C, 0x8DC0DD8F, + 0xE330A81A, 0x115B2B19, 0x020BD8ED, 0xF0605BEE, + 0x24AA3F05, 0xD6C1BC06, 0xC5914FF2, 0x37FACCF1, + 0x69E9F0D5, 0x9B8273D6, 0x88D28022, 0x7AB90321, + 0xAE7367CA, 0x5C18E4C9, 0x4F48173D, 0xBD23943E, + 0xF36E6F75, 0x0105EC76, 0x12551F82, 0xE03E9C81, + 0x34F4F86A, 0xC69F7B69, 0xD5CF889D, 0x27A40B9E, + 0x79B737BA, 0x8BDCB4B9, 0x988C474D, 0x6AE7C44E, + 0xBE2DA0A5, 0x4C4623A6, 0x5F16D052, 0xAD7D5351}}; // CRC32 algorithm that uses polynomial 0x04C11DB7 -constexpr CRC32Table iso_table{{ - 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, - 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3, - 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, - 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, - 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE, - 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7, - 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, - 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5, - 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, - 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, - 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940, - 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59, - 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, - 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F, - 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, - 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, - 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A, - 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433, - 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, - 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01, - 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, - 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, - 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C, - 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65, - 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, - 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB, - 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, - 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, - 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086, - 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F, - 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, - 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD, - 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, - 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, - 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8, - 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1, - 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, - 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7, - 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, - 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, - 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252, - 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B, - 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, - 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79, - 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, - 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, - 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04, - 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D, - 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, - 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713, - 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, - 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, - 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E, - 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777, - 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, - 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45, - 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, - 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, - 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0, - 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9, - 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, - 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF, - 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, - 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D -}}; +constexpr CRC32Table iso_table{ + {0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3, + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE, + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7, + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5, + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940, + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59, + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F, + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A, + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433, + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01, + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C, + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65, + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB, + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086, + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F, + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD, + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8, + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1, + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7, + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252, + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B, + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79, + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04, + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D, + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713, + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E, + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777, + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45, + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0, + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9, + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF, + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D}}; static u32 ComputeCRC32(const CRC32Table& table, u32 crc, const u64 value, int length) { const auto* data = reinterpret_cast(&value); @@ -166,4 +165,4 @@ u32 ComputeCRC32ISO(u32 crc, u64 value, int length) { return ComputeCRC32(iso_table, crc, value, length); } -} // namespace Dynarmic::Common::Crypto::CRC32 +} // namespace Dynarmic::Common::Crypto::CRC32 diff --git a/src/dynarmic/common/crypto/crc32.h b/src/dynarmic/common/crypto/crc32.h index d56a9415..11f9233e 100644 --- a/src/dynarmic/common/crypto/crc32.h +++ b/src/dynarmic/common/crypto/crc32.h @@ -37,4 +37,4 @@ u32 ComputeCRC32Castagnoli(u32 crc, u64 value, int length); */ u32 ComputeCRC32ISO(u32 crc, u64 value, int length); -} // namespace Dynarmic::Common::Crypto::CRC32 +} // namespace Dynarmic::Common::Crypto::CRC32 diff --git a/src/dynarmic/common/crypto/sm4.cpp b/src/dynarmic/common/crypto/sm4.cpp index 6407ead7..c101634a 100644 --- a/src/dynarmic/common/crypto/sm4.cpp +++ b/src/dynarmic/common/crypto/sm4.cpp @@ -3,52 +3,52 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/common/crypto/sm4.h" + #include #include "dynarmic/common/common_types.h" -#include "dynarmic/common/crypto/sm4.h" namespace Dynarmic::Common::Crypto::SM4 { using SubstitutionTable = std::array; -constexpr SubstitutionTable substitution_box{{ - 0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, - 0x16, 0xB6, 0x14, 0xC2, 0x28, 0xFB, 0x2C, 0x05, - 0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, - 0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99, - 0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, 0x7A, - 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62, - 0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, - 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6, - 0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, - 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8, - 0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, - 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35, - 0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, - 0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87, - 0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, - 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E, - 0xEA, 0xBF, 0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, - 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1, - 0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, - 0xAD, 0x93, 0x32, 0x30, 0xF5, 0x8C, 0xB1, 0xE3, - 0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, - 0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F, - 0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, 0x8E, 0x2F, - 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51, - 0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, - 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8, - 0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, - 0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0, - 0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, - 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84, - 0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, - 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48 -}}; +constexpr SubstitutionTable substitution_box{ + {0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, + 0x16, 0xB6, 0x14, 0xC2, 0x28, 0xFB, 0x2C, 0x05, + 0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, + 0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99, + 0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, 0x7A, + 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62, + 0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, + 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6, + 0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, + 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8, + 0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, + 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35, + 0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, + 0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87, + 0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, + 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E, + 0xEA, 0xBF, 0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, + 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1, + 0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, + 0xAD, 0x93, 0x32, 0x30, 0xF5, 0x8C, 0xB1, 0xE3, + 0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, + 0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F, + 0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, 0x8E, 0x2F, + 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51, + 0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, + 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8, + 0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, + 0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0, + 0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, + 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84, + 0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, + 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48}}; u8 AccessSubstitutionBox(u8 index) { return substitution_box[index]; } -} // namespace Dynarmic::Common::Crypto::SM4 +} // namespace Dynarmic::Common::Crypto::SM4 diff --git a/src/dynarmic/common/crypto/sm4.h b/src/dynarmic/common/crypto/sm4.h index d764614a..2444ed28 100644 --- a/src/dynarmic/common/crypto/sm4.h +++ b/src/dynarmic/common/crypto/sm4.h @@ -11,4 +11,4 @@ namespace Dynarmic::Common::Crypto::SM4 { u8 AccessSubstitutionBox(u8 index); -} // namespace Dynarmic::Common::Crypto::SM4 +} // namespace Dynarmic::Common::Crypto::SM4 diff --git a/src/dynarmic/common/fp/fpcr.h b/src/dynarmic/common/fp/fpcr.h index 701e6a9e..8a1b0d73 100644 --- a/src/dynarmic/common/fp/fpcr.h +++ b/src/dynarmic/common/fp/fpcr.h @@ -22,7 +22,8 @@ public: FPCR() = default; FPCR(const FPCR&) = default; FPCR(FPCR&&) = default; - explicit FPCR(u32 data) : value{data & mask} {} + explicit FPCR(u32 data) + : value{data & mask} {} FPCR& operator=(const FPCR&) = default; FPCR& operator=(FPCR&&) = default; @@ -204,4 +205,4 @@ inline bool operator!=(FPCR lhs, FPCR rhs) { return !operator==(lhs, rhs); } -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/fpsr.h b/src/dynarmic/common/fp/fpsr.h index 4cf114a9..1accf872 100644 --- a/src/dynarmic/common/fp/fpsr.h +++ b/src/dynarmic/common/fp/fpsr.h @@ -18,7 +18,8 @@ public: FPSR() = default; FPSR(const FPSR&) = default; FPSR(FPSR&&) = default; - explicit FPSR(u32 data) : value{data & mask} {} + explicit FPSR(u32 data) + : value{data & mask} {} FPSR& operator=(const FPSR&) = default; FPSR& operator=(FPSR&&) = default; @@ -156,4 +157,4 @@ inline bool operator!=(FPSR lhs, FPSR rhs) { return !operator==(lhs, rhs); } -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/fused.cpp b/src/dynarmic/common/fp/fused.cpp index 50d48606..2f3ccacb 100644 --- a/src/dynarmic/common/fp/fused.cpp +++ b/src/dynarmic/common/fp/fused.cpp @@ -4,6 +4,7 @@ */ #include "dynarmic/common/fp/fused.h" + #include "dynarmic/common/fp/mantissa_util.h" #include "dynarmic/common/fp/unpacked.h" #include "dynarmic/common/u128.h" @@ -20,7 +21,7 @@ static FPUnpacked ReduceMantissa(bool sign, int exponent, const u128& mantissa) FPUnpacked FusedMulAdd(FPUnpacked addend, FPUnpacked op1, FPUnpacked op2) { const bool product_sign = op1.sign != op2.sign; - const auto [product_exponent, product_value] = [op1, op2]{ + const auto [product_exponent, product_value] = [op1, op2] { int exponent = op1.exponent + op2.exponent; u128 value = Multiply64To128(op1.mantissa, op2.mantissa); if (value.Bit()) { @@ -86,4 +87,4 @@ FPUnpacked FusedMulAdd(FPUnpacked addend, FPUnpacked op1, FPUnpacked op2) { return ReduceMantissa(result_sign, result_exponent, result); } -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/fused.h b/src/dynarmic/common/fp/fused.h index a365d636..0ffa2683 100644 --- a/src/dynarmic/common/fp/fused.h +++ b/src/dynarmic/common/fp/fused.h @@ -12,4 +12,4 @@ struct FPUnpacked; /// This function assumes all arguments have been normalized. FPUnpacked FusedMulAdd(FPUnpacked addend, FPUnpacked op1, FPUnpacked op2); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/info.h b/src/dynarmic/common/fp/info.h index da928e0f..f5a7b57f 100644 --- a/src/dynarmic/common/fp/info.h +++ b/src/dynarmic/common/fp/info.h @@ -135,4 +135,4 @@ constexpr FPT FPValue() { return FPT(FPInfo::Zero(sign) | mantissa | (biased_exponent << FPInfo::explicit_mantissa_width)); } -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/mantissa_util.h b/src/dynarmic/common/fp/mantissa_util.h index aa3e058d..a2fe7c21 100644 --- a/src/dynarmic/common/fp/mantissa_util.h +++ b/src/dynarmic/common/fp/mantissa_util.h @@ -43,4 +43,4 @@ inline ResidualError ResidualErrorOnRightShift(u64 mantissa, int shift_amount) { return ResidualError::GreaterThanHalf; } -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op.h b/src/dynarmic/common/fp/op.h index e5736e44..b30ff39c 100644 --- a/src/dynarmic/common/fp/op.h +++ b/src/dynarmic/common/fp/op.h @@ -8,10 +8,10 @@ #include "dynarmic/common/fp/op/FPCompare.h" #include "dynarmic/common/fp/op/FPConvert.h" #include "dynarmic/common/fp/op/FPMulAdd.h" +#include "dynarmic/common/fp/op/FPRSqrtEstimate.h" +#include "dynarmic/common/fp/op/FPRSqrtStepFused.h" #include "dynarmic/common/fp/op/FPRecipEstimate.h" #include "dynarmic/common/fp/op/FPRecipExponent.h" #include "dynarmic/common/fp/op/FPRecipStepFused.h" #include "dynarmic/common/fp/op/FPRoundInt.h" -#include "dynarmic/common/fp/op/FPRSqrtEstimate.h" -#include "dynarmic/common/fp/op/FPRSqrtStepFused.h" #include "dynarmic/common/fp/op/FPToFixed.h" diff --git a/src/dynarmic/common/fp/op/FPCompare.cpp b/src/dynarmic/common/fp/op/FPCompare.cpp index 20323847..8aeaadc5 100644 --- a/src/dynarmic/common/fp/op/FPCompare.cpp +++ b/src/dynarmic/common/fp/op/FPCompare.cpp @@ -3,15 +3,16 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/common/fp/op/FPCompare.h" + #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" -#include "dynarmic/common/fp/op/FPCompare.h" #include "dynarmic/common/fp/process_exception.h" #include "dynarmic/common/fp/unpacked.h" namespace Dynarmic::FP { -template +template bool FPCompareEQ(FPT lhs, FPT rhs, FPCR fpcr, FPSR& fpsr) { const auto unpacked1 = FPUnpack(lhs, fpcr, fpsr); const auto unpacked2 = FPUnpack(rhs, fpcr, fpsr); @@ -20,8 +21,7 @@ bool FPCompareEQ(FPT lhs, FPT rhs, FPCR fpcr, FPSR& fpsr) { const auto& value1 = std::get(unpacked1); const auto& value2 = std::get(unpacked2); - if (type1 == FPType::QNaN || type1 == FPType::SNaN || - type2 == FPType::QNaN || type2 == FPType::SNaN) { + if (type1 == FPType::QNaN || type1 == FPType::SNaN || type2 == FPType::QNaN || type2 == FPType::SNaN) { if (type1 == FPType::SNaN || type2 == FPType::SNaN) { FPProcessException(FPExc::InvalidOp, fpcr, fpsr); } @@ -37,4 +37,4 @@ template bool FPCompareEQ(u16 lhs, u16 rhs, FPCR fpcr, FPSR& fpsr); template bool FPCompareEQ(u32 lhs, u32 rhs, FPCR fpcr, FPSR& fpsr); template bool FPCompareEQ(u64 lhs, u64 rhs, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPCompare.h b/src/dynarmic/common/fp/op/FPCompare.h index 1a68c6b0..e0d5ca03 100644 --- a/src/dynarmic/common/fp/op/FPCompare.h +++ b/src/dynarmic/common/fp/op/FPCompare.h @@ -10,7 +10,7 @@ namespace Dynarmic::FP { class FPCR; class FPSR; -template +template bool FPCompareEQ(FPT lhs, FPT rhs, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPConvert.cpp b/src/dynarmic/common/fp/op/FPConvert.cpp index e3392eaf..8d01e524 100644 --- a/src/dynarmic/common/fp/op/FPConvert.cpp +++ b/src/dynarmic/common/fp/op/FPConvert.cpp @@ -3,17 +3,18 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/common/fp/op/FPConvert.h" + #include "dynarmic/common/common_types.h" #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/info.h" -#include "dynarmic/common/fp/op/FPConvert.h" #include "dynarmic/common/fp/process_exception.h" #include "dynarmic/common/fp/unpacked.h" namespace Dynarmic::FP { namespace { -template +template FPT_TO FPConvertNaN(FPT_FROM op) { const bool sign = Common::Bit() - 1>(op); const u64 frac = [op] { @@ -38,9 +39,9 @@ FPT_TO FPConvertNaN(FPT_FROM op) { return FPT_TO(shifted_sign | exponent << 9 | Common::Bits<42, 50>(frac)); } } -} // Anonymous namespace +} // Anonymous namespace -template +template FPT_TO FPConvert(FPT_FROM op, FPCR fpcr, RoundingMode rounding_mode, FPSR& fpsr) { const auto [type, sign, value] = FPUnpackCV(op, fpcr, fpsr); const bool is_althp = Common::BitSize() == 16 && fpcr.AHP(); @@ -86,4 +87,4 @@ template u32 FPConvert(u64 op, FPCR fpcr, RoundingMode rounding_mode, template u64 FPConvert(u16 op, FPCR fpcr, RoundingMode rounding_mode, FPSR& fpsr); template u64 FPConvert(u32 op, FPCR fpcr, RoundingMode rounding_mode, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPConvert.h b/src/dynarmic/common/fp/op/FPConvert.h index ad0b048b..0fea22e4 100644 --- a/src/dynarmic/common/fp/op/FPConvert.h +++ b/src/dynarmic/common/fp/op/FPConvert.h @@ -11,7 +11,7 @@ class FPCR; class FPSR; enum class RoundingMode; -template +template FPT_TO FPConvert(FPT_FROM op, FPCR fpcr, RoundingMode rounding_mode, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPMulAdd.cpp b/src/dynarmic/common/fp/op/FPMulAdd.cpp index c06e9c8d..409b750b 100644 --- a/src/dynarmic/common/fp/op/FPMulAdd.cpp +++ b/src/dynarmic/common/fp/op/FPMulAdd.cpp @@ -3,12 +3,13 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/common/fp/op/FPMulAdd.h" + #include "dynarmic/common/common_types.h" #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" -#include "dynarmic/common/fp/info.h" #include "dynarmic/common/fp/fused.h" -#include "dynarmic/common/fp/op/FPMulAdd.h" +#include "dynarmic/common/fp/info.h" #include "dynarmic/common/fp/process_exception.h" #include "dynarmic/common/fp/process_nan.h" #include "dynarmic/common/fp/unpacked.h" @@ -76,4 +77,4 @@ template u16 FPMulAdd(u16 addend, u16 op1, u16 op2, FPCR fpcr, FPSR& fpsr); template u32 FPMulAdd(u32 addend, u32 op1, u32 op2, FPCR fpcr, FPSR& fpsr); template u64 FPMulAdd(u64 addend, u64 op1, u64 op2, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPMulAdd.h b/src/dynarmic/common/fp/op/FPMulAdd.h index bd5638dd..774fe88b 100644 --- a/src/dynarmic/common/fp/op/FPMulAdd.h +++ b/src/dynarmic/common/fp/op/FPMulAdd.h @@ -13,4 +13,4 @@ class FPSR; template FPT FPMulAdd(FPT addend, FPT op1, FPT op2, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPNeg.h b/src/dynarmic/common/fp/op/FPNeg.h index c30079d2..4f172a59 100644 --- a/src/dynarmic/common/fp/op/FPNeg.h +++ b/src/dynarmic/common/fp/op/FPNeg.h @@ -14,4 +14,4 @@ constexpr FPT FPNeg(FPT op) { return op ^ FPInfo::sign_mask; } -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp b/src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp index 367a94c1..4f547e9d 100644 --- a/src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp +++ b/src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp @@ -3,11 +3,12 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/common/fp/op/FPRSqrtEstimate.h" + #include "dynarmic/common/common_types.h" #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/info.h" -#include "dynarmic/common/fp/op/FPRSqrtEstimate.h" #include "dynarmic/common/fp/process_exception.h" #include "dynarmic/common/fp/process_nan.h" #include "dynarmic/common/fp/unpacked.h" @@ -54,4 +55,4 @@ template u16 FPRSqrtEstimate(u16 op, FPCR fpcr, FPSR& fpsr); template u32 FPRSqrtEstimate(u32 op, FPCR fpcr, FPSR& fpsr); template u64 FPRSqrtEstimate(u64 op, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPRSqrtEstimate.h b/src/dynarmic/common/fp/op/FPRSqrtEstimate.h index e7f8cfc3..f51be1e8 100644 --- a/src/dynarmic/common/fp/op/FPRSqrtEstimate.h +++ b/src/dynarmic/common/fp/op/FPRSqrtEstimate.h @@ -13,4 +13,4 @@ class FPSR; template FPT FPRSqrtEstimate(FPT op, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPRSqrtStepFused.cpp b/src/dynarmic/common/fp/op/FPRSqrtStepFused.cpp index 4f7421e0..06fe96d4 100644 --- a/src/dynarmic/common/fp/op/FPRSqrtStepFused.cpp +++ b/src/dynarmic/common/fp/op/FPRSqrtStepFused.cpp @@ -3,12 +3,13 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/common/fp/op/FPRSqrtStepFused.h" + #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/fused.h" #include "dynarmic/common/fp/info.h" #include "dynarmic/common/fp/op/FPNeg.h" -#include "dynarmic/common/fp/op/FPRSqrtStepFused.h" #include "dynarmic/common/fp/process_nan.h" #include "dynarmic/common/fp/unpacked.h" @@ -53,4 +54,4 @@ template u16 FPRSqrtStepFused(u16 op1, u16 op2, FPCR fpcr, FPSR& fpsr); template u32 FPRSqrtStepFused(u32 op1, u32 op2, FPCR fpcr, FPSR& fpsr); template u64 FPRSqrtStepFused(u64 op1, u64 op2, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPRSqrtStepFused.h b/src/dynarmic/common/fp/op/FPRSqrtStepFused.h index d425447f..384a7592 100644 --- a/src/dynarmic/common/fp/op/FPRSqrtStepFused.h +++ b/src/dynarmic/common/fp/op/FPRSqrtStepFused.h @@ -13,4 +13,4 @@ class FPSR; template FPT FPRSqrtStepFused(FPT op1, FPT op2, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPRecipEstimate.cpp b/src/dynarmic/common/fp/op/FPRecipEstimate.cpp index 1a3fe8fc..956c7819 100644 --- a/src/dynarmic/common/fp/op/FPRecipEstimate.cpp +++ b/src/dynarmic/common/fp/op/FPRecipEstimate.cpp @@ -3,6 +3,8 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/common/fp/op/FPRecipEstimate.h" + #include #include "dynarmic/common/assert.h" @@ -10,7 +12,6 @@ #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/info.h" -#include "dynarmic/common/fp/op/FPRecipEstimate.h" #include "dynarmic/common/fp/process_exception.h" #include "dynarmic/common/fp/process_nan.h" #include "dynarmic/common/fp/unpacked.h" @@ -39,7 +40,7 @@ FPT FPRecipEstimate(FPT op, FPCR fpcr, FPSR& fpsr) { } if (value.exponent < FPInfo::exponent_min - 2) { - const bool overflow_to_inf = [&]{ + const bool overflow_to_inf = [&] { switch (fpcr.RMode()) { case RoundingMode::ToNearest_TieEven: return true; @@ -95,4 +96,4 @@ template u16 FPRecipEstimate(u16 op, FPCR fpcr, FPSR& fpsr); template u32 FPRecipEstimate(u32 op, FPCR fpcr, FPSR& fpsr); template u64 FPRecipEstimate(u64 op, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPRecipEstimate.h b/src/dynarmic/common/fp/op/FPRecipEstimate.h index 26d6ec0f..eaf6fee5 100644 --- a/src/dynarmic/common/fp/op/FPRecipEstimate.h +++ b/src/dynarmic/common/fp/op/FPRecipEstimate.h @@ -13,4 +13,4 @@ class FPSR; template FPT FPRecipEstimate(FPT op, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPRecipExponent.cpp b/src/dynarmic/common/fp/op/FPRecipExponent.cpp index a101d5c3..7bbcb8cc 100644 --- a/src/dynarmic/common/fp/op/FPRecipExponent.cpp +++ b/src/dynarmic/common/fp/op/FPRecipExponent.cpp @@ -3,18 +3,19 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/common_types.h" +#include "dynarmic/common/fp/op/FPRecipExponent.h" + #include "dynarmic/common/bit_util.h" +#include "dynarmic/common/common_types.h" #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/info.h" -#include "dynarmic/common/fp/op/FPRecipExponent.h" #include "dynarmic/common/fp/process_nan.h" #include "dynarmic/common/fp/unpacked.h" namespace Dynarmic::FP { namespace { -template +template FPT DetermineExponentValue(size_t value) { if constexpr (sizeof(FPT) == sizeof(u32)) { return static_cast(Common::Bits<23, 30>(value)); @@ -24,9 +25,9 @@ FPT DetermineExponentValue(size_t value) { return static_cast(Common::Bits<10, 14>(value)); } } -} // Anonymous namespace +} // Anonymous namespace -template +template FPT FPRecipExponent(FPT op, FPCR fpcr, FPSR& fpsr) { const auto [type, sign, value] = FPUnpack(op, fpcr, fpsr); (void)value; @@ -54,4 +55,4 @@ template u16 FPRecipExponent(u16 op, FPCR fpcr, FPSR& fpsr); template u32 FPRecipExponent(u32 op, FPCR fpcr, FPSR& fpsr); template u64 FPRecipExponent(u64 op, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPRecipExponent.h b/src/dynarmic/common/fp/op/FPRecipExponent.h index e9af0603..63ff3530 100644 --- a/src/dynarmic/common/fp/op/FPRecipExponent.h +++ b/src/dynarmic/common/fp/op/FPRecipExponent.h @@ -10,7 +10,7 @@ namespace Dynarmic::FP { class FPCR; class FPSR; -template +template FPT FPRecipExponent(FPT op, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPRecipStepFused.cpp b/src/dynarmic/common/fp/op/FPRecipStepFused.cpp index 623e592f..b01477fe 100644 --- a/src/dynarmic/common/fp/op/FPRecipStepFused.cpp +++ b/src/dynarmic/common/fp/op/FPRecipStepFused.cpp @@ -3,12 +3,13 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/common/fp/op/FPRecipStepFused.h" + #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/fused.h" #include "dynarmic/common/fp/info.h" #include "dynarmic/common/fp/op/FPNeg.h" -#include "dynarmic/common/fp/op/FPRecipStepFused.h" #include "dynarmic/common/fp/process_nan.h" #include "dynarmic/common/fp/unpacked.h" @@ -52,4 +53,4 @@ template u16 FPRecipStepFused(u16 op1, u16 op2, FPCR fpcr, FPSR& fpsr); template u32 FPRecipStepFused(u32 op1, u32 op2, FPCR fpcr, FPSR& fpsr); template u64 FPRecipStepFused(u64 op1, u64 op2, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPRecipStepFused.h b/src/dynarmic/common/fp/op/FPRecipStepFused.h index 8892d03d..abe447b5 100644 --- a/src/dynarmic/common/fp/op/FPRecipStepFused.h +++ b/src/dynarmic/common/fp/op/FPRecipStepFused.h @@ -13,4 +13,4 @@ class FPSR; template FPT FPRecipStepFused(FPT op1, FPT op2, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPRoundInt.cpp b/src/dynarmic/common/fp/op/FPRoundInt.cpp index e94f2be6..6721228b 100644 --- a/src/dynarmic/common/fp/op/FPRoundInt.cpp +++ b/src/dynarmic/common/fp/op/FPRoundInt.cpp @@ -3,6 +3,8 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/common/fp/op/FPRoundInt.h" + #include "dynarmic/common/assert.h" #include "dynarmic/common/bit_util.h" #include "dynarmic/common/common_types.h" @@ -10,7 +12,6 @@ #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/info.h" #include "dynarmic/common/fp/mantissa_util.h" -#include "dynarmic/common/fp/op/FPRoundInt.h" #include "dynarmic/common/fp/process_exception.h" #include "dynarmic/common/fp/process_nan.h" #include "dynarmic/common/fp/rounding_mode.h" @@ -78,8 +79,8 @@ u64 FPRoundInt(FPT op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr) const u64 abs_int_result = new_sign ? Safe::Negate(int_result) : static_cast(int_result); const FPT result = int_result == 0 - ? FPInfo::Zero(sign) - : FPRound(FPUnpacked{new_sign, normalized_point_position, abs_int_result}, fpcr, RoundingMode::TowardsZero, fpsr); + ? FPInfo::Zero(sign) + : FPRound(FPUnpacked{new_sign, normalized_point_position, abs_int_result}, fpcr, RoundingMode::TowardsZero, fpsr); if (error != ResidualError::Zero && exact) { FPProcessException(FPExc::Inexact, fpcr, fpsr); @@ -92,4 +93,4 @@ template u64 FPRoundInt(u16 op, FPCR fpcr, RoundingMode rounding, bool exac template u64 FPRoundInt(u32 op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr); template u64 FPRoundInt(u64 op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPRoundInt.h b/src/dynarmic/common/fp/op/FPRoundInt.h index c070fdf4..e8d0609a 100644 --- a/src/dynarmic/common/fp/op/FPRoundInt.h +++ b/src/dynarmic/common/fp/op/FPRoundInt.h @@ -16,4 +16,4 @@ enum class RoundingMode; template u64 FPRoundInt(FPT op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPToFixed.cpp b/src/dynarmic/common/fp/op/FPToFixed.cpp index ae755e67..011ec4e8 100644 --- a/src/dynarmic/common/fp/op/FPToFixed.cpp +++ b/src/dynarmic/common/fp/op/FPToFixed.cpp @@ -3,13 +3,14 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/common/fp/op/FPToFixed.h" + #include "dynarmic/common/assert.h" #include "dynarmic/common/bit_util.h" #include "dynarmic/common/common_types.h" #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/mantissa_util.h" -#include "dynarmic/common/fp/op/FPToFixed.h" #include "dynarmic/common/fp/process_exception.h" #include "dynarmic/common/fp/rounding_mode.h" #include "dynarmic/common/fp/unpacked.h" @@ -98,4 +99,4 @@ template u64 FPToFixed(size_t ibits, u16 op, size_t fbits, bool unsigned_, template u64 FPToFixed(size_t ibits, u32 op, size_t fbits, bool unsigned_, FPCR fpcr, RoundingMode rounding, FPSR& fpsr); template u64 FPToFixed(size_t ibits, u64 op, size_t fbits, bool unsigned_, FPCR fpcr, RoundingMode rounding, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/op/FPToFixed.h b/src/dynarmic/common/fp/op/FPToFixed.h index b44587ae..e87565a4 100644 --- a/src/dynarmic/common/fp/op/FPToFixed.h +++ b/src/dynarmic/common/fp/op/FPToFixed.h @@ -16,4 +16,4 @@ enum class RoundingMode; template u64 FPToFixed(size_t ibits, FPT op, size_t fbits, bool unsigned_, FPCR fpcr, RoundingMode rounding, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/process_exception.cpp b/src/dynarmic/common/fp/process_exception.cpp index d427964e..a934118f 100644 --- a/src/dynarmic/common/fp/process_exception.cpp +++ b/src/dynarmic/common/fp/process_exception.cpp @@ -3,10 +3,11 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/common/fp/process_exception.h" + #include "dynarmic/common/assert.h" #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" -#include "dynarmic/common/fp/process_exception.h" namespace Dynarmic::FP { @@ -54,4 +55,4 @@ void FPProcessException(FPExc exception, FPCR fpcr, FPSR& fpsr) { } } -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/process_exception.h b/src/dynarmic/common/fp/process_exception.h index 0c8af1a2..436a9daa 100644 --- a/src/dynarmic/common/fp/process_exception.h +++ b/src/dynarmic/common/fp/process_exception.h @@ -21,4 +21,4 @@ enum class FPExc { void FPProcessException(FPExc exception, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/process_nan.cpp b/src/dynarmic/common/fp/process_nan.cpp index 71e5e348..0e2891dc 100644 --- a/src/dynarmic/common/fp/process_nan.cpp +++ b/src/dynarmic/common/fp/process_nan.cpp @@ -3,6 +3,8 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/common/fp/process_nan.h" + #include #include "dynarmic/common/assert.h" @@ -11,7 +13,6 @@ #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/info.h" #include "dynarmic/common/fp/process_exception.h" -#include "dynarmic/common/fp/process_nan.h" #include "dynarmic/common/fp/unpacked.h" namespace Dynarmic::FP { @@ -88,4 +89,4 @@ template std::optional FPProcessNaNs3(FPType type1, FPType type2, FPTy template std::optional FPProcessNaNs3(FPType type1, FPType type2, FPType type3, u32 op1, u32 op2, u32 op3, FPCR fpcr, FPSR& fpsr); template std::optional FPProcessNaNs3(FPType type1, FPType type2, FPType type3, u64 op1, u64 op2, u64 op3, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/process_nan.h b/src/dynarmic/common/fp/process_nan.h index ccf9cc5a..331b7943 100644 --- a/src/dynarmic/common/fp/process_nan.h +++ b/src/dynarmic/common/fp/process_nan.h @@ -22,4 +22,4 @@ std::optional FPProcessNaNs(FPType type1, FPType type2, FPT op1, FPT op2, F template std::optional FPProcessNaNs3(FPType type1, FPType type2, FPType type3, FPT op1, FPT op2, FPT op3, FPCR fpcr, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/rounding_mode.h b/src/dynarmic/common/fp/rounding_mode.h index 60c09563..fcf36f61 100644 --- a/src/dynarmic/common/fp/rounding_mode.h +++ b/src/dynarmic/common/fp/rounding_mode.h @@ -24,4 +24,4 @@ enum class RoundingMode { ToOdd, }; -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/unpacked.cpp b/src/dynarmic/common/fp/unpacked.cpp index 53bc1ead..3a0c6b32 100644 --- a/src/dynarmic/common/fp/unpacked.cpp +++ b/src/dynarmic/common/fp/unpacked.cpp @@ -3,12 +3,13 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/common/fp/unpacked.h" + #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/info.h" #include "dynarmic/common/fp/mantissa_util.h" #include "dynarmic/common/fp/process_exception.h" #include "dynarmic/common/fp/rounding_mode.h" -#include "dynarmic/common/fp/unpacked.h" #include "dynarmic/common/safe_ops.h" namespace Dynarmic::FP { @@ -143,12 +144,12 @@ FPT FPRoundBase(FPUnpacked op, FPCR fpcr, RoundingMode rounding, FPSR& fpsr) { FPT result = 0; #ifdef _MSC_VER -#pragma warning(push) -#pragma warning(disable:4127) // C4127: conditional expression is constant +# pragma warning(push) +# pragma warning(disable : 4127) // C4127: conditional expression is constant #endif if (!isFP16 || !fpcr.AHP()) { #ifdef _MSC_VER -#pragma warning(pop) +# pragma warning(pop) #endif constexpr int max_biased_exp = (1 << E) - 1; if (biased_exp >= max_biased_exp) { @@ -188,4 +189,4 @@ template u16 FPRoundBase(FPUnpacked op, FPCR fpcr, RoundingMode rounding, F template u32 FPRoundBase(FPUnpacked op, FPCR fpcr, RoundingMode rounding, FPSR& fpsr); template u64 FPRoundBase(FPUnpacked op, FPCR fpcr, RoundingMode rounding, FPSR& fpsr); -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/unpacked.h b/src/dynarmic/common/fp/unpacked.h index 4431a637..e77c87a5 100644 --- a/src/dynarmic/common/fp/unpacked.h +++ b/src/dynarmic/common/fp/unpacked.h @@ -85,4 +85,4 @@ FPT FPRound(FPUnpacked op, FPCR fpcr, FPSR& fpsr) { return FPRound(op, fpcr, fpcr.RMode(), fpsr); } -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/fp/util.h b/src/dynarmic/common/fp/util.h index c21f6ef8..fda34e3e 100644 --- a/src/dynarmic/common/fp/util.h +++ b/src/dynarmic/common/fp/util.h @@ -96,4 +96,4 @@ constexpr std::optional ProcessNaNs(FPT a, FPT b, FPT c) { return std::nullopt; } -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP diff --git a/src/dynarmic/common/intrusive_list.h b/src/dynarmic/common/intrusive_list.h index ea27a5ac..7ee8e439 100644 --- a/src/dynarmic/common/intrusive_list.h +++ b/src/dynarmic/common/intrusive_list.h @@ -14,10 +14,12 @@ namespace Dynarmic::Common { -template class IntrusiveList; -template class IntrusiveListIterator; +template +class IntrusiveList; +template +class IntrusiveListIterator; -template +template class IntrusiveListNode { public: bool IsSentinel() const { @@ -34,9 +36,8 @@ protected: friend class IntrusiveListIterator; }; -template -class IntrusiveListSentinel final : public IntrusiveListNode -{ +template +class IntrusiveListSentinel final : public IntrusiveListNode { using IntrusiveListNode::next; using IntrusiveListNode::prev; using IntrusiveListNode::is_sentinel; @@ -49,33 +50,36 @@ public: } }; -template +template class IntrusiveListIterator { public: using iterator_category = std::bidirectional_iterator_tag; - using difference_type = std::ptrdiff_t; - using value_type = T; - using pointer = value_type*; - using const_pointer = const value_type*; - using reference = value_type&; - using const_reference = const value_type&; + using difference_type = std::ptrdiff_t; + using value_type = T; + using pointer = value_type*; + using const_pointer = const value_type*; + using reference = value_type&; + using const_reference = const value_type&; // If value_type is const, we want "const IntrusiveListNode", not "const IntrusiveListNode" - using node_type = std::conditional_t::value, - const IntrusiveListNode>, - IntrusiveListNode>; - using node_pointer = node_type*; - using node_reference = node_type&; + using node_type = std::conditional_t::value, + const IntrusiveListNode>, + IntrusiveListNode>; + using node_pointer = node_type*; + using node_reference = node_type&; IntrusiveListIterator() = default; IntrusiveListIterator(const IntrusiveListIterator& other) = default; IntrusiveListIterator& operator=(const IntrusiveListIterator& other) = default; - explicit IntrusiveListIterator(node_pointer list_node) : node(list_node) { + explicit IntrusiveListIterator(node_pointer list_node) + : node(list_node) { } - explicit IntrusiveListIterator(pointer data) : node(data) { + explicit IntrusiveListIterator(pointer data) + : node(data) { } - explicit IntrusiveListIterator(reference data) : node(&data) { + explicit IntrusiveListIterator(reference data) + : node(&data) { } IntrusiveListIterator& operator++() { @@ -121,19 +125,19 @@ private: node_pointer node = nullptr; }; -template +template class IntrusiveList { public: - using difference_type = std::ptrdiff_t; - using size_type = std::size_t; - using value_type = T; - using pointer = value_type*; - using const_pointer = const value_type*; - using reference = value_type&; - using const_reference = const value_type&; - using iterator = IntrusiveListIterator; - using const_iterator = IntrusiveListIterator; - using reverse_iterator = std::reverse_iterator; + using difference_type = std::ptrdiff_t; + using size_type = std::size_t; + using value_type = T; + using pointer = value_type*; + using const_pointer = const value_type*; + using reference = value_type&; + using const_reference = const value_type&; + using iterator = IntrusiveListIterator; + using const_iterator = IntrusiveListIterator; + using reverse_iterator = std::reverse_iterator; using const_reverse_iterator = std::reverse_iterator; /** @@ -222,10 +226,10 @@ public: node->prev->next = node->next; node->next->prev = node->prev; - #if !defined(NDEBUG) +#if !defined(NDEBUG) node->next = nullptr; node->prev = nullptr; - #endif +#endif return node; } @@ -308,21 +312,21 @@ public: } // Iterator interface - iterator begin() { return iterator(root->next); } - const_iterator begin() const { return const_iterator(root->next); } - const_iterator cbegin() const { return begin(); } + iterator begin() { return iterator(root->next); } + const_iterator begin() const { return const_iterator(root->next); } + const_iterator cbegin() const { return begin(); } - iterator end() { return iterator(root.get()); } - const_iterator end() const { return const_iterator(root.get()); } - const_iterator cend() const { return end(); } + iterator end() { return iterator(root.get()); } + const_iterator end() const { return const_iterator(root.get()); } + const_iterator cend() const { return end(); } - reverse_iterator rbegin() { return reverse_iterator(end()); } - const_reverse_iterator rbegin() const { return const_reverse_iterator(end()); } - const_reverse_iterator crbegin() const { return rbegin(); } + reverse_iterator rbegin() { return reverse_iterator(end()); } + const_reverse_iterator rbegin() const { return const_reverse_iterator(end()); } + const_reverse_iterator crbegin() const { return rbegin(); } - reverse_iterator rend() { return reverse_iterator(begin()); } - const_reverse_iterator rend() const { return const_reverse_iterator(begin()); } - const_reverse_iterator crend() const { return rend(); } + reverse_iterator rend() { return reverse_iterator(begin()); } + const_reverse_iterator rend() const { return const_reverse_iterator(begin()); } + const_reverse_iterator crend() const { return rend(); } /** * Erases a node from the list, indicated by an iterator. @@ -367,9 +371,9 @@ private: * @param lhs The first list. * @param rhs The second list. */ -template +template void swap(IntrusiveList& lhs, IntrusiveList& rhs) noexcept { lhs.swap(rhs); } -} // namespace Dynarmic::Common +} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/iterator_util.h b/src/dynarmic/common/iterator_util.h index 82ba3b55..982f5313 100644 --- a/src/dynarmic/common/iterator_util.h +++ b/src/dynarmic/common/iterator_util.h @@ -25,11 +25,11 @@ struct ReverseAdapter { } }; -} // namespace detail +} // namespace detail template constexpr detail::ReverseAdapter Reverse(T&& iterable) { return detail::ReverseAdapter{iterable}; } -} // namespace Dynarmic::Common +} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/llvm_disassemble.cpp b/src/dynarmic/common/llvm_disassemble.cpp index 9e942a74..ef02d601 100644 --- a/src/dynarmic/common/llvm_disassemble.cpp +++ b/src/dynarmic/common/llvm_disassemble.cpp @@ -8,8 +8,8 @@ #include #ifdef DYNARMIC_USE_LLVM -#include -#include +# include +# include #endif #include "dynarmic/common/assert.h" @@ -79,8 +79,10 @@ std::string DisassembleAArch32([[maybe_unused]] bool is_thumb, [[maybe_unused]] result += inst_size > 0 ? buffer : ""; result += '\n'; - if (inst_size == 0) inst_size = is_thumb ? 2 : 4; - if (length <= inst_size) break; + if (inst_size == 0) + inst_size = is_thumb ? 2 : 4; + if (length <= inst_size) + break; pc += inst_size; instructions += inst_size; @@ -118,4 +120,4 @@ std::string DisassembleAArch64([[maybe_unused]] u32 instruction, [[maybe_unused] return result; } -} // namespace Dynarmic::Common +} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/llvm_disassemble.h b/src/dynarmic/common/llvm_disassemble.h index 21d0aea4..16dc15f8 100644 --- a/src/dynarmic/common/llvm_disassemble.h +++ b/src/dynarmic/common/llvm_disassemble.h @@ -15,4 +15,4 @@ std::string DisassembleX64(const void* pos, const void* end); std::string DisassembleAArch32(bool is_thumb, u32 pc, const u8* instructions, size_t length); std::string DisassembleAArch64(u32 instruction, u64 pc = 0); -} // namespace Dynarmic::Common +} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/lut_from_list.h b/src/dynarmic/common/lut_from_list.h index e6f660a1..5145a6b3 100644 --- a/src/dynarmic/common/lut_from_list.h +++ b/src/dynarmic/common/lut_from_list.h @@ -14,12 +14,12 @@ #include #ifdef _MSC_VER -#include +# include #endif namespace Dynarmic::Common { -template +template inline auto GenerateLookupTableFromList(Function f, mp::list) { #ifdef _MSC_VER using PairT = std::invoke_result_t>>; @@ -34,4 +34,4 @@ inline auto GenerateLookupTableFromList(Function f, mp::list) { return MapT(pair_array.begin(), pair_array.end()); } -} // namespace Dynarmic::Common +} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/macro_util.h b/src/dynarmic/common/macro_util.h index 63150678..2ccb33bd 100644 --- a/src/dynarmic/common/macro_util.h +++ b/src/dynarmic/common/macro_util.h @@ -6,10 +6,10 @@ #pragma once #define CONCATENATE_TOKENS(x, y) CONCATENATE_TOKENS_IMPL(x, y) -#define CONCATENATE_TOKENS_IMPL(x, y) x ## y +#define CONCATENATE_TOKENS_IMPL(x, y) x##y #ifdef __COUNTER__ -#define ANONYMOUS_VARIABLE(str) CONCATENATE_TOKENS(str, __COUNTER__) +# define ANONYMOUS_VARIABLE(str) CONCATENATE_TOKENS(str, __COUNTER__) #else -#define ANONYMOUS_VARIABLE(str) CONCATENATE_TOKENS(str, __LINE__) +# define ANONYMOUS_VARIABLE(str) CONCATENATE_TOKENS(str, __LINE__) #endif diff --git a/src/dynarmic/common/math_util.cpp b/src/dynarmic/common/math_util.cpp index 61800f35..32211fd9 100644 --- a/src/dynarmic/common/math_util.cpp +++ b/src/dynarmic/common/math_util.cpp @@ -3,9 +3,10 @@ * SPDX-License-Identifier: 0BSD */ -#include #include "dynarmic/common/math_util.h" +#include + namespace Dynarmic::Common { u8 RecipEstimate(u64 a) { @@ -64,4 +65,4 @@ u8 RecipSqrtEstimate(u64 a) { return lut[a & 0x1FF]; } -} // namespace Dynarmic::Common +} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/math_util.h b/src/dynarmic/common/math_util.h index d30ebebd..9006fb2d 100644 --- a/src/dynarmic/common/math_util.h +++ b/src/dynarmic/common/math_util.h @@ -44,4 +44,4 @@ u8 RecipEstimate(u64 a); */ u8 RecipSqrtEstimate(u64 a); -} // namespace Dynarmic::Common +} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/memory_pool.cpp b/src/dynarmic/common/memory_pool.cpp index 58f86b5e..9e25fba5 100644 --- a/src/dynarmic/common/memory_pool.cpp +++ b/src/dynarmic/common/memory_pool.cpp @@ -3,13 +3,14 @@ * SPDX-License-Identifier: 0BSD */ -#include - #include "dynarmic/common/memory_pool.h" +#include + namespace Dynarmic::Common { -Pool::Pool(size_t object_size, size_t initial_pool_size) : object_size(object_size), slab_size(initial_pool_size) { +Pool::Pool(size_t object_size, size_t initial_pool_size) + : object_size(object_size), slab_size(initial_pool_size) { AllocateNewSlab(); } @@ -40,4 +41,4 @@ void Pool::AllocateNewSlab() { remaining = slab_size; } -} // namespace Dynarmic::Common +} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/memory_pool.h b/src/dynarmic/common/memory_pool.h index f34041f7..1cbdd909 100644 --- a/src/dynarmic/common/memory_pool.h +++ b/src/dynarmic/common/memory_pool.h @@ -42,4 +42,4 @@ private: std::vector slabs; }; -} // namespace Dynarmic::Common +} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/safe_ops.h b/src/dynarmic/common/safe_ops.h index fbd17f62..50e20fbf 100644 --- a/src/dynarmic/common/safe_ops.h +++ b/src/dynarmic/common/safe_ops.h @@ -13,10 +13,14 @@ namespace Dynarmic::Safe { -template T LogicalShiftLeft(T value, int shift_amount); -template T LogicalShiftRight(T value, int shift_amount); -template T ArithmeticShiftLeft(T value, int shift_amount); -template T ArithmeticShiftRight(T value, int shift_amount); +template +T LogicalShiftLeft(T value, int shift_amount); +template +T LogicalShiftRight(T value, int shift_amount); +template +T ArithmeticShiftLeft(T value, int shift_amount); +template +T ArithmeticShiftRight(T value, int shift_amount); template T LogicalShiftLeft(T value, int shift_amount) { @@ -107,4 +111,4 @@ T Negate(T value) { return static_cast(~static_cast(value) + 1); } -} // namespace Dynarmic::Safe +} // namespace Dynarmic::Safe diff --git a/src/dynarmic/common/scope_exit.h b/src/dynarmic/common/scope_exit.h index fbe8378d..4801f135 100644 --- a/src/dynarmic/common/scope_exit.h +++ b/src/dynarmic/common/scope_exit.h @@ -17,40 +17,46 @@ struct ScopeExitTag {}; struct ScopeFailTag {}; struct ScopeSuccessTag {}; -template +template class ScopeExit final { public: - explicit ScopeExit(Function&& fn) : function(std::move(fn)) {} + explicit ScopeExit(Function&& fn) + : function(std::move(fn)) {} ~ScopeExit() noexcept { function(); } + private: Function function; }; -template +template class ScopeFail final { public: - explicit ScopeFail(Function&& fn) : function(std::move(fn)), exception_count(std::uncaught_exceptions()) {} + explicit ScopeFail(Function&& fn) + : function(std::move(fn)), exception_count(std::uncaught_exceptions()) {} ~ScopeFail() noexcept { if (std::uncaught_exceptions() > exception_count) { function(); } } + private: Function function; int exception_count; }; -template +template class ScopeSuccess final { public: - explicit ScopeSuccess(Function&& fn) : function(std::move(fn)), exception_count(std::uncaught_exceptions()) {} + explicit ScopeSuccess(Function&& fn) + : function(std::move(fn)), exception_count(std::uncaught_exceptions()) {} ~ScopeSuccess() { if (std::uncaught_exceptions() <= exception_count) { function(); } } + private: Function function; int exception_count; @@ -58,23 +64,23 @@ private: // We use ->* here as it has the highest precedence of the operators we can use. -template +template auto operator->*(ScopeExitTag, Function&& function) { return ScopeExit>{std::forward(function)}; } -template +template auto operator->*(ScopeFailTag, Function&& function) { return ScopeFail>{std::forward(function)}; } -template +template auto operator->*(ScopeSuccessTag, Function&& function) { return ScopeSuccess>{std::forward(function)}; } -} // namespace Dynarmic::detail +} // namespace Dynarmic::detail -#define SCOPE_EXIT auto ANONYMOUS_VARIABLE(_SCOPE_EXIT_) = ::Dynarmic::detail::ScopeExitTag{} ->* [&]() noexcept -#define SCOPE_FAIL auto ANONYMOUS_VARIABLE(_SCOPE_FAIL_) = ::Dynarmic::detail::ScopeFailTag{} ->* [&]() noexcept -#define SCOPE_SUCCESS auto ANONYMOUS_VARIABLE(_SCOPE_FAIL_) = ::Dynarmic::detail::ScopeSuccessTag{} ->* [&]() +#define SCOPE_EXIT auto ANONYMOUS_VARIABLE(_SCOPE_EXIT_) = ::Dynarmic::detail::ScopeExitTag{}->*[&]() noexcept +#define SCOPE_FAIL auto ANONYMOUS_VARIABLE(_SCOPE_FAIL_) = ::Dynarmic::detail::ScopeFailTag{}->*[&]() noexcept +#define SCOPE_SUCCESS auto ANONYMOUS_VARIABLE(_SCOPE_FAIL_) = ::Dynarmic::detail::ScopeSuccessTag{}->*[&]() diff --git a/src/dynarmic/common/string_util.h b/src/dynarmic/common/string_util.h index 42ed7d2b..900b3aad 100644 --- a/src/dynarmic/common/string_util.h +++ b/src/dynarmic/common/string_util.h @@ -7,9 +7,9 @@ namespace Dynarmic::Common { -template +template constexpr char SignToChar(T value) { return value >= 0 ? '+' : '-'; } -} // namespace Dynarmic::Common +} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/u128.cpp b/src/dynarmic/common/u128.cpp index c8c7d4ae..81aa0cf9 100644 --- a/src/dynarmic/common/u128.cpp +++ b/src/dynarmic/common/u128.cpp @@ -3,9 +3,10 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/common_types.h" #include "dynarmic/common/u128.h" +#include "dynarmic/common/common_types.h" + namespace Dynarmic { u128 Multiply64To128(u64 a, u64 b) { @@ -138,4 +139,4 @@ u128 StickyLogicalShiftRight(u128 operand, int amount) { return {}; } -} // namespace Dynarmic +} // namespace Dynarmic diff --git a/src/dynarmic/common/u128.h b/src/dynarmic/common/u128.h index 04b8ed1b..415173b0 100644 --- a/src/dynarmic/common/u128.h +++ b/src/dynarmic/common/u128.h @@ -20,10 +20,12 @@ struct u128 { u128& operator=(const u128&) = default; u128& operator=(u128&&) = default; - u128(u64 lower_, u64 upper_) : lower(lower_), upper(upper_) {} + u128(u64 lower_, u64 upper_) + : lower(lower_), upper(upper_) {} template - /* implicit */ u128(T value) : lower(value), upper(0) { + /* implicit */ u128(T value) + : lower(value), upper(0) { static_assert(std::is_integral_v); static_assert(Common::BitSize() <= Common::BitSize()); } @@ -93,4 +95,4 @@ u128 operator>>(u128 operand, int amount); /// If a 1 is shifted off, the LSB would be set. u128 StickyLogicalShiftRight(u128 operand, int amount); -} // namespace Dynarmic +} // namespace Dynarmic diff --git a/src/dynarmic/common/unlikely.h b/src/dynarmic/common/unlikely.h index 9f8ae34f..746418da 100644 --- a/src/dynarmic/common/unlikely.h +++ b/src/dynarmic/common/unlikely.h @@ -6,7 +6,7 @@ #pragma once #if defined(__clang__) || defined(__GNUC__) - #define UNLIKELY(x) __builtin_expect(!!(x), 0) +# define UNLIKELY(x) __builtin_expect(!!(x), 0) #else - #define UNLIKELY(x) !!(x) +# define UNLIKELY(x) !!(x) #endif diff --git a/src/dynarmic/common/variant_util.h b/src/dynarmic/common/variant_util.h index 0363ccae..4dd7f671 100644 --- a/src/dynarmic/common/variant_util.h +++ b/src/dynarmic/common/variant_util.h @@ -10,20 +10,20 @@ namespace Dynarmic::Common { namespace detail { -template -struct VariantVisitor : boost::static_visitor, Lambda { - VariantVisitor(Lambda&& lambda) - : Lambda(std::move(lambda)) - {} +template +struct VariantVisitor : boost::static_visitor + , Lambda { + VariantVisitor(Lambda&& lambda) + : Lambda(std::move(lambda)) {} - using Lambda::operator(); + using Lambda::operator(); }; -} // namespace detail +} // namespace detail template inline ReturnT VisitVariant(Variant&& variant, Lambda&& lambda) { return boost::apply_visitor(detail::VariantVisitor(std::move(lambda)), variant); } -} // namespace Dynarmic::Common +} // namespace Dynarmic::Common diff --git a/src/dynarmic/frontend/A32/FPSCR.h b/src/dynarmic/frontend/A32/FPSCR.h index 8ea745f5..f8f0205d 100644 --- a/src/dynarmic/frontend/A32/FPSCR.h +++ b/src/dynarmic/frontend/A32/FPSCR.h @@ -16,13 +16,13 @@ namespace Dynarmic::A32 { /** * Representation of the Floating-Point Status and Control Register. */ -class FPSCR final -{ +class FPSCR final { public: FPSCR() = default; FPSCR(const FPSCR&) = default; FPSCR(FPSCR&&) = default; - explicit FPSCR(u32 data) : value{data & mask} {} + explicit FPSCR(u32 data) + : value{data & mask} {} FPSCR& operator=(const FPSCR&) = default; FPSCR& operator=(FPSCR&&) = default; @@ -163,7 +163,7 @@ public: */ bool InRunFastMode() const { constexpr u32 runfast_mask = 0x03001F00; - constexpr u32 expected = 0x03000000; + constexpr u32 expected = 0x03000000; return (value & runfast_mask) == expected; } @@ -187,4 +187,4 @@ inline bool operator!=(FPSCR lhs, FPSCR rhs) { return !operator==(lhs, rhs); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/ITState.h b/src/dynarmic/frontend/A32/ITState.h index 000acfeb..ef8228f1 100644 --- a/src/dynarmic/frontend/A32/ITState.h +++ b/src/dynarmic/frontend/A32/ITState.h @@ -5,8 +5,8 @@ #pragma once -#include "dynarmic/common/common_types.h" #include "dynarmic/common/bit_util.h" +#include "dynarmic/common/common_types.h" #include "dynarmic/ir/cond.h" namespace Dynarmic::A32 { @@ -14,7 +14,8 @@ namespace Dynarmic::A32 { class ITState final { public: ITState() = default; - explicit ITState(u8 data) : value(data) {} + explicit ITState(u8 data) + : value(data) {} ITState& operator=(u8 data) { value = data; @@ -59,4 +60,4 @@ inline bool operator!=(ITState lhs, ITState rhs) { return !operator==(lhs, rhs); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/PSR.h b/src/dynarmic/frontend/A32/PSR.h index 9fc589f5..5c12ba4b 100644 --- a/src/dynarmic/frontend/A32/PSR.h +++ b/src/dynarmic/frontend/A32/PSR.h @@ -36,15 +36,15 @@ class PSR final { public: /// Valid processor modes that may be indicated. enum class Mode : u32 { - User = 0b10000, - FIQ = 0b10001, - IRQ = 0b10010, + User = 0b10000, + FIQ = 0b10001, + IRQ = 0b10010, Supervisor = 0b10011, - Monitor = 0b10110, - Abort = 0b10111, + Monitor = 0b10110, + Abort = 0b10111, Hypervisor = 0b11010, - Undefined = 0b11011, - System = 0b11111 + Undefined = 0b11011, + System = 0b11111 }; /// Instruction sets that may be signified through a PSR. @@ -56,7 +56,8 @@ public: }; PSR() = default; - explicit PSR(u32 data) : value{data & mask} {} + explicit PSR(u32 data) + : value{data & mask} {} PSR& operator=(u32 data) { value = data & mask; @@ -219,4 +220,4 @@ inline bool operator!=(PSR lhs, PSR rhs) { return !operator==(lhs, rhs); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/decoder/arm.h b/src/dynarmic/frontend/A32/decoder/arm.h index abe66213..3ef69c05 100644 --- a/src/dynarmic/frontend/A32/decoder/arm.h +++ b/src/dynarmic/frontend/A32/decoder/arm.h @@ -19,10 +19,10 @@ namespace Dynarmic::A32 { -template +template using ArmMatcher = Decoder::Matcher; -template +template std::vector> GetArmDecodeTable() { std::vector> table = { @@ -50,4 +50,4 @@ std::optional>> DecodeArm(u32 instruc return iter != table.end() ? std::optional>>(*iter) : std::nullopt; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/decoder/asimd.h b/src/dynarmic/frontend/A32/decoder/asimd.h index 126d941c..73b02975 100644 --- a/src/dynarmic/frontend/A32/decoder/asimd.h +++ b/src/dynarmic/frontend/A32/decoder/asimd.h @@ -18,10 +18,10 @@ namespace Dynarmic::A32 { -template +template using ASIMDMatcher = Decoder::Matcher; -template +template std::vector> GetASIMDDecodeTable() { std::vector> table = { @@ -74,4 +74,4 @@ std::optional>> DecodeASIMD(u32 ins return iter != table.end() ? std::optional>>(*iter) : std::nullopt; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/decoder/thumb16.h b/src/dynarmic/frontend/A32/decoder/thumb16.h index 75aa5efb..568d5f42 100644 --- a/src/dynarmic/frontend/A32/decoder/thumb16.h +++ b/src/dynarmic/frontend/A32/decoder/thumb16.h @@ -16,7 +16,7 @@ namespace Dynarmic::A32 { -template +template using Thumb16Matcher = Decoder::Matcher; template @@ -29,10 +29,10 @@ std::optional>> DecodeThumb16(u16 }; - const auto matches_instruction = [instruction](const auto& matcher){ return matcher.Matches(instruction); }; + const auto matches_instruction = [instruction](const auto& matcher) { return matcher.Matches(instruction); }; auto iter = std::find_if(table.begin(), table.end(), matches_instruction); return iter != table.end() ? std::optional>>(*iter) : std::nullopt; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/decoder/thumb32.h b/src/dynarmic/frontend/A32/decoder/thumb32.h index 0692f53c..2d5d5b1e 100644 --- a/src/dynarmic/frontend/A32/decoder/thumb32.h +++ b/src/dynarmic/frontend/A32/decoder/thumb32.h @@ -15,7 +15,7 @@ namespace Dynarmic::A32 { -template +template using Thumb32Matcher = Decoder::Matcher; template @@ -28,10 +28,10 @@ std::optional>> DecodeThumb32(u32 }; - const auto matches_instruction = [instruction](const auto& matcher){ return matcher.Matches(instruction); }; + const auto matches_instruction = [instruction](const auto& matcher) { return matcher.Matches(instruction); }; auto iter = std::find_if(table.begin(), table.end(), matches_instruction); return iter != table.end() ? std::optional>>(*iter) : std::nullopt; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/decoder/vfp.h b/src/dynarmic/frontend/A32/decoder/vfp.h index cb376169..62b1288a 100644 --- a/src/dynarmic/frontend/A32/decoder/vfp.h +++ b/src/dynarmic/frontend/A32/decoder/vfp.h @@ -10,14 +10,13 @@ #include #include - #include "dynarmic/common/common_types.h" #include "dynarmic/frontend/decoder/decoder_detail.h" #include "dynarmic/frontend/decoder/matcher.h" namespace Dynarmic::A32 { -template +template using VFPMatcher = Decoder::Matcher; template @@ -27,7 +26,7 @@ std::optional>> DecodeVFP(u32 instruc static const struct Tables { Table unconditional; Table conditional; - } tables = []{ + } tables = [] { Table list = { #define INST(fn, name, bitstring) DYNARMIC_DECODER_GET_MATCHER(VFPMatcher, fn, name, Decoder::detail::StringToArray<32>(bitstring)), @@ -49,10 +48,10 @@ std::optional>> DecodeVFP(u32 instruc const bool is_unconditional = (instruction & 0xF0000000) == 0xF0000000; const Table& table = is_unconditional ? tables.unconditional : tables.conditional; - const auto matches_instruction = [instruction](const auto& matcher){ return matcher.Matches(instruction); }; + const auto matches_instruction = [instruction](const auto& matcher) { return matcher.Matches(instruction); }; auto iter = std::find_if(table.begin(), table.end(), matches_instruction); return iter != table.end() ? std::optional>>(*iter) : std::nullopt; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/disassembler/disassembler.h b/src/dynarmic/frontend/A32/disassembler/disassembler.h index 3e2f686a..65dac998 100644 --- a/src/dynarmic/frontend/A32/disassembler/disassembler.h +++ b/src/dynarmic/frontend/A32/disassembler/disassembler.h @@ -14,4 +14,4 @@ namespace Dynarmic::A32 { std::string DisassembleArm(u32 instruction); std::string DisassembleThumb16(u16 instruction); -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/disassembler/disassembler_arm.cpp b/src/dynarmic/frontend/A32/disassembler/disassembler_arm.cpp index fcf8a1a1..8911354d 100644 --- a/src/dynarmic/frontend/A32/disassembler/disassembler_arm.cpp +++ b/src/dynarmic/frontend/A32/disassembler/disassembler_arm.cpp @@ -11,11 +11,11 @@ #include "dynarmic/common/bit_util.h" #include "dynarmic/common/string_util.h" -#include "dynarmic/frontend/imm.h" #include "dynarmic/frontend/A32/decoder/arm.h" #include "dynarmic/frontend/A32/decoder/vfp.h" #include "dynarmic/frontend/A32/disassembler/disassembler.h" #include "dynarmic/frontend/A32/types.h" +#include "dynarmic/frontend/imm.h" namespace Dynarmic::A32 { @@ -24,22 +24,26 @@ public: using instruction_return_type = std::string; static u32 ArmExpandImm(int rotate, Imm<8> imm8) { - return Common::RotateRight(static_cast(imm8.ZeroExtend()), rotate*2); + return Common::RotateRight(static_cast(imm8.ZeroExtend()), rotate * 2); } static std::string ShiftStr(ShiftType shift, Imm<5> imm5) { switch (shift) { case ShiftType::LSL: - if (imm5 == 0) return ""; + if (imm5 == 0) + return ""; return fmt::format(", lsl #{}", imm5.ZeroExtend()); case ShiftType::LSR: - if (imm5 == 0) return ", lsr #32"; + if (imm5 == 0) + return ", lsr #32"; return fmt::format(", lsr #{}", imm5.ZeroExtend()); case ShiftType::ASR: - if (imm5 == 0) return ", asr #32"; + if (imm5 == 0) + return ", asr #32"; return fmt::format(", asr #{}", imm5.ZeroExtend()); case ShiftType::ROR: - if (imm5 == 0) return ", rrx"; + if (imm5 == 0) + return ", rrx"; return fmt::format(", ror #{}", imm5.ZeroExtend()); } ASSERT(false); @@ -47,7 +51,7 @@ public: } static std::string RsrStr(Reg s, ShiftType shift, Reg m) { - switch (shift){ + switch (shift) { case ShiftType::LSL: return fmt::format("{}, lsl {}", m, s); case ShiftType::LSR: @@ -92,7 +96,7 @@ public: return " ish"; case 0b1110: return " st"; - case 0b1111: // SY can be omitted. + case 0b1111: // SY can be omitted. return ""; default: return " unknown"; @@ -234,14 +238,20 @@ public: // CRC32 instructions std::string arm_CRC32([[maybe_unused]] Cond cond, Imm<2> sz, Reg n, Reg d, Reg m) { static constexpr std::array data_type{ - "b", "h", "w", "invalid", + "b", + "h", + "w", + "invalid", }; return fmt::format("crc32{} {}, {}, {}", data_type[sz.ZeroExtend()], d, n, m); } std::string arm_CRC32C([[maybe_unused]] Cond cond, Imm<2> sz, Reg n, Reg d, Reg m) { static constexpr std::array data_type{ - "b", "h", "w", "invalid", + "b", + "h", + "w", + "invalid", }; return fmt::format("crc32c{} {}, {}, {}", data_type[sz.ZeroExtend()], d, n, m); @@ -548,11 +558,11 @@ public: if (P) { return fmt::format("ldrd{} {}, {}, [{}, #{}{}]{}", - CondToString(cond), t, t+1, n, sign, imm32, + CondToString(cond), t, t + 1, n, sign, imm32, W ? "!" : ""); } else { return fmt::format("ldrd{} {}, {}, [{}], #{}{}{}", - CondToString(cond), t, t+1, n, sign, imm32, + CondToString(cond), t, t + 1, n, sign, imm32, W ? " (err: W == 1!!!)" : ""); } } @@ -561,11 +571,11 @@ public: if (P) { return fmt::format("ldrd{} {}, {}, [{}, {}{}]{}", - CondToString(cond), t, t+1, n, sign, m, + CondToString(cond), t, t + 1, n, sign, m, W ? "!" : ""); } else { return fmt::format("ldrd{} {}, {}, [{}], {}{}{}", - CondToString(cond), t, t+1, n, sign, m, + CondToString(cond), t, t + 1, n, sign, m, W ? " (err: W == 1!!!)" : ""); } } @@ -728,11 +738,11 @@ public: if (P) { return fmt::format("strd{} {}, {}, [{}, #{}{}]{}", - CondToString(cond), t, t+1, n, sign, imm32, + CondToString(cond), t, t + 1, n, sign, imm32, W ? "!" : ""); } else { return fmt::format("strd{} {}, {}, [{}], #{}{}{}", - CondToString(cond), t, t+1, n, sign, imm32, + CondToString(cond), t, t + 1, n, sign, imm32, W ? " (err: W == 1!!!)" : ""); } } @@ -741,11 +751,11 @@ public: if (P) { return fmt::format("strd{} {}, {}, [{}, {}{}]{}", - CondToString(cond), t, t+1, n, sign, m, + CondToString(cond), t, t + 1, n, sign, m, W ? "!" : ""); } else { return fmt::format("strd{} {}, {}, [{}], {}{}{}", - CondToString(cond), t, t+1, n, sign, m, + CondToString(cond), t, t + 1, n, sign, m, W ? " (err: W == 1!!!)" : ""); } } @@ -1143,7 +1153,7 @@ public: return fmt::format("ldaexb{} {}, [{}]", CondToString(cond), t, n); } std::string arm_LDAEXD(Cond cond, Reg n, Reg t) { - return fmt::format("ldaexd{} {}, {}, [{}]", CondToString(cond), t, t+1, n); + return fmt::format("ldaexd{} {}, {}, [{}]", CondToString(cond), t, t + 1, n); } std::string arm_LDAEXH(Cond cond, Reg n, Reg t) { return fmt::format("ldaexh{} {}, [{}]", CondToString(cond), t, n); @@ -1164,7 +1174,7 @@ public: return fmt::format("stlexb{} {}, {}, [{}]", CondToString(cond), d, m, n); } std::string arm_STLEXD(Cond cond, Reg n, Reg d, Reg m) { - return fmt::format("stlexd{} {}, {}, {}, [{}]", CondToString(cond), d, m, m+1, n); + return fmt::format("stlexd{} {}, {}, {}, [{}]", CondToString(cond), d, m, m + 1, n); } std::string arm_STLEXH(Cond cond, Reg n, Reg d, Reg m) { return fmt::format("stlexh{} {}, {}, [{}]", CondToString(cond), d, m, n); @@ -1176,7 +1186,7 @@ public: return fmt::format("ldrexb{} {}, [{}]", CondToString(cond), d, n); } std::string arm_LDREXD(Cond cond, Reg n, Reg d) { - return fmt::format("ldrexd{} {}, {}, [{}]", CondToString(cond), d, d+1, n); + return fmt::format("ldrexd{} {}, {}, [{}]", CondToString(cond), d, d + 1, n); } std::string arm_LDREXH(Cond cond, Reg n, Reg d) { return fmt::format("ldrexh{} {}, [{}]", CondToString(cond), d, n); @@ -1188,7 +1198,7 @@ public: return fmt::format("strexb{} {}, {}, [{}]", CondToString(cond), d, m, n); } std::string arm_STREXD(Cond cond, Reg n, Reg d, Reg m) { - return fmt::format("strexd{} {}, {}, {}, [{}]", CondToString(cond), d, m, m+1, n); + return fmt::format("strexd{} {}, {}, {}, [{}]", CondToString(cond), d, m, m + 1, n); } std::string arm_STREXH(Cond cond, Reg n, Reg d, Reg m) { return fmt::format("strexh{} {}, {}, [{}]", CondToString(cond), d, m, n); @@ -1315,35 +1325,35 @@ public: } } - std::string vfp_VMOV_u32_f64(Cond cond, size_t Vd, Reg t, bool D){ + std::string vfp_VMOV_u32_f64(Cond cond, size_t Vd, Reg t, bool D) { return fmt::format("vmov{}.32 {}, {}", CondToString(cond), FPRegStr(true, Vd, D), t); } - std::string vfp_VMOV_f64_u32(Cond cond, size_t Vn, Reg t, bool N){ + std::string vfp_VMOV_f64_u32(Cond cond, size_t Vn, Reg t, bool N) { return fmt::format("vmov{}.32 {}, {}", CondToString(cond), t, FPRegStr(true, Vn, N)); } - std::string vfp_VMOV_u32_f32(Cond cond, size_t Vn, Reg t, bool N){ + std::string vfp_VMOV_u32_f32(Cond cond, size_t Vn, Reg t, bool N) { return fmt::format("vmov{}.32 {}, {}", CondToString(cond), FPRegStr(false, Vn, N), t); } - std::string vfp_VMOV_f32_u32(Cond cond, size_t Vn, Reg t, bool N){ + std::string vfp_VMOV_f32_u32(Cond cond, size_t Vn, Reg t, bool N) { return fmt::format("vmov{}.32 {}, {}", CondToString(cond), t, FPRegStr(false, Vn, N)); } - std::string vfp_VMOV_2u32_2f32(Cond cond, Reg t2, Reg t, bool M, size_t Vm){ + std::string vfp_VMOV_2u32_2f32(Cond cond, Reg t2, Reg t, bool M, size_t Vm) { return fmt::format("vmov{} {}, {}, {}, {}", CondToString(cond), FPRegStr(false, Vm, M), FPNextRegStr(false, Vm, M), t, t2); } - std::string vfp_VMOV_2f32_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm){ + std::string vfp_VMOV_2f32_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm) { return fmt::format("vmov{} {}, {}, {}, {}", CondToString(cond), t, t2, FPRegStr(false, Vm, M), FPNextRegStr(false, Vm, M)); } - std::string vfp_VMOV_2u32_f64(Cond cond, Reg t2, Reg t, bool M, size_t Vm){ + std::string vfp_VMOV_2u32_f64(Cond cond, Reg t2, Reg t, bool M, size_t Vm) { return fmt::format("vmov{} {}, {}, {}", CondToString(cond), FPRegStr(true, Vm, M), t, t2); } - std::string vfp_VMOV_f64_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm){ + std::string vfp_VMOV_f64_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm) { return fmt::format("vmov{} {}, {}, {}", CondToString(cond), t, t2, FPRegStr(true, Vm, M)); } @@ -1382,7 +1392,7 @@ public: return fmt::format("vdup{}.{} {}, {}", CondToString(cond), esize, VectorStr(Q, Vd, D), t); } - std::string vfp_VMOV_reg(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm){ + std::string vfp_VMOV_reg(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { return fmt::format("vmov{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M)); } @@ -1570,4 +1580,4 @@ std::string DisassembleArm(u32 instruction) { } } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/disassembler/disassembler_thumb.cpp b/src/dynarmic/frontend/A32/disassembler/disassembler_thumb.cpp index 345d778f..b2225513 100644 --- a/src/dynarmic/frontend/A32/disassembler/disassembler_thumb.cpp +++ b/src/dynarmic/frontend/A32/disassembler/disassembler_thumb.cpp @@ -11,10 +11,10 @@ #include "dynarmic/common/bit_util.h" #include "dynarmic/common/string_util.h" -#include "dynarmic/frontend/imm.h" #include "dynarmic/frontend/A32/decoder/thumb16.h" #include "dynarmic/frontend/A32/disassembler/disassembler.h" #include "dynarmic/frontend/A32/types.h" +#include "dynarmic/frontend/imm.h" namespace Dynarmic::A32 { @@ -272,7 +272,7 @@ public: std::string thumb16_IT(Imm<8> imm8) { const Cond firstcond = imm8.Bits<4, 7, Cond>(); const bool firstcond0 = imm8.Bit<4>(); - const auto [x, y, z] = [&]{ + const auto [x, y, z] = [&] { if (imm8.Bits<0, 3>() == 0b1000) { return std::make_tuple("", "", ""); } @@ -305,12 +305,14 @@ public: } std::string thumb16_PUSH(bool M, RegList reg_list) { - if (M) reg_list |= 1 << 14; + if (M) + reg_list |= 1 << 14; return fmt::format("push {{{}}}", RegListToString(reg_list)); } std::string thumb16_POP(bool P, RegList reg_list) { - if (P) reg_list |= 1 << 15; + if (P) + reg_list |= 1 << 15; return fmt::format("pop {{{}}}", RegListToString(reg_list)); } @@ -392,4 +394,4 @@ std::string DisassembleThumb16(u16 instruction) { return !decoder ? fmt::format("UNKNOWN: {:x}", instruction) : decoder->get().call(visitor, instruction); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/ir_emitter.cpp b/src/dynarmic/frontend/A32/ir_emitter.cpp index ac77a610..9839beca 100644 --- a/src/dynarmic/frontend/A32/ir_emitter.cpp +++ b/src/dynarmic/frontend/A32/ir_emitter.cpp @@ -3,8 +3,9 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/assert.h" #include "dynarmic/frontend/A32/ir_emitter.h" + +#include "dynarmic/common/assert.h" #include "dynarmic/frontend/A32/types.h" #include "dynarmic/interface/A32/arch_version.h" #include "dynarmic/ir/opcodes.h" @@ -429,4 +430,4 @@ void IREmitter::CoprocStoreWords(size_t coproc_no, bool two, bool long_transfer, Inst(Opcode::A32CoprocStoreWords, IR::Value(coproc_info), address); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/ir_emitter.h b/src/dynarmic/frontend/A32/ir_emitter.h index 816ddcaa..80bcf6b9 100644 --- a/src/dynarmic/frontend/A32/ir_emitter.h +++ b/src/dynarmic/frontend/A32/ir_emitter.h @@ -27,7 +27,8 @@ enum class Reg; */ class IREmitter : public IR::IREmitter { public: - IREmitter(IR::Block& block, LocationDescriptor descriptor, ArchVersion arch_version) : IR::IREmitter(block), current_location(descriptor), arch_version(arch_version) {} + IREmitter(IR::Block& block, LocationDescriptor descriptor, ArchVersion arch_version) + : IR::IREmitter(block), current_location(descriptor), arch_version(arch_version) {} LocationDescriptor current_location; @@ -108,4 +109,4 @@ private: enum ArchVersion arch_version; }; -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/location_descriptor.cpp b/src/dynarmic/frontend/A32/location_descriptor.cpp index 7844f78c..e3cd3bc1 100644 --- a/src/dynarmic/frontend/A32/location_descriptor.cpp +++ b/src/dynarmic/frontend/A32/location_descriptor.cpp @@ -3,10 +3,12 @@ * SPDX-License-Identifier: 0BSD */ -#include -#include #include "dynarmic/frontend/A32/location_descriptor.h" +#include + +#include + namespace Dynarmic::A32 { std::ostream& operator<<(std::ostream& o, const LocationDescriptor& descriptor) { @@ -19,4 +21,4 @@ std::ostream& operator<<(std::ostream& o, const LocationDescriptor& descriptor) return o; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/location_descriptor.h b/src/dynarmic/frontend/A32/location_descriptor.h index c7117daf..4b68d2de 100644 --- a/src/dynarmic/frontend/A32/location_descriptor.h +++ b/src/dynarmic/frontend/A32/location_descriptor.h @@ -8,10 +8,11 @@ #include #include #include + #include "dynarmic/common/common_types.h" #include "dynarmic/frontend/A32/FPSCR.h" -#include "dynarmic/frontend/A32/PSR.h" #include "dynarmic/frontend/A32/ITState.h" +#include "dynarmic/frontend/A32/PSR.h" #include "dynarmic/ir/location_descriptor.h" namespace Dynarmic::A32 { @@ -25,15 +26,14 @@ namespace Dynarmic::A32 { class LocationDescriptor { public: // Indicates bits that should be preserved within descriptors. - static constexpr u32 CPSR_MODE_MASK = 0x0600FE20; + static constexpr u32 CPSR_MODE_MASK = 0x0600FE20; static constexpr u32 FPSCR_MODE_MASK = 0x07F70000; LocationDescriptor(u32 arm_pc, PSR cpsr, FPSCR fpscr, bool single_stepping = false) - : arm_pc(arm_pc) - , cpsr(cpsr.Value() & CPSR_MODE_MASK) - , fpscr(fpscr.Value() & FPSCR_MODE_MASK) - , single_stepping(single_stepping) - {} + : arm_pc(arm_pc) + , cpsr(cpsr.Value() & CPSR_MODE_MASK) + , fpscr(fpscr.Value() & FPSCR_MODE_MASK) + , single_stepping(single_stepping) {} explicit LocationDescriptor(const IR::LocationDescriptor& o) { arm_pc = static_cast(o.Value()); @@ -54,11 +54,11 @@ public: bool SingleStepping() const { return single_stepping; } - bool operator == (const LocationDescriptor& o) const { + bool operator==(const LocationDescriptor& o) const { return std::tie(arm_pc, cpsr, fpscr, single_stepping) == std::tie(o.arm_pc, o.cpsr, o.fpscr, o.single_stepping); } - bool operator != (const LocationDescriptor& o) const { + bool operator!=(const LocationDescriptor& o) const { return !operator==(o); } @@ -121,9 +121,9 @@ public: } private: - u32 arm_pc; ///< Current program counter value. - PSR cpsr; ///< Current program status register. - A32::FPSCR fpscr; ///< Floating point status control register. + u32 arm_pc; ///< Current program counter value. + PSR cpsr; ///< Current program status register. + A32::FPSCR fpscr; ///< Floating point status control register. bool single_stepping; }; @@ -135,19 +135,19 @@ private: */ std::ostream& operator<<(std::ostream& o, const LocationDescriptor& descriptor); -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 namespace std { -template <> +template<> struct less { bool operator()(const Dynarmic::A32::LocationDescriptor& x, const Dynarmic::A32::LocationDescriptor& y) const noexcept { return x.UniqueHash() < y.UniqueHash(); } }; -template <> +template<> struct hash { size_t operator()(const Dynarmic::A32::LocationDescriptor& x) const noexcept { return std::hash()(x.UniqueHash()); } }; -} // namespace std +} // namespace std diff --git a/src/dynarmic/frontend/A32/translate/conditional_state.cpp b/src/dynarmic/frontend/A32/translate/conditional_state.cpp index 4673c8a2..9ed61a9c 100644 --- a/src/dynarmic/frontend/A32/translate/conditional_state.cpp +++ b/src/dynarmic/frontend/A32/translate/conditional_state.cpp @@ -3,12 +3,13 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/frontend/A32/translate/conditional_state.h" + #include #include "dynarmic/common/assert.h" #include "dynarmic/common/common_types.h" #include "dynarmic/frontend/A32/ir_emitter.h" -#include "dynarmic/frontend/A32/translate/conditional_state.h" #include "dynarmic/frontend/A32/translate/impl/translate.h" #include "dynarmic/interface/A32/config.h" #include "dynarmic/ir/cond.h" @@ -76,4 +77,4 @@ bool IsConditionPassed(TranslatorVisitor& v, IR::Cond cond) { return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/conditional_state.h b/src/dynarmic/frontend/A32/translate/conditional_state.h index 8ec42392..a86bf9fb 100644 --- a/src/dynarmic/frontend/A32/translate/conditional_state.h +++ b/src/dynarmic/frontend/A32/translate/conditional_state.h @@ -9,7 +9,7 @@ namespace Dynarmic::IR { enum class Cond; -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR namespace Dynarmic::A32 { @@ -30,4 +30,4 @@ enum class ConditionalState { bool CondCanContinue(ConditionalState cond_state, const A32::IREmitter& ir); bool IsConditionPassed(TranslatorVisitor& v, IR::Cond cond); -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp b/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp index 5c9f35de..54412f1b 100644 --- a/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp @@ -3,11 +3,11 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/frontend/A32/translate/impl/translate.h" - #include #include + #include "dynarmic/common/bit_util.h" +#include "dynarmic/frontend/A32/translate/impl/translate.h" namespace Dynarmic::A32 { @@ -15,54 +15,54 @@ namespace { std::optional> DecodeType(Imm<4> type, size_t size, size_t align) { switch (type.ZeroExtend()) { - case 0b0111: // VST1 A1 / VLD1 A1 + case 0b0111: // VST1 A1 / VLD1 A1 if (Common::Bit<1>(align)) { return std::nullopt; } return std::tuple{1, 1, 0}; - case 0b1010: // VST1 A2 / VLD1 A2 + case 0b1010: // VST1 A2 / VLD1 A2 if (align == 0b11) { return std::nullopt; } return std::tuple{1, 2, 0}; - case 0b0110: // VST1 A3 / VLD1 A3 + case 0b0110: // VST1 A3 / VLD1 A3 if (Common::Bit<1>(align)) { return std::nullopt; } return std::tuple{1, 3, 0}; - case 0b0010: // VST1 A4 / VLD1 A4 + case 0b0010: // VST1 A4 / VLD1 A4 return std::tuple{1, 4, 0}; - case 0b1000: // VST2 A1 / VLD2 A1 + case 0b1000: // VST2 A1 / VLD2 A1 if (size == 0b11 || align == 0b11) { return std::nullopt; } return std::tuple{2, 1, 1}; - case 0b1001: // VST2 A1 / VLD2 A1 + case 0b1001: // VST2 A1 / VLD2 A1 if (size == 0b11 || align == 0b11) { return std::nullopt; } return std::tuple{2, 1, 2}; - case 0b0011: // VST2 A2 / VLD2 A2 + case 0b0011: // VST2 A2 / VLD2 A2 if (size == 0b11) { return std::nullopt; } return std::tuple{2, 2, 2}; - case 0b0100: // VST3 / VLD3 + case 0b0100: // VST3 / VLD3 if (size == 0b11 || Common::Bit<1>(align)) { return std::nullopt; } return std::tuple{3, 1, 1}; - case 0b0101: // VST3 / VLD3 + case 0b0101: // VST3 / VLD3 if (size == 0b11 || Common::Bit<1>(align)) { return std::nullopt; } return std::tuple{3, 1, 2}; - case 0b0000: // VST4 / VLD4 + case 0b0000: // VST4 / VLD4 if (size == 0b11) { return std::nullopt; } return std::tuple{4, 1, 1}; - case 0b0001: // VST4 / VLD4 + case 0b0001: // VST4 / VLD4 if (size == 0b11) { return std::nullopt; } @@ -70,7 +70,7 @@ std::optional> DecodeType(Imm<4> type, size_t } ASSERT_FALSE("Decode error"); } -} // anoynmous namespace +} // namespace bool TranslatorVisitor::v8_VST_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t size, size_t align, Reg m) { if (type == 0b1011 || type.Bits<2, 3>() == 0b11) { @@ -371,4 +371,4 @@ bool TranslatorVisitor::v8_VLD_single(bool D, Reg n, size_t Vd, size_t sz, size_ return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp b/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp index cdb022be..3e05d428 100644 --- a/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp @@ -3,10 +3,9 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/frontend/A32/translate/impl/translate.h" - #include "dynarmic/common/assert.h" #include "dynarmic/common/bit_util.h" +#include "dynarmic/frontend/A32/translate/impl/translate.h" namespace Dynarmic::A32 { @@ -20,7 +19,7 @@ static bool TableLookup(TranslatorVisitor& v, bool is_vtbl, bool D, size_t Vn, s return v.UnpredictableInstruction(); } - const IR::Table table = v.ir.VectorTable([&]{ + const IR::Table table = v.ir.VectorTable([&] { std::vector result; for (size_t i = 0; i < length; ++i) { result.emplace_back(v.ir.GetExtendedRegister(n + i)); @@ -88,4 +87,4 @@ bool TranslatorVisitor::asimd_VDUP_scalar(bool D, Imm<4> imm4, size_t Vd, bool Q return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp b/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp index 73f2dac7..7796cd7b 100644 --- a/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp @@ -3,15 +3,13 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/frontend/A32/translate/impl/translate.h" - #include "dynarmic/common/assert.h" #include "dynarmic/common/bit_util.h" +#include "dynarmic/frontend/A32/translate/impl/translate.h" namespace Dynarmic::A32 { -bool TranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c, Imm<1> d, size_t Vd, - Imm<4> cmode, bool Q, bool op, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h) { +bool TranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c, Imm<1> d, size_t Vd, Imm<4> cmode, bool Q, bool op, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h) { if (Q && Common::Bit<0>(Vd)) { return UndefinedInstruction(); } @@ -68,31 +66,46 @@ bool TranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c, Imm }; switch (concatenate(cmode, Imm<1>{op}).ZeroExtend()) { - case 0b00000: case 0b00100: - case 0b01000: case 0b01100: - case 0b10000: case 0b10100: - case 0b11000: case 0b11010: - case 0b11100: case 0b11101: + case 0b00000: + case 0b00100: + case 0b01000: + case 0b01100: + case 0b10000: + case 0b10100: + case 0b11000: + case 0b11010: + case 0b11100: + case 0b11101: case 0b11110: return mov(); case 0b11111: return UndefinedInstruction(); - case 0b00001: case 0b00101: - case 0b01001: case 0b01101: - case 0b10001: case 0b10101: - case 0b11001: case 0b11011: + case 0b00001: + case 0b00101: + case 0b01001: + case 0b01101: + case 0b10001: + case 0b10101: + case 0b11001: + case 0b11011: return mvn(); - case 0b00010: case 0b00110: - case 0b01010: case 0b01110: - case 0b10010: case 0b10110: + case 0b00010: + case 0b00110: + case 0b01010: + case 0b01110: + case 0b10010: + case 0b10110: return orr(); - case 0b00011: case 0b00111: - case 0b01011: case 0b01111: - case 0b10011: case 0b10111: + case 0b00011: + case 0b00111: + case 0b01011: + case 0b01111: + case 0b10011: + case 0b10111: return bic(); } UNREACHABLE(); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp b/src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp index bc37e44f..49a655c0 100644 --- a/src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp @@ -3,9 +3,8 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/frontend/A32/translate/impl/translate.h" - #include "dynarmic/common/bit_util.h" +#include "dynarmic/frontend/A32/translate/impl/translate.h" namespace Dynarmic::A32 { namespace { @@ -27,7 +26,7 @@ enum class WidenBehaviour { Both, }; -template +template bool BitwiseInstruction(TranslatorVisitor& v, bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, Callable fn) { if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { return v.UndefinedInstruction(); @@ -53,7 +52,7 @@ bool BitwiseInstruction(TranslatorVisitor& v, bool D, size_t Vn, size_t Vd, bool return true; } -template +template bool FloatingPointInstruction(TranslatorVisitor& v, bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, Callable fn) { if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { return v.UndefinedInstruction(); @@ -76,8 +75,7 @@ bool FloatingPointInstruction(TranslatorVisitor& v, bool D, bool sz, size_t Vn, return true; } -bool IntegerComparison(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, - Comparison comparison) { +bool IntegerComparison(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, Comparison comparison) { if (sz == 0b11) { return v.UndefinedInstruction(); } @@ -112,8 +110,7 @@ bool IntegerComparison(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t V return true; } -bool FloatComparison(TranslatorVisitor& v, bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, - Comparison comparison) { +bool FloatComparison(TranslatorVisitor& v, bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, Comparison comparison) { if (sz) { return v.UndefinedInstruction(); } @@ -149,8 +146,7 @@ bool FloatComparison(TranslatorVisitor& v, bool D, bool sz, size_t Vn, size_t Vd return true; } -bool AbsoluteDifference(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, - AccumulateBehavior accumulate) { +bool AbsoluteDifference(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, AccumulateBehavior accumulate) { if (sz == 0b11) { return v.UndefinedInstruction(); } @@ -182,8 +178,7 @@ bool AbsoluteDifference(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t return true; } -bool AbsoluteDifferenceLong(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool M, size_t Vm, - AccumulateBehavior accumulate) { +bool AbsoluteDifferenceLong(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool M, size_t Vm, AccumulateBehavior accumulate) { if (sz == 0b11) { return v.DecodeError(); } @@ -217,7 +212,7 @@ bool AbsoluteDifferenceLong(TranslatorVisitor& v, bool U, bool D, size_t sz, siz return true; } -template +template bool WideInstruction(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool M, size_t Vm, WidenBehaviour widen_behaviour, Callable fn) { const size_t esize = 8U << sz; const bool widen_first = widen_behaviour == WidenBehaviour::Both; @@ -245,7 +240,7 @@ bool WideInstruction(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t Vn, return true; } -} // Anonymous namespace +} // Anonymous namespace // ASIMD Three registers of the same length @@ -893,4 +888,4 @@ bool TranslatorVisitor::asimd_VMULL(bool U, bool D, size_t sz, size_t Vn, size_t return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp index 18e29a1e..449d46da 100644 --- a/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp @@ -3,11 +3,10 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/frontend/A32/translate/impl/translate.h" - #include #include "dynarmic/common/bit_util.h" +#include "dynarmic/frontend/A32/translate/impl/translate.h" namespace Dynarmic::A32 { namespace { @@ -19,8 +18,7 @@ enum class Comparison { LT, }; -bool CompareWithZero(TranslatorVisitor& v, bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm, - Comparison type) { +bool CompareWithZero(TranslatorVisitor& v, bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm, Comparison type) { if (sz == 0b11 || (F && sz != 0b10)) { return v.UndefinedInstruction(); } @@ -73,8 +71,7 @@ enum class AccumulateBehavior { Accumulate, }; -bool PairedAddOperation(TranslatorVisitor& v, bool D, size_t sz, size_t Vd, bool op, bool Q, bool M, size_t Vm, - AccumulateBehavior accumulate) { +bool PairedAddOperation(TranslatorVisitor& v, bool D, size_t sz, size_t Vd, bool op, bool Q, bool M, size_t Vm, AccumulateBehavior accumulate) { if (sz == 0b11) { return v.UndefinedInstruction(); } @@ -104,7 +101,7 @@ bool PairedAddOperation(TranslatorVisitor& v, bool D, size_t sz, size_t Vd, bool return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool Q, bool M, size_t Vm) { if (op + sz >= 3) { @@ -128,11 +125,11 @@ bool TranslatorVisitor::asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool ir.VectorLogicalShiftLeft(esize, reg_m, shift)); switch (sz) { - case 0: // 8-bit elements + case 0: // 8-bit elements result = ir.VectorShuffleLowHalfwords(result, 0b00011011); result = ir.VectorShuffleHighHalfwords(result, 0b00011011); break; - case 1: // 16-bit elements + case 1: // 16-bit elements result = ir.VectorShuffleLowHalfwords(result, 0b01001110); result = ir.VectorShuffleHighHalfwords(result, 0b01001110); break; @@ -535,7 +532,7 @@ bool TranslatorVisitor::asimd_VZIP(bool D, size_t sz, size_t Vd, bool Q, bool M, const auto reg_d = ir.GetVector(d); const auto reg_m = ir.GetVector(m); - if (Q){ + if (Q) { const auto result_d = ir.VectorInterleaveLower(esize, reg_d, reg_m); const auto result_m = ir.VectorInterleaveUpper(esize, reg_d, reg_m); @@ -624,7 +621,7 @@ bool TranslatorVisitor::asimd_VCVT_half(bool D, size_t sz, size_t Vd, bool half_ const size_t esize = 8U << sz; const size_t num_elements = 4; - const auto rounding_mode = FP::RoundingMode::ToNearest_TieEven; // StandardFPSCRValue().RMode + const auto rounding_mode = FP::RoundingMode::ToNearest_TieEven; // StandardFPSCRValue().RMode const auto d = ToVector(half_to_single, Vd, D); const auto m = ToVector(!half_to_single, Vm, M); @@ -719,4 +716,4 @@ bool TranslatorVisitor::asimd_VCVT_integer(bool D, size_t sz, size_t Vd, bool op return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp b/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp index f8d304c2..ebba0681 100644 --- a/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp @@ -3,12 +3,11 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/frontend/A32/translate/impl/translate.h" - #include #include "dynarmic/common/assert.h" #include "dynarmic/common/bit_util.h" +#include "dynarmic/frontend/A32/translate/impl/translate.h" namespace Dynarmic::A32 { namespace { @@ -29,8 +28,7 @@ enum class Rounding { Round, }; -bool ScalarMultiply(TranslatorVisitor& v, bool Q, bool D, size_t sz, size_t Vn, size_t Vd, bool F, bool N, bool M, size_t Vm, - MultiplyBehavior multiply) { +bool ScalarMultiply(TranslatorVisitor& v, bool Q, bool D, size_t sz, size_t Vn, size_t Vd, bool F, bool N, bool M, size_t Vm, MultiplyBehavior multiply) { if (sz == 0b11) { return v.DecodeError(); } @@ -72,8 +70,7 @@ bool ScalarMultiply(TranslatorVisitor& v, bool Q, bool D, size_t sz, size_t Vn, return true; } -bool ScalarMultiplyLong(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool M, size_t Vm, - MultiplyBehavior multiply) { +bool ScalarMultiplyLong(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool M, size_t Vm, MultiplyBehavior multiply) { if (sz == 0b11) { return v.DecodeError(); } @@ -110,8 +107,7 @@ bool ScalarMultiplyLong(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t return true; } -bool ScalarMultiplyReturnHigh(TranslatorVisitor& v, bool Q, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool M, size_t Vm, - Rounding round) { +bool ScalarMultiplyReturnHigh(TranslatorVisitor& v, bool Q, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool M, size_t Vm, Rounding round) { if (sz == 0b11) { return v.DecodeError(); } @@ -145,7 +141,7 @@ bool ScalarMultiplyReturnHigh(TranslatorVisitor& v, bool Q, bool D, size_t sz, s v.ir.SetVector(d, result); return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::asimd_VMLA_scalar(bool Q, bool D, size_t sz, size_t Vn, size_t Vd, bool op, bool F, bool N, bool M, size_t Vm) { const auto behavior = op ? MultiplyBehavior::MultiplySubtract @@ -198,4 +194,4 @@ bool TranslatorVisitor::asimd_VQRDMULH_scalar(bool Q, bool D, size_t sz, size_t return ScalarMultiplyReturnHigh(*this, Q, D, sz, Vn, Vd, N, M, Vm, Rounding::Round); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp b/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp index 69c87e2f..e5ea0e22 100644 --- a/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp @@ -3,10 +3,9 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/frontend/A32/translate/impl/translate.h" - #include "dynarmic/common/assert.h" #include "dynarmic/common/bit_util.h" +#include "dynarmic/frontend/A32/translate/impl/translate.h" namespace Dynarmic::A32 { namespace { @@ -57,8 +56,7 @@ std::pair ElementSizeAndShiftAmount(bool right_shift, bool L, si } } -bool ShiftRight(TranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm, - Accumulating accumulate, Rounding rounding) { +bool ShiftRight(TranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm, Accumulating accumulate, Rounding rounding) { if (!L && Common::Bits<3, 5>(imm6) == 0) { return v.DecodeError(); } @@ -89,8 +87,7 @@ bool ShiftRight(TranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd, bo return true; } -bool ShiftRightNarrowing(TranslatorVisitor& v, bool D, size_t imm6, size_t Vd, bool M, size_t Vm, - Rounding rounding, Narrowing narrowing, Signedness signedness) { +bool ShiftRightNarrowing(TranslatorVisitor& v, bool D, size_t imm6, size_t Vd, bool M, size_t Vm, Rounding rounding, Narrowing narrowing, Signedness signedness) { if (Common::Bits<3, 5>(imm6) == 0) { return v.DecodeError(); } @@ -138,7 +135,7 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, bool D, size_t imm6, size_t Vd, b v.ir.SetVector(d, result); return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::asimd_SHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) { return ShiftRight(*this, U, D, imm6, Vd, L, Q, M, Vm, @@ -347,4 +344,4 @@ bool TranslatorVisitor::asimd_VCVT_fixed(bool U, bool D, size_t imm6, size_t Vd, return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/barrier.cpp b/src/dynarmic/frontend/A32/translate/impl/barrier.cpp index 7b7ad67c..b509cd0e 100644 --- a/src/dynarmic/frontend/A32/translate/impl/barrier.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/barrier.cpp @@ -24,4 +24,4 @@ bool TranslatorVisitor::arm_ISB(Imm<4> /*option*/) { return false; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/branch.cpp b/src/dynarmic/frontend/A32/translate/impl/branch.cpp index f838d4eb..0a004f2c 100644 --- a/src/dynarmic/frontend/A32/translate/impl/branch.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/branch.cpp @@ -3,9 +3,8 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/frontend/A32/translate/impl/translate.h" - #include "dynarmic/common/bit_util.h" +#include "dynarmic/frontend/A32/translate/impl/translate.h" namespace Dynarmic::A32 { @@ -85,4 +84,4 @@ bool TranslatorVisitor::arm_BXJ(Cond cond, Reg m) { return arm_BX(cond, m); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/coprocessor.cpp b/src/dynarmic/frontend/A32/translate/impl/coprocessor.cpp index 7ab7eba1..63a233f0 100644 --- a/src/dynarmic/frontend/A32/translate/impl/coprocessor.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/coprocessor.cpp @@ -163,4 +163,4 @@ bool TranslatorVisitor::arm_STC(Cond cond, bool p, bool u, bool d, bool w, Reg n return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/crc32.cpp b/src/dynarmic/frontend/A32/translate/impl/crc32.cpp index 7718f351..0dca5b84 100644 --- a/src/dynarmic/frontend/A32/translate/impl/crc32.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/crc32.cpp @@ -80,7 +80,7 @@ bool CRC32Variant(TranslatorVisitor& v, Cond cond, Imm<2> sz, Reg n, Reg d, Reg v.ir.SetRegister(d, result); return true; } -} // Anonymous namespace +} // Anonymous namespace // CRC32{B,H,W}{} , , bool TranslatorVisitor::arm_CRC32(Cond cond, Imm<2> sz, Reg n, Reg d, Reg m) { @@ -92,4 +92,4 @@ bool TranslatorVisitor::arm_CRC32C(Cond cond, Imm<2> sz, Reg n, Reg d, Reg m) { return CRC32Variant(*this, cond, sz, n, d, m, CRCType::Castagnoli); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/data_processing.cpp b/src/dynarmic/frontend/A32/translate/impl/data_processing.cpp index b4260cab..ef038d2b 100644 --- a/src/dynarmic/frontend/A32/translate/impl/data_processing.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/data_processing.cpp @@ -1233,4 +1233,4 @@ bool TranslatorVisitor::arm_TST_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Re return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/divide.cpp b/src/dynarmic/frontend/A32/translate/impl/divide.cpp index 358ac254..e144f03b 100644 --- a/src/dynarmic/frontend/A32/translate/impl/divide.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/divide.cpp @@ -9,8 +9,7 @@ namespace Dynarmic::A32 { namespace { using DivideFunction = IR::U32U64 (IREmitter::*)(const IR::U32U64&, const IR::U32U64&); -bool DivideOperation(TranslatorVisitor& v, Cond cond, Reg d, Reg m, Reg n, - DivideFunction fn) { +bool DivideOperation(TranslatorVisitor& v, Cond cond, Reg d, Reg m, Reg n, DivideFunction fn) { if (d == Reg::PC || m == Reg::PC || n == Reg::PC) { return v.UnpredictableInstruction(); } @@ -26,7 +25,7 @@ bool DivideOperation(TranslatorVisitor& v, Cond cond, Reg d, Reg m, Reg n, v.ir.SetRegister(d, result); return true; } -} // Anonymous namespace +} // Anonymous namespace // SDIV , , bool TranslatorVisitor::arm_SDIV(Cond cond, Reg d, Reg m, Reg n) { @@ -38,4 +37,4 @@ bool TranslatorVisitor::arm_UDIV(Cond cond, Reg d, Reg m, Reg n) { return DivideOperation(*this, cond, d, m, n, &IREmitter::UnsignedDiv); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/exception_generating.cpp b/src/dynarmic/frontend/A32/translate/impl/exception_generating.cpp index 547f0d49..f4b81777 100644 --- a/src/dynarmic/frontend/A32/translate/impl/exception_generating.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/exception_generating.cpp @@ -4,7 +4,6 @@ */ #include "dynarmic/frontend/A32/translate/impl/translate.h" - #include "dynarmic/interface/A32/config.h" namespace Dynarmic::A32 { @@ -42,4 +41,4 @@ bool TranslatorVisitor::arm_UDF() { return UndefinedInstruction(); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/extension.cpp b/src/dynarmic/frontend/A32/translate/impl/extension.cpp index ee85e4d0..9cd672b5 100644 --- a/src/dynarmic/frontend/A32/translate/impl/extension.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/extension.cpp @@ -226,4 +226,4 @@ bool TranslatorVisitor::arm_UXTH(Cond cond, Reg d, SignExtendRotation rotate, Re return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/hint.cpp b/src/dynarmic/frontend/A32/translate/impl/hint.cpp index 3923a553..72b58f3e 100644 --- a/src/dynarmic/frontend/A32/translate/impl/hint.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/hint.cpp @@ -4,7 +4,6 @@ */ #include "dynarmic/frontend/A32/translate/impl/translate.h" - #include "dynarmic/interface/A32/config.h" namespace Dynarmic::A32 { @@ -67,4 +66,4 @@ bool TranslatorVisitor::arm_YIELD() { return RaiseException(Exception::Yield); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/load_store.cpp b/src/dynarmic/frontend/A32/translate/impl/load_store.cpp index 3e413294..da606409 100644 --- a/src/dynarmic/frontend/A32/translate/impl/load_store.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/load_store.cpp @@ -229,7 +229,7 @@ bool TranslatorVisitor::arm_LDRD_lit(Cond cond, bool U, Reg t, Imm<4> imm8a, Imm return UnpredictableInstruction(); } - if (t+1 == Reg::PC) { + if (t + 1 == Reg::PC) { return UnpredictableInstruction(); } @@ -237,7 +237,7 @@ bool TranslatorVisitor::arm_LDRD_lit(Cond cond, bool U, Reg t, Imm<4> imm8a, Imm return true; } - const Reg t2 = t+1; + const Reg t2 = t + 1; const u32 imm32 = concatenate(imm8a, imm8b).ZeroExtend(); const bool add = U; @@ -266,11 +266,11 @@ bool TranslatorVisitor::arm_LDRD_imm(Cond cond, bool P, bool U, bool W, Reg n, R return UnpredictableInstruction(); } - if ((!P || W) && (n == t || n == t+1)) { + if ((!P || W) && (n == t || n == t + 1)) { return UnpredictableInstruction(); } - if (t+1 == Reg::PC) { + if (t + 1 == Reg::PC) { return UnpredictableInstruction(); } @@ -278,7 +278,7 @@ bool TranslatorVisitor::arm_LDRD_imm(Cond cond, bool P, bool U, bool W, Reg n, R return true; } - const Reg t2 = t+1; + const Reg t2 = t + 1; const u32 imm32 = concatenate(imm8a, imm8b).ZeroExtend(); const auto offset = ir.Imm32(imm32); @@ -303,11 +303,11 @@ bool TranslatorVisitor::arm_LDRD_reg(Cond cond, bool P, bool U, bool W, Reg n, R return UnpredictableInstruction(); } - if (t+1 == Reg::PC || m == Reg::PC || m == t || m == t+1) { + if (t + 1 == Reg::PC || m == Reg::PC || m == t || m == t + 1) { return UnpredictableInstruction(); } - if ((!P || W) && (n == Reg::PC || n == t || n == t+1)) { + if ((!P || W) && (n == Reg::PC || n == t || n == t + 1)) { return UnpredictableInstruction(); } @@ -315,7 +315,7 @@ bool TranslatorVisitor::arm_LDRD_reg(Cond cond, bool P, bool U, bool W, Reg n, R return true; } - const Reg t2 = t+1; + const Reg t2 = t + 1; const auto offset = ir.GetRegister(m); const auto address_a = GetAddress(ir, P, U, W, n, offset); const auto address_b = ir.Add(address_a, ir.Imm32(4)); @@ -931,4 +931,4 @@ bool TranslatorVisitor::arm_STM_usr() { return InterpretThisInstruction(); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/misc.cpp b/src/dynarmic/frontend/A32/translate/impl/misc.cpp index e8ace86c..f4969cd7 100644 --- a/src/dynarmic/frontend/A32/translate/impl/misc.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/misc.cpp @@ -3,9 +3,8 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/frontend/A32/translate/impl/translate.h" - #include "dynarmic/common/bit_util.h" +#include "dynarmic/frontend/A32/translate/impl/translate.h" namespace Dynarmic::A32 { @@ -176,4 +175,4 @@ bool TranslatorVisitor::arm_UBFX(Cond cond, Imm<5> widthm1, Reg d, Imm<5> lsb, R return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/multiply.cpp b/src/dynarmic/frontend/A32/translate/impl/multiply.cpp index 55709d16..3af0600d 100644 --- a/src/dynarmic/frontend/A32/translate/impl/multiply.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/multiply.cpp @@ -66,7 +66,6 @@ bool TranslatorVisitor::arm_MUL(Cond cond, bool S, Reg d, Reg m, Reg n) { return true; } - // SMLAL{S} , , , bool TranslatorVisitor::arm_SMLAL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) { if (dLo == Reg::PC || dHi == Reg::PC || n == Reg::PC || m == Reg::PC) { @@ -608,4 +607,4 @@ bool TranslatorVisitor::arm_SMUSD(Cond cond, Reg d, Reg m, bool M, Reg n) { return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/packing.cpp b/src/dynarmic/frontend/A32/translate/impl/packing.cpp index 59bd6dc9..651af188 100644 --- a/src/dynarmic/frontend/A32/translate/impl/packing.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/packing.cpp @@ -43,4 +43,4 @@ bool TranslatorVisitor::arm_PKHTB(Cond cond, Reg n, Reg d, Imm<5> imm5, Reg m) { return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/parallel.cpp b/src/dynarmic/frontend/A32/translate/impl/parallel.cpp index 2439bcc0..8f036c6c 100644 --- a/src/dynarmic/frontend/A32/translate/impl/parallel.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/parallel.cpp @@ -122,7 +122,7 @@ bool TranslatorVisitor::arm_UADD8(Cond cond, Reg n, Reg d, Reg m) { // UADD16 , , bool TranslatorVisitor::arm_UADD16(Cond cond, Reg n, Reg d, Reg m) { if (d == Reg::PC || n == Reg::PC || m == Reg::PC) { - return UnpredictableInstruction(); + return UnpredictableInstruction(); } if (!ArmConditionPassed(cond)) { @@ -183,7 +183,7 @@ bool TranslatorVisitor::arm_USAD8(Cond cond, Reg d, Reg m, Reg n) { } // USADA8 , , , -bool TranslatorVisitor::arm_USADA8(Cond cond, Reg d, Reg a, Reg m, Reg n){ +bool TranslatorVisitor::arm_USADA8(Cond cond, Reg d, Reg a, Reg m, Reg n) { if (d == Reg::PC || n == Reg::PC || m == Reg::PC) { return UnpredictableInstruction(); } @@ -534,4 +534,4 @@ bool TranslatorVisitor::arm_UHSUB16(Cond cond, Reg n, Reg d, Reg m) { return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/reversal.cpp b/src/dynarmic/frontend/A32/translate/impl/reversal.cpp index c494ec8c..c6d2c7f3 100644 --- a/src/dynarmic/frontend/A32/translate/impl/reversal.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/reversal.cpp @@ -86,4 +86,4 @@ bool TranslatorVisitor::arm_REVSH(Cond cond, Reg d, Reg m) { return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/saturated.cpp b/src/dynarmic/frontend/A32/translate/impl/saturated.cpp index 120e0a3b..43dcf105 100644 --- a/src/dynarmic/frontend/A32/translate/impl/saturated.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/saturated.cpp @@ -282,4 +282,4 @@ bool TranslatorVisitor::arm_UQSAX(Cond cond, Reg n, Reg d, Reg m) { return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp b/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp index d0d92595..866fa516 100644 --- a/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp @@ -3,9 +3,8 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/frontend/A32/translate/impl/translate.h" - #include "dynarmic/common/bit_util.h" +#include "dynarmic/frontend/A32/translate/impl/translate.h" namespace Dynarmic::A32 { @@ -118,4 +117,4 @@ bool TranslatorVisitor::arm_SRS() { return InterpretThisInstruction(); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/synchronization.cpp b/src/dynarmic/frontend/A32/translate/impl/synchronization.cpp index eb8c87be..689e0572 100644 --- a/src/dynarmic/frontend/A32/translate/impl/synchronization.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/synchronization.cpp @@ -60,7 +60,7 @@ bool TranslatorVisitor::arm_LDA(Cond cond, Reg n, Reg t) { } const auto address = ir.GetRegister(n); - ir.SetRegister(t, ir.ReadMemory32(address)); // AccType::Ordered + ir.SetRegister(t, ir.ReadMemory32(address)); // AccType::Ordered return true; } // LDAB , [] @@ -74,7 +74,7 @@ bool TranslatorVisitor::arm_LDAB(Cond cond, Reg n, Reg t) { } const auto address = ir.GetRegister(n); - ir.SetRegister(t, ir.ZeroExtendToWord(ir.ReadMemory8(address))); // AccType::Ordered + ir.SetRegister(t, ir.ZeroExtendToWord(ir.ReadMemory8(address))); // AccType::Ordered return true; } // LDAH , [] @@ -88,7 +88,7 @@ bool TranslatorVisitor::arm_LDAH(Cond cond, Reg n, Reg t) { } const auto address = ir.GetRegister(n); - ir.SetRegister(t, ir.ZeroExtendToWord(ir.ReadMemory16(address))); // AccType::Ordered + ir.SetRegister(t, ir.ZeroExtendToWord(ir.ReadMemory16(address))); // AccType::Ordered return true; } @@ -103,7 +103,7 @@ bool TranslatorVisitor::arm_LDAEX(Cond cond, Reg n, Reg t) { } const auto address = ir.GetRegister(n); - ir.SetRegister(t, ir.ExclusiveReadMemory32(address)); // AccType::Ordered + ir.SetRegister(t, ir.ExclusiveReadMemory32(address)); // AccType::Ordered return true; } @@ -118,7 +118,7 @@ bool TranslatorVisitor::arm_LDAEXB(Cond cond, Reg n, Reg t) { } const auto address = ir.GetRegister(n); - ir.SetRegister(t, ir.ZeroExtendByteToWord(ir.ExclusiveReadMemory8(address))); // AccType::Ordered + ir.SetRegister(t, ir.ZeroExtendByteToWord(ir.ExclusiveReadMemory8(address))); // AccType::Ordered return true; } @@ -133,10 +133,10 @@ bool TranslatorVisitor::arm_LDAEXD(Cond cond, Reg n, Reg t) { } const auto address = ir.GetRegister(n); - const auto [lo, hi] = ir.ExclusiveReadMemory64(address); // AccType::Ordered + const auto [lo, hi] = ir.ExclusiveReadMemory64(address); // AccType::Ordered // DO NOT SWAP hi AND lo IN BIG ENDIAN MODE, THIS IS CORRECT BEHAVIOUR ir.SetRegister(t, lo); - ir.SetRegister(t+1, hi); + ir.SetRegister(t + 1, hi); return true; } @@ -151,7 +151,7 @@ bool TranslatorVisitor::arm_LDAEXH(Cond cond, Reg n, Reg t) { } const auto address = ir.GetRegister(n); - ir.SetRegister(t, ir.ZeroExtendHalfToWord(ir.ExclusiveReadMemory16(address))); // AccType::Ordered + ir.SetRegister(t, ir.ZeroExtendHalfToWord(ir.ExclusiveReadMemory16(address))); // AccType::Ordered return true; } @@ -166,7 +166,7 @@ bool TranslatorVisitor::arm_STL(Cond cond, Reg n, Reg t) { } const auto address = ir.GetRegister(n); - ir.WriteMemory32(address, ir.GetRegister(t)); // AccType::Ordered + ir.WriteMemory32(address, ir.GetRegister(t)); // AccType::Ordered return true; } @@ -181,7 +181,7 @@ bool TranslatorVisitor::arm_STLB(Cond cond, Reg n, Reg t) { } const auto address = ir.GetRegister(n); - ir.WriteMemory8(address, ir.LeastSignificantByte(ir.GetRegister(t))); // AccType::Ordered + ir.WriteMemory8(address, ir.LeastSignificantByte(ir.GetRegister(t))); // AccType::Ordered return true; } @@ -196,7 +196,7 @@ bool TranslatorVisitor::arm_STLH(Cond cond, Reg n, Reg t) { } const auto address = ir.GetRegister(n); - ir.WriteMemory16(address, ir.LeastSignificantHalf(ir.GetRegister(t))); // AccType::Ordered + ir.WriteMemory16(address, ir.LeastSignificantHalf(ir.GetRegister(t))); // AccType::Ordered return true; } @@ -216,7 +216,7 @@ bool TranslatorVisitor::arm_STLEXB(Cond cond, Reg n, Reg d, Reg t) { const auto address = ir.GetRegister(n); const auto value = ir.LeastSignificantByte(ir.GetRegister(t)); - const auto passed = ir.ExclusiveWriteMemory8(address, value); // AccType::Ordered + const auto passed = ir.ExclusiveWriteMemory8(address, value); // AccType::Ordered ir.SetRegister(d, passed); return true; } @@ -226,7 +226,7 @@ bool TranslatorVisitor::arm_STLEXD(Cond cond, Reg n, Reg d, Reg t) { return UnpredictableInstruction(); } - if (d == n || d == t || d == t+1) { + if (d == n || d == t || d == t + 1) { return UnpredictableInstruction(); } @@ -238,7 +238,7 @@ bool TranslatorVisitor::arm_STLEXD(Cond cond, Reg n, Reg d, Reg t) { const auto address = ir.GetRegister(n); const auto value_lo = ir.GetRegister(t); const auto value_hi = ir.GetRegister(t2); - const auto passed = ir.ExclusiveWriteMemory64(address, value_lo, value_hi); // AccType::Ordered + const auto passed = ir.ExclusiveWriteMemory64(address, value_lo, value_hi); // AccType::Ordered ir.SetRegister(d, passed); return true; } @@ -259,7 +259,7 @@ bool TranslatorVisitor::arm_STLEXH(Cond cond, Reg n, Reg d, Reg t) { const auto address = ir.GetRegister(n); const auto value = ir.LeastSignificantHalf(ir.GetRegister(t)); - const auto passed = ir.ExclusiveWriteMemory16(address, value); // AccType::Ordered + const auto passed = ir.ExclusiveWriteMemory16(address, value); // AccType::Ordered ir.SetRegister(d, passed); return true; } @@ -329,7 +329,7 @@ bool TranslatorVisitor::arm_LDREXD(Cond cond, Reg n, Reg t) { const auto [lo, hi] = ir.ExclusiveReadMemory64(address); // DO NOT SWAP hi AND lo IN BIG ENDIAN MODE, THIS IS CORRECT BEHAVIOUR ir.SetRegister(t, lo); - ir.SetRegister(t+1, hi); + ir.SetRegister(t + 1, hi); return true; } @@ -396,7 +396,7 @@ bool TranslatorVisitor::arm_STREXD(Cond cond, Reg n, Reg d, Reg t) { return UnpredictableInstruction(); } - if (d == n || d == t || d == t+1) { + if (d == n || d == t || d == t + 1) { return UnpredictableInstruction(); } @@ -434,4 +434,4 @@ bool TranslatorVisitor::arm_STREXH(Cond cond, Reg n, Reg d, Reg t) { return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp index f95b828d..6e2899d2 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp @@ -4,7 +4,6 @@ */ #include "dynarmic/frontend/A32/translate/impl/translate.h" - #include "dynarmic/interface/A32/config.h" namespace Dynarmic::A32 { @@ -1052,4 +1051,4 @@ bool TranslatorVisitor::thumb16_B_t2(Imm<11> imm11) { return false; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_branch.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_branch.cpp index 909efdbc..82c07b20 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_branch.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_branch.cpp @@ -21,8 +21,8 @@ bool TranslatorVisitor::thumb32_BL_imm(Imm<1> S, Imm<10> hi, Imm<1> j1, Imm<1> j const s32 imm32 = static_cast((concatenate(S, i1, i2, hi, lo).SignExtend() << 1) + 4); const auto new_location = ir.current_location - .AdvancePC(imm32) - .AdvanceIT(); + .AdvancePC(imm32) + .AdvanceIT(); ir.SetTerm(IR::Term::LinkBlock{new_location}); return false; } @@ -45,9 +45,9 @@ bool TranslatorVisitor::thumb32_BLX_imm(Imm<1> S, Imm<10> hi, Imm<1> j1, Imm<1> const s32 imm32 = static_cast(concatenate(S, i1, i2, hi, lo).SignExtend() << 1); const auto new_location = ir.current_location - .SetPC(ir.AlignPC(4) + imm32) - .SetTFlag(false) - .AdvanceIT(); + .SetPC(ir.AlignPC(4) + imm32) + .SetTFlag(false) + .AdvanceIT(); ir.SetTerm(IR::Term::LinkBlock{new_location}); return false; } @@ -62,8 +62,8 @@ bool TranslatorVisitor::thumb32_B(Imm<1> S, Imm<10> hi, Imm<1> j1, Imm<1> j2, Im const s32 imm32 = static_cast((concatenate(S, i1, i2, hi, lo).SignExtend() << 1) + 4); const auto new_location = ir.current_location - .AdvancePC(imm32) - .AdvanceIT(); + .AdvancePC(imm32) + .AdvanceIT(); ir.SetTerm(IR::Term::LinkBlock{new_location}); return false; } @@ -76,13 +76,13 @@ bool TranslatorVisitor::thumb32_B_cond(Imm<1> S, Cond cond, Imm<6> hi, Imm<1> i1 // Note: i1 and i2 were not inverted from encoding and are opposite compared to the other B instructions. const s32 imm32 = static_cast((concatenate(S, i2, i1, hi, lo).SignExtend() << 1) + 4); const auto then_location = ir.current_location - .AdvancePC(imm32) - .AdvanceIT(); + .AdvancePC(imm32) + .AdvanceIT(); const auto else_location = ir.current_location - .AdvancePC(4) - .AdvanceIT(); + .AdvancePC(4) + .AdvanceIT(); ir.SetTerm(IR::Term::If{cond, IR::Term::LinkBlock{then_location}, IR::Term::LinkBlock{else_location}}); return false; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_control.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_control.cpp index 96a46950..52cc6e5a 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_control.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_control.cpp @@ -123,4 +123,4 @@ bool TranslatorVisitor::thumb32_MRS_reg(bool read_spsr, Reg d) { return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_coprocessor.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_coprocessor.cpp index 1261c945..23cf5fa8 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_coprocessor.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_coprocessor.cpp @@ -72,4 +72,4 @@ bool TranslatorVisitor::thumb32_MRC(bool two, size_t opc1, CoprocReg CRn, Reg t, return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp index da7a6552..f7c710c7 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp @@ -280,4 +280,4 @@ bool TranslatorVisitor::thumb32_RSB_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Re return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp index b17611e4..ffe5e56d 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp @@ -3,10 +3,9 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/frontend/A32/translate/impl/translate.h" - #include "dynarmic/common/assert.h" #include "dynarmic/common/bit_util.h" +#include "dynarmic/frontend/A32/translate/impl/translate.h" namespace Dynarmic::A32 { static IR::U32 Pack2x16To1x32(A32::IREmitter& ir, IR::U32 lo, IR::U32 hi) { @@ -229,4 +228,4 @@ bool TranslatorVisitor::thumb32_USAT16(Reg n, Reg d, Imm<4> sat_imm) { return Saturation16(*this, n, d, sat_imm.ZeroExtend(), &IREmitter::UnsignedSaturation); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_register.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_register.cpp index 3427e021..0ef5403d 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_register.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_register.cpp @@ -32,7 +32,7 @@ bool ShiftInstruction(TranslatorVisitor& v, Reg m, Reg d, Reg s, bool S, ShiftFu v.ir.SetRegister(d, result_carry.result); return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::thumb32_ASR_reg(bool S, Reg m, Reg d, Reg s) { return ShiftInstruction(*this, m, d, s, S, &IREmitter::ArithmeticShiftRight); @@ -205,4 +205,4 @@ bool TranslatorVisitor::thumb32_UXTAH(Reg n, Reg d, SignExtendRotation rotate, R return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp index fb064d32..82a25fad 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp @@ -289,4 +289,4 @@ bool TranslatorVisitor::thumb32_RSB_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2 return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_load_byte.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_load_byte.cpp index 8932f308..b83f8ee7 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_load_byte.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_load_byte.cpp @@ -4,7 +4,6 @@ */ #include "dynarmic/frontend/A32/translate/impl/translate.h" - #include "dynarmic/interface/A32/config.h" namespace Dynarmic::A32 { @@ -28,8 +27,7 @@ static bool PLIHandler(TranslatorVisitor& v) { using ExtensionFunction = IR::U32 (IREmitter::*)(const IR::U8&); -static bool LoadByteLiteral(TranslatorVisitor& v, bool U, Reg t, Imm<12> imm12, - ExtensionFunction ext_fn) { +static bool LoadByteLiteral(TranslatorVisitor& v, bool U, Reg t, Imm<12> imm12, ExtensionFunction ext_fn) { const u32 imm32 = imm12.ZeroExtend(); const u32 base = v.ir.AlignPC(4); const u32 address = U ? (base + imm32) : (base - imm32); @@ -39,8 +37,7 @@ static bool LoadByteLiteral(TranslatorVisitor& v, bool U, Reg t, Imm<12> imm12, return true; } -static bool LoadByteRegister(TranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Reg m, - ExtensionFunction ext_fn) { +static bool LoadByteRegister(TranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Reg m, ExtensionFunction ext_fn) { if (m == Reg::PC) { return v.UnpredictableInstruction(); } @@ -55,8 +52,7 @@ static bool LoadByteRegister(TranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Re return true; } -static bool LoadByteImmediate(TranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W, Imm<12> imm12, - ExtensionFunction ext_fn) { +static bool LoadByteImmediate(TranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W, Imm<12> imm12, ExtensionFunction ext_fn) { const u32 imm32 = imm12.ZeroExtend(); const IR::U32 reg_n = v.ir.GetRegister(n); const IR::U32 offset_address = U ? v.ir.Add(reg_n, v.ir.Imm32(imm32)) @@ -199,4 +195,4 @@ bool TranslatorVisitor::thumb32_LDRSBT(Reg n, Reg t, Imm<8> imm8) { return thumb32_LDRSB_imm8(n, t, true, true, false, imm8); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_load_halfword.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_load_halfword.cpp index 07a93403..8a589b99 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_load_halfword.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_load_halfword.cpp @@ -9,8 +9,7 @@ namespace Dynarmic::A32 { using ExtensionFunction = IR::U32 (IREmitter::*)(const IR::U16&); -static bool LoadHalfLiteral(TranslatorVisitor& v, bool U, Reg t, Imm<12> imm12, - ExtensionFunction ext_fn) { +static bool LoadHalfLiteral(TranslatorVisitor& v, bool U, Reg t, Imm<12> imm12, ExtensionFunction ext_fn) { const auto imm32 = imm12.ZeroExtend(); const auto base = v.ir.AlignPC(4); const auto address = U ? (base + imm32) : (base - imm32); @@ -20,8 +19,7 @@ static bool LoadHalfLiteral(TranslatorVisitor& v, bool U, Reg t, Imm<12> imm12, return true; } -static bool LoadHalfRegister(TranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Reg m, - ExtensionFunction ext_fn) { +static bool LoadHalfRegister(TranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Reg m, ExtensionFunction ext_fn) { if (m == Reg::PC) { return v.UnpredictableInstruction(); } @@ -36,8 +34,7 @@ static bool LoadHalfRegister(TranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Re return true; } -static bool LoadHalfImmediate(TranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W, - Imm<12> imm12, ExtensionFunction ext_fn) { +static bool LoadHalfImmediate(TranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W, Imm<12> imm12, ExtensionFunction ext_fn) { const u32 imm32 = imm12.ZeroExtend(); const IR::U32 reg_n = v.ir.GetRegister(n); const IR::U32 offset_address = U ? v.ir.Add(reg_n, v.ir.Imm32(imm32)) @@ -138,4 +135,4 @@ bool TranslatorVisitor::thumb32_LDRSHT(Reg n, Reg t, Imm<8> imm8) { return thumb32_LDRSH_imm8(n, t, true, true, false, imm8); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_dual.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_dual.cpp index 16b24a38..7232954f 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_dual.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_dual.cpp @@ -3,9 +3,8 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/frontend/A32/translate/impl/translate.h" - #include "dynarmic/common/bit_util.h" +#include "dynarmic/frontend/A32/translate/impl/translate.h" namespace Dynarmic::A32 { static bool ITBlockCheck(const A32::IREmitter& ir) { @@ -40,8 +39,7 @@ static bool TableBranch(TranslatorVisitor& v, Reg n, Reg m, bool half) { return false; } -static bool LoadDualImmediate(TranslatorVisitor& v, bool P, bool U, bool W, - Reg n, Reg t, Reg t2, Imm<8> imm8) { +static bool LoadDualImmediate(TranslatorVisitor& v, bool P, bool U, bool W, Reg n, Reg t, Reg t2, Imm<8> imm8) { if (W && (n == t || n == t2)) { return v.UnpredictableInstruction(); } @@ -255,4 +253,4 @@ bool TranslatorVisitor::thumb32_TBH(Reg n, Reg m) { return TableBranch(*this, n, m, true); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_multiple.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_multiple.cpp index 70895f27..f7c8490c 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_multiple.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_multiple.cpp @@ -3,17 +3,15 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/frontend/A32/translate/impl/translate.h" - #include "dynarmic/common/bit_util.h" +#include "dynarmic/frontend/A32/translate/impl/translate.h" namespace Dynarmic::A32 { static bool ITBlockCheck(const A32::IREmitter& ir) { return ir.current_location.IT().IsInITBlock() && !ir.current_location.IT().IsLastInITBlock(); } -static bool LDMHelper(A32::IREmitter& ir, bool W, Reg n, u32 list, - const IR::U32& start_address, const IR::U32& writeback_address) { +static bool LDMHelper(A32::IREmitter& ir, bool W, Reg n, u32 list, const IR::U32& start_address, const IR::U32& writeback_address) { auto address = start_address; for (size_t i = 0; i <= 14; i++) { if (Common::Bit(i, list)) { @@ -37,8 +35,7 @@ static bool LDMHelper(A32::IREmitter& ir, bool W, Reg n, u32 list, return true; } -static bool STMHelper(A32::IREmitter& ir, bool W, Reg n, u32 list, - const IR::U32& start_address, const IR::U32& writeback_address) { +static bool STMHelper(A32::IREmitter& ir, bool W, Reg n, u32 list, const IR::U32& start_address, const IR::U32& writeback_address) { auto address = start_address; for (size_t i = 0; i <= 14; i++) { if (Common::Bit(i, list)) { @@ -148,4 +145,4 @@ bool TranslatorVisitor::thumb32_STMDB(bool W, Reg n, Imm<15> reg_list) { return STMHelper(ir, W, n, regs_imm, start_address, start_address); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_load_word.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_load_word.cpp index d9cf5f5c..b8288c25 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_load_word.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_load_word.cpp @@ -131,4 +131,4 @@ bool TranslatorVisitor::thumb32_LDRT(Reg n, Reg t, Imm<8> imm8) { return thumb32_LDR_imm8(n, t, true, true, false, imm8); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_long_multiply.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_long_multiply.cpp index 2a0980ea..210248b2 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_long_multiply.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_long_multiply.cpp @@ -21,7 +21,7 @@ bool DivideOperation(TranslatorVisitor& v, Reg d, Reg m, Reg n, DivideFunction f v.ir.SetRegister(d, result); return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::thumb32_SDIV(Reg n, Reg d, Reg m) { return DivideOperation(*this, d, m, n, &IREmitter::SignedDiv); @@ -219,4 +219,4 @@ bool TranslatorVisitor::thumb32_UMAAL(Reg n, Reg dLo, Reg dHi, Reg m) { return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_misc.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_misc.cpp index b0703d54..b772fe3d 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_misc.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_misc.cpp @@ -154,4 +154,4 @@ bool TranslatorVisitor::thumb32_SEL(Reg n, Reg d, Reg m) { return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_multiply.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_multiply.cpp index ad891dbe..bcbcf73c 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_multiply.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_multiply.cpp @@ -309,4 +309,4 @@ bool TranslatorVisitor::thumb32_USADA8(Reg n, Reg a, Reg d, Reg m) { return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_parallel.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_parallel.cpp index 9a74604b..e511060f 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_parallel.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_parallel.cpp @@ -518,4 +518,4 @@ bool TranslatorVisitor::thumb32_UHSUB16(Reg n, Reg d, Reg m) { return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp index bc8e3c59..963fb3c2 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp @@ -7,7 +7,7 @@ namespace Dynarmic::A32 { -template +template static bool StoreRegister(TranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Reg m, StoreRegFn store_fn) { if (n == Reg::PC) { return v.UndefinedInstruction(); @@ -43,8 +43,7 @@ static void StoreImmWordFn(TranslatorVisitor& v, const IR::U32& address, const I v.ir.WriteMemory32(address, data); } -static bool StoreImmediate(TranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W, Imm<12> imm12, - StoreImmFn store_fn) { +static bool StoreImmediate(TranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W, Imm<12> imm12, StoreImmFn store_fn) { const auto imm32 = imm12.ZeroExtend(); const auto reg_n = v.ir.GetRegister(n); const auto reg_t = v.ir.GetRegister(t); @@ -221,4 +220,4 @@ bool TranslatorVisitor::thumb32_STR_reg(Reg n, Reg t, Imm<2> imm2, Reg m) { }); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/translate.cpp b/src/dynarmic/frontend/A32/translate/impl/translate.cpp index 188cab35..b898147f 100644 --- a/src/dynarmic/frontend/A32/translate/impl/translate.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/translate.cpp @@ -106,4 +106,4 @@ IR::ResultAndCarry TranslatorVisitor::EmitRegShift(IR::U32 value, Shift UNREACHABLE(); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/translate.h b/src/dynarmic/frontend/A32/translate/impl/translate.h index 7274f6e3..3b978f6a 100644 --- a/src/dynarmic/frontend/A32/translate/impl/translate.h +++ b/src/dynarmic/frontend/A32/translate/impl/translate.h @@ -7,12 +7,12 @@ #include "dynarmic/common/assert.h" #include "dynarmic/common/bit_util.h" -#include "dynarmic/frontend/imm.h" #include "dynarmic/frontend/A32/ir_emitter.h" #include "dynarmic/frontend/A32/location_descriptor.h" #include "dynarmic/frontend/A32/translate/conditional_state.h" #include "dynarmic/frontend/A32/translate/translate.h" #include "dynarmic/frontend/A32/types.h" +#include "dynarmic/frontend/imm.h" namespace Dynarmic::A32 { @@ -22,8 +22,7 @@ struct TranslatorVisitor final { using instruction_return_type = bool; explicit TranslatorVisitor(IR::Block& block, LocationDescriptor descriptor, const TranslationOptions& options) - : ir(block, descriptor, options.arch_version), options(options) - {} + : ir(block, descriptor, options.arch_version), options(options) {} A32::IREmitter ir; ConditionalState cond_state = ConditionalState::None; @@ -63,7 +62,7 @@ struct TranslatorVisitor final { ImmAndCarry ThumbExpandImm_C(Imm<1> i, Imm<3> imm3, Imm<8> imm8, IR::U1 carry_in) { const Imm<12> imm12 = concatenate(i, imm3, imm8); if (imm12.Bits<10, 11>() == 0) { - const u32 imm32 = [&]{ + const u32 imm32 = [&] { const u32 imm8 = imm12.Bits<0, 7>(); switch (imm12.Bits<8, 9>()) { case 0b00: @@ -93,8 +92,10 @@ struct TranslatorVisitor final { IR::ResultAndCarry EmitImmShift(IR::U32 value, ShiftType type, Imm<3> imm3, Imm<2> imm2, IR::U1 carry_in); IR::ResultAndCarry EmitImmShift(IR::U32 value, ShiftType type, Imm<5> imm5, IR::U1 carry_in); IR::ResultAndCarry EmitRegShift(IR::U32 value, ShiftType type, IR::U8 amount, IR::U1 carry_in); - template bool EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg n, ExtReg m, const FnT& fn); - template bool EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg m, const FnT& fn); + template + bool EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg n, ExtReg m, const FnT& fn); + template + bool EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg m, const FnT& fn); // Barrier instructions bool arm_DMB(Imm<4> option); @@ -821,8 +822,7 @@ struct TranslatorVisitor final { bool vfp_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8); // Advanced SIMD one register, modified immediate - bool asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c, Imm<1> d, size_t Vd, - Imm<4> cmode, bool Q, bool op, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h); + bool asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c, Imm<1> d, size_t Vd, Imm<4> cmode, bool Q, bool op, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h); // Advanced SIMD three register with same length bool asimd_VHADD(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); @@ -959,4 +959,4 @@ struct TranslatorVisitor final { bool v8_VLD_single(bool D, Reg n, size_t Vd, size_t sz, size_t nn, size_t index_align, Reg m); }; -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/impl/vfp.cpp b/src/dynarmic/frontend/A32/translate/impl/vfp.cpp index 35237fff..c3622533 100644 --- a/src/dynarmic/frontend/A32/translate/impl/vfp.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/vfp.cpp @@ -3,13 +3,13 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/frontend/A32/translate/impl/translate.h" - #include +#include "dynarmic/frontend/A32/translate/impl/translate.h" + namespace Dynarmic::A32 { -template +template bool TranslatorVisitor::EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg n, ExtReg m, const FnT& fn) { if (!ir.current_location.FPSCR().Stride()) { return UnpredictableInstruction(); @@ -76,9 +76,9 @@ bool TranslatorVisitor::EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg n, ExtR return true; } -template +template bool TranslatorVisitor::EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg m, const FnT& fn) { - return EmitVfpVectorOperation(sz, d, ExtReg::S0, m, [fn](ExtReg d, ExtReg, ExtReg m){ + return EmitVfpVectorOperation(sz, d, ExtReg::S0, m, [fn](ExtReg d, ExtReg, ExtReg m) { fn(d, m); }); } @@ -462,7 +462,7 @@ bool TranslatorVisitor::vfp_VMOV_2u32_2f32(Cond cond, Reg t2, Reg t, bool M, siz } ir.SetExtendedRegister(m, ir.GetRegister(t)); - ir.SetExtendedRegister(m+1, ir.GetRegister(t2)); + ir.SetExtendedRegister(m + 1, ir.GetRegister(t2)); return true; } @@ -482,7 +482,7 @@ bool TranslatorVisitor::vfp_VMOV_2f32_2u32(Cond cond, Reg t2, Reg t, bool M, siz } ir.SetRegister(t, ir.GetExtendedRegister(m)); - ir.SetRegister(t2, ir.GetExtendedRegister(m+1)); + ir.SetRegister(t2, ir.GetExtendedRegister(m + 1)); return true; } @@ -940,7 +940,7 @@ bool TranslatorVisitor::vfp_VCVT_f_to_f(Cond cond, bool D, size_t Vd, bool sz, b return true; } - const auto d = ToExtReg(!sz, Vd, D); // Destination is of opposite size to source + const auto d = ToExtReg(!sz, Vd, D); // Destination is of opposite size to source const auto m = ToExtReg(sz, Vm, M); const auto reg_m = ir.GetExtendedRegister(m); const auto rounding_mode = ir.current_location.FPSCR().RMode(); @@ -970,13 +970,13 @@ bool TranslatorVisitor::vfp_VCVT_from_int(Cond cond, bool D, size_t Vd, bool sz, if (sz) { const auto result = is_signed - ? ir.FPSignedFixedToDouble(reg_m, 0, rounding_mode) - : ir.FPUnsignedFixedToDouble(reg_m, 0, rounding_mode); + ? ir.FPSignedFixedToDouble(reg_m, 0, rounding_mode) + : ir.FPUnsignedFixedToDouble(reg_m, 0, rounding_mode); ir.SetExtendedRegister(d, result); } else { const auto result = is_signed - ? ir.FPSignedFixedToSingle(reg_m, 0, rounding_mode) - : ir.FPUnsignedFixedToSingle(reg_m, 0, rounding_mode); + ? ir.FPSignedFixedToSingle(reg_m, 0, rounding_mode) + : ir.FPUnsignedFixedToSingle(reg_m, 0, rounding_mode); ir.SetExtendedRegister(d, result); } @@ -1168,7 +1168,7 @@ bool TranslatorVisitor::vfp_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm<8> i const ExtReg d = ToExtReg(sz, Vd, D); const size_t regs = sz ? imm8.ZeroExtend() >> 1 : imm8.ZeroExtend(); - if (regs == 0 || RegNumber(d)+regs > 32) { + if (regs == 0 || RegNumber(d) + regs > 32) { return UnpredictableInstruction(); } @@ -1209,7 +1209,7 @@ bool TranslatorVisitor::vfp_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm<8> const ExtReg d = ToExtReg(sz, Vd, D); const size_t regs = sz ? imm8.ZeroExtend() >> 1 : imm8.ZeroExtend(); - if (regs == 0 || RegNumber(d)+regs > 32) { + if (regs == 0 || RegNumber(d) + regs > 32) { return UnpredictableInstruction(); } @@ -1230,7 +1230,8 @@ bool TranslatorVisitor::vfp_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm<8> const auto reg_d = ir.GetExtendedRegister(d + i); auto lo = ir.LeastSignificantWord(reg_d); auto hi = ir.MostSignificantWord(reg_d).result; - if (ir.current_location.EFlag()) std::swap(lo, hi); + if (ir.current_location.EFlag()) + std::swap(lo, hi); ir.WriteMemory32(address, lo); address = ir.Add(address, ir.Imm32(4)); ir.WriteMemory32(address, hi); @@ -1318,7 +1319,7 @@ bool TranslatorVisitor::vfp_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, R const auto d = ToExtReg(true, Vd, D); const size_t regs = imm8.ZeroExtend() / 2; - if (regs == 0 || regs > 16 || A32::RegNumber(d)+regs > 32) { + if (regs == 0 || regs > 16 || A32::RegNumber(d) + regs > 32) { return UnpredictableInstruction(); } @@ -1370,7 +1371,7 @@ bool TranslatorVisitor::vfp_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, R const auto d = ToExtReg(false, Vd, D); const size_t regs = imm8.ZeroExtend(); - if (regs == 0 || A32::RegNumber(d)+regs > 32) { + if (regs == 0 || A32::RegNumber(d) + regs > 32) { return UnpredictableInstruction(); } @@ -1413,7 +1414,7 @@ bool TranslatorVisitor::vfp_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, R const auto d = ToExtReg(true, Vd, D); const size_t regs = imm8.ZeroExtend() / 2; - if (regs == 0 || regs > 16 || A32::RegNumber(d)+regs > 32) { + if (regs == 0 || regs > 16 || A32::RegNumber(d) + regs > 32) { return UnpredictableInstruction(); } @@ -1463,7 +1464,7 @@ bool TranslatorVisitor::vfp_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, R const auto d = ToExtReg(false, Vd, D); const size_t regs = imm8.ZeroExtend(); - if (regs == 0 || A32::RegNumber(d)+regs > 32) { + if (regs == 0 || A32::RegNumber(d) + regs > 32) { return UnpredictableInstruction(); } @@ -1485,4 +1486,4 @@ bool TranslatorVisitor::vfp_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, R return true; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/translate.cpp b/src/dynarmic/frontend/A32/translate/translate.cpp index 5e7971a8..5780b24f 100644 --- a/src/dynarmic/frontend/A32/translate/translate.cpp +++ b/src/dynarmic/frontend/A32/translate/translate.cpp @@ -24,4 +24,4 @@ bool TranslateSingleInstruction(IR::Block& block, LocationDescriptor descriptor, return (descriptor.TFlag() ? TranslateSingleThumbInstruction : TranslateSingleArmInstruction)(block, descriptor, instruction); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/translate.h b/src/dynarmic/frontend/A32/translate/translate.h index f0502735..9af458e6 100644 --- a/src/dynarmic/frontend/A32/translate/translate.h +++ b/src/dynarmic/frontend/A32/translate/translate.h @@ -9,15 +9,13 @@ namespace Dynarmic::IR { class Block; -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR namespace Dynarmic::A32 { class LocationDescriptor; struct TranslateCallbacks; -using MemoryReadCodeFuncType = std::function; - struct TranslationOptions { ArchVersion arch_version; @@ -50,4 +48,4 @@ IR::Block Translate(LocationDescriptor descriptor, TranslateCallbacks* tcb, cons */ bool TranslateSingleInstruction(IR::Block& block, LocationDescriptor descriptor, u32 instruction); -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/translate_arm.cpp b/src/dynarmic/frontend/A32/translate/translate_arm.cpp index 8e90771e..24c7ced8 100644 --- a/src/dynarmic/frontend/A32/translate/translate_arm.cpp +++ b/src/dynarmic/frontend/A32/translate/translate_arm.cpp @@ -93,4 +93,4 @@ bool TranslateSingleArmInstruction(IR::Block& block, LocationDescriptor descript return should_continue; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/translate_callbacks.h b/src/dynarmic/frontend/A32/translate/translate_callbacks.h index 612cedaf..eeffd9d4 100644 --- a/src/dynarmic/frontend/A32/translate/translate_callbacks.h +++ b/src/dynarmic/frontend/A32/translate/translate_callbacks.h @@ -22,4 +22,4 @@ struct TranslateCallbacks { virtual void PreCodeTranslationHook(bool is_thumb, VAddr pc, A32::IREmitter& ir) = 0; }; -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/translate/translate_thumb.cpp b/src/dynarmic/frontend/A32/translate/translate_thumb.cpp index 99482340..4d040bd3 100644 --- a/src/dynarmic/frontend/A32/translate/translate_thumb.cpp +++ b/src/dynarmic/frontend/A32/translate/translate_thumb.cpp @@ -24,7 +24,8 @@ namespace Dynarmic::A32 { namespace { enum class ThumbInstSize { - Thumb16, Thumb32 + Thumb16, + Thumb32 }; bool IsThumb16(u16 first_part) { @@ -34,9 +35,9 @@ bool IsThumb16(u16 first_part) { bool IsUnconditionalInstruction(bool is_thumb_16, u32 instruction) { if (!is_thumb_16) return false; - if ((instruction & 0xFF00) == 0b10111110'00000000) // BKPT + if ((instruction & 0xFF00) == 0b10111110'00000000) // BKPT return true; - if ((instruction & 0xFFC0) == 0b10111010'10000000) // HLT + if ((instruction & 0xFFC0) == 0b10111010'10000000) // HLT return true; return false; } @@ -76,14 +77,14 @@ u32 ConvertASIMDInstruction(u32 thumb_instruction) { return 0xF4000000 | (thumb_instruction & 0x00FFFFFF); } - return 0xF7F0A000; // UDF + return 0xF7F0A000; // UDF } bool MaybeVFPOrASIMDInstruction(u32 thumb_instruction) { return (thumb_instruction & 0xEC000000) == 0xEC000000 || (thumb_instruction & 0xFF100000) == 0xF9000000; } -} // local namespace +} // namespace IR::Block TranslateThumb(LocationDescriptor descriptor, TranslateCallbacks* tcb, const TranslationOptions& options) { const bool single_step = descriptor.SingleStepping(); @@ -193,4 +194,4 @@ bool TranslateSingleThumbInstruction(IR::Block& block, LocationDescriptor descri return should_continue; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/types.cpp b/src/dynarmic/frontend/A32/types.cpp index 5d255e5b..b0c77d95 100644 --- a/src/dynarmic/frontend/A32/types.cpp +++ b/src/dynarmic/frontend/A32/types.cpp @@ -3,53 +3,42 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/frontend/A32/types.h" + #include #include #include "dynarmic/common/bit_util.h" -#include "dynarmic/frontend/A32/types.h" namespace Dynarmic::A32 { const char* CondToString(Cond cond, bool explicit_al) { - static constexpr std::array cond_strs = { - "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", - "hi", "ls", "ge", "lt", "gt", "le", "al", "nv", - }; + static constexpr std::array cond_strs = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"}; return (!explicit_al && cond == Cond::AL) ? "" : cond_strs.at(static_cast(cond)); } const char* RegToString(Reg reg) { - static constexpr std::array reg_strs = { - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" - }; + static constexpr std::array reg_strs = {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc"}; return reg_strs.at(static_cast(reg)); } const char* ExtRegToString(ExtReg reg) { static constexpr std::array reg_strs = { - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", - "s9", "s10", "s11", "s12", "s13", "s14", "s15", "s16", - "s17", "s18", "s19", "s20", "s21", "s22", "s23", "s24", - "s25", "s26", "s27", "s28", "s29", "s30", "s31", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", "s16", + "s17", "s18", "s19", "s20", "s21", "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", - "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", - "d9", "d10", "d11", "d12", "d13", "d14", "d15", "d16", - "d17", "d18", "d19", "d20", "d21", "d22", "d23", "d24", - "d25", "d26", "d27", "d28", "d29", "d30", "d31", + "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", "d16", + "d17", "d18", "d19", "d20", "d21", "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", - "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8", - "q9", "q10", "q11", "q12", "q13", "q14", "q15", "q16", - }; + "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", "q16"}; return reg_strs.at(static_cast(reg)); } const char* CoprocRegToString(CoprocReg reg) { static constexpr std::array reg_strs = { "c0", "c1", "c2", "c3", "c4", "c5", "c6", "c7", "c8", - "c9", "c10", "c11", "c12", "c13", "c14", "c15" - }; + "c9", "c10", "c11", "c12", "c13", "c14", "c15"}; return reg_strs.at(static_cast(reg)); } @@ -88,4 +77,4 @@ std::ostream& operator<<(std::ostream& o, RegList reg_list) { return o; } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A32/types.h b/src/dynarmic/frontend/A32/types.h index fb6fc21d..ff30cc76 100644 --- a/src/dynarmic/frontend/A32/types.h +++ b/src/dynarmic/frontend/A32/types.h @@ -19,7 +19,22 @@ namespace Dynarmic::A32 { using Cond = IR::Cond; enum class Reg { - R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, + R0, + R1, + R2, + R3, + R4, + R5, + R6, + R7, + R8, + R9, + R10, + R11, + R12, + R13, + R14, + R15, SP = R13, LR = R14, PC = R15, @@ -27,16 +42,11 @@ enum class Reg { }; enum class ExtReg { - S0, S1, S2, S3, S4, S5, S6, S7, - S8, S9, S10, S11, S12, S13, S14, S15, - S16, S17, S18, S19, S20, S21, S22, S23, - S24, S25, S26, S27, S28, S29, S30, S31, - D0, D1, D2, D3, D4, D5, D6, D7, - D8, D9, D10, D11, D12, D13, D14, D15, - D16, D17, D18, D19, D20, D21, D22, D23, - D24, D25, D26, D27, D28, D29, D30, D31, - Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, - Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, + // clang-format off + S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31, + D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, D31, + Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 + // clang-format on }; using RegList = u16; @@ -45,14 +55,14 @@ enum class ShiftType { LSL, LSR, ASR, - ROR ///< RRX falls under this too + ROR ///< RRX falls under this too }; enum class SignExtendRotation { - ROR_0, ///< ROR #0 or omitted - ROR_8, ///< ROR #8 - ROR_16, ///< ROR #16 - ROR_24 ///< ROR #24 + ROR_0, ///< ROR #0 or omitted + ROR_8, ///< ROR #8 + ROR_16, ///< ROR #16 + ROR_24 ///< ROR #24 }; const char* CondToString(Cond cond, bool explicit_al = false); @@ -109,9 +119,9 @@ inline Reg operator+(Reg reg, size_t number) { inline ExtReg operator+(ExtReg reg, size_t number) { const auto new_reg = static_cast(static_cast(reg) + number); - ASSERT((IsSingleExtReg(reg) && IsSingleExtReg(new_reg)) || - (IsDoubleExtReg(reg) && IsDoubleExtReg(new_reg)) || - (IsQuadExtReg(reg) && IsQuadExtReg(new_reg))); + ASSERT((IsSingleExtReg(reg) && IsSingleExtReg(new_reg)) + || (IsDoubleExtReg(reg) && IsDoubleExtReg(new_reg)) + || (IsQuadExtReg(reg) && IsQuadExtReg(new_reg))); return new_reg; } @@ -136,4 +146,4 @@ inline ExtReg ToVector(bool Q, size_t base, bool bit) { return Q ? ToExtRegQ(base, bit) : ToExtRegD(base, bit); } -} // namespace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/dynarmic/frontend/A64/decoder/a64.h b/src/dynarmic/frontend/A64/decoder/a64.h index a43019e7..7da60e30 100644 --- a/src/dynarmic/frontend/A64/decoder/a64.h +++ b/src/dynarmic/frontend/A64/decoder/a64.h @@ -19,19 +19,19 @@ namespace Dynarmic::A64 { -template +template using Matcher = Decoder::Matcher; -template +template using DecodeTable = std::array>, 0x1000>; namespace detail { inline size_t ToFastLookupIndex(u32 instruction) { return ((instruction >> 10) & 0x00F) | ((instruction >> 18) & 0xFF0); } -} // namespace detail +} // namespace detail -template +template DecodeTable GetDecodeTable() { std::vector> list = { #define INST(fn, name, bitstring) DYNARMIC_DECODER_GET_MATCHER(Matcher, fn, name, Decoder::detail::StringToArray<32>(bitstring)), @@ -45,7 +45,7 @@ DecodeTable GetDecodeTable() { }); // Exceptions to the above rule of thumb. - const std::set comes_first { + const std::set comes_first{ "MOVI, MVNI, ORR, BIC (vector, immediate)", "FMOV (vector, immediate)", "Unallocated SIMD modified immediate", @@ -79,4 +79,4 @@ std::optional>> Decode(u32 instruction) return iter != subtable.end() ? std::optional>>(*iter) : std::nullopt; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/ir_emitter.cpp b/src/dynarmic/frontend/A64/ir_emitter.cpp index f3aaa801..7975b2a8 100644 --- a/src/dynarmic/frontend/A64/ir_emitter.cpp +++ b/src/dynarmic/frontend/A64/ir_emitter.cpp @@ -3,8 +3,9 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/assert.h" #include "dynarmic/frontend/A64/ir_emitter.h" + +#include "dynarmic/common/assert.h" #include "dynarmic/ir/opcodes.h" namespace Dynarmic::A64 { @@ -260,4 +261,4 @@ void IREmitter::SetPC(const IR::U64& value) { Inst(Opcode::A64SetPC, value); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/ir_emitter.h b/src/dynarmic/frontend/A64/ir_emitter.h index a99a5068..deca27d5 100644 --- a/src/dynarmic/frontend/A64/ir_emitter.h +++ b/src/dynarmic/frontend/A64/ir_emitter.h @@ -23,8 +23,10 @@ namespace Dynarmic::A64 { */ class IREmitter : public IR::IREmitter { public: - explicit IREmitter(IR::Block& block) : IR::IREmitter(block) {} - explicit IREmitter(IR::Block& block, LocationDescriptor descriptor) : IR::IREmitter(block), current_location(descriptor) {} + explicit IREmitter(IR::Block& block) + : IR::IREmitter(block) {} + explicit IREmitter(IR::Block& block, LocationDescriptor descriptor) + : IR::IREmitter(block), current_location(descriptor) {} std::optional current_location; @@ -46,7 +48,7 @@ public: void DataMemoryBarrier(); void InstructionSynchronizationBarrier(); IR::U32 GetCNTFRQ(); - IR::U64 GetCNTPCT(); // TODO: Ensure sub-basic-block cycle counts are updated before this. + IR::U64 GetCNTPCT(); // TODO: Ensure sub-basic-block cycle counts are updated before this. IR::U32 GetCTR(); IR::U32 GetDCZID(); IR::U64 GetTPIDR(); @@ -94,4 +96,4 @@ public: void SetPC(const IR::U64& value); }; -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/location_descriptor.cpp b/src/dynarmic/frontend/A64/location_descriptor.cpp index e4d21294..53c8d35b 100644 --- a/src/dynarmic/frontend/A64/location_descriptor.cpp +++ b/src/dynarmic/frontend/A64/location_descriptor.cpp @@ -3,11 +3,12 @@ * SPDX-License-Identifier: 0BSD */ -#include -#include - #include "dynarmic/frontend/A64/location_descriptor.h" +#include + +#include + namespace Dynarmic::A64 { std::ostream& operator<<(std::ostream& o, const LocationDescriptor& descriptor) { @@ -15,4 +16,4 @@ std::ostream& operator<<(std::ostream& o, const LocationDescriptor& descriptor) return o; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/location_descriptor.h b/src/dynarmic/frontend/A64/location_descriptor.h index ea0fa00d..322cea3b 100644 --- a/src/dynarmic/frontend/A64/location_descriptor.h +++ b/src/dynarmic/frontend/A64/location_descriptor.h @@ -31,24 +31,22 @@ public: static_assert((pc_mask & (u64(fpcr_mask) << fpcr_shift) & (u64(1) << single_stepping_bit)) == 0); LocationDescriptor(u64 pc, FP::FPCR fpcr, bool single_stepping = false) - : pc(pc & pc_mask), fpcr(fpcr.Value() & fpcr_mask), single_stepping(single_stepping) - {} + : pc(pc & pc_mask), fpcr(fpcr.Value() & fpcr_mask), single_stepping(single_stepping) {} explicit LocationDescriptor(const IR::LocationDescriptor& o) - : pc(o.Value() & pc_mask) - , fpcr((o.Value() >> fpcr_shift) & fpcr_mask) - , single_stepping(Common::Bit(o.Value())) - {} + : pc(o.Value() & pc_mask) + , fpcr((o.Value() >> fpcr_shift) & fpcr_mask) + , single_stepping(Common::Bit(o.Value())) {} u64 PC() const { return Common::SignExtend(pc); } FP::FPCR FPCR() const { return fpcr; } bool SingleStepping() const { return single_stepping; } - bool operator == (const LocationDescriptor& o) const { + bool operator==(const LocationDescriptor& o) const { return std::tie(pc, fpcr, single_stepping) == std::tie(o.pc, o.fpcr, o.single_stepping); } - bool operator != (const LocationDescriptor& o) const { + bool operator!=(const LocationDescriptor& o) const { return !operator==(o); } @@ -77,8 +75,8 @@ public: } private: - u64 pc; ///< Current program counter value. - FP::FPCR fpcr; ///< Floating point control register. + u64 pc; ///< Current program counter value. + FP::FPCR fpcr; ///< Floating point control register. bool single_stepping; }; @@ -90,19 +88,19 @@ private: */ std::ostream& operator<<(std::ostream& o, const LocationDescriptor& descriptor); -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 namespace std { -template <> +template<> struct less { bool operator()(const Dynarmic::A64::LocationDescriptor& x, const Dynarmic::A64::LocationDescriptor& y) const noexcept { return x.UniqueHash() < y.UniqueHash(); } }; -template <> +template<> struct hash { size_t operator()(const Dynarmic::A64::LocationDescriptor& x) const noexcept { return std::hash()(x.UniqueHash()); } }; -} // namespace std +} // namespace std diff --git a/src/dynarmic/frontend/A64/translate/impl/branch.cpp b/src/dynarmic/frontend/A64/translate/impl/branch.cpp index 4c5611b4..01cc1390 100644 --- a/src/dynarmic/frontend/A64/translate/impl/branch.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/branch.cpp @@ -125,4 +125,4 @@ bool TranslatorVisitor::TBNZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) { return false; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/data_processing_addsub.cpp b/src/dynarmic/frontend/A64/translate/impl/data_processing_addsub.cpp index ad706e3a..5df4fe1c 100644 --- a/src/dynarmic/frontend/A64/translate/impl/data_processing_addsub.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/data_processing_addsub.cpp @@ -327,4 +327,4 @@ bool TranslatorVisitor::SBCS(bool sf, Reg Rm, Reg Rn, Reg Rd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/data_processing_bitfield.cpp b/src/dynarmic/frontend/A64/translate/impl/data_processing_bitfield.cpp index 8d6981ad..aec6729a 100644 --- a/src/dynarmic/frontend/A64/translate/impl/data_processing_bitfield.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/data_processing_bitfield.cpp @@ -152,4 +152,4 @@ bool TranslatorVisitor::EXTR(bool sf, bool N, Reg Rm, Imm<6> imms, Reg Rn, Reg R return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/data_processing_conditional_compare.cpp b/src/dynarmic/frontend/A64/translate/impl/data_processing_conditional_compare.cpp index f72b1fdf..03725c26 100644 --- a/src/dynarmic/frontend/A64/translate/impl/data_processing_conditional_compare.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/data_processing_conditional_compare.cpp @@ -59,4 +59,4 @@ bool TranslatorVisitor::CCMP_imm(bool sf, Imm<5> imm5, Cond cond, Reg Rn, Imm<4> return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/data_processing_conditional_select.cpp b/src/dynarmic/frontend/A64/translate/impl/data_processing_conditional_select.cpp index 88679d23..49dadaa3 100644 --- a/src/dynarmic/frontend/A64/translate/impl/data_processing_conditional_select.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/data_processing_conditional_select.cpp @@ -55,4 +55,4 @@ bool TranslatorVisitor::CSNEG(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/data_processing_crc32.cpp b/src/dynarmic/frontend/A64/translate/impl/data_processing_crc32.cpp index a690316e..a0bf932a 100644 --- a/src/dynarmic/frontend/A64/translate/impl/data_processing_crc32.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/data_processing_crc32.cpp @@ -24,15 +24,15 @@ bool TranslatorVisitor::CRC32(bool sf, Reg Rm, Imm<2> sz, Reg Rn, Reg Rd) { const IR::U32U64 data = X(datasize, Rm); switch (integral_size) { - case 0b00: - return ir.CRC32ISO8(accumulator, data); - case 0b01: - return ir.CRC32ISO16(accumulator, data); - case 0b10: - return ir.CRC32ISO32(accumulator, data); - case 0b11: - default: - return ir.CRC32ISO64(accumulator, data); + case 0b00: + return ir.CRC32ISO8(accumulator, data); + case 0b01: + return ir.CRC32ISO16(accumulator, data); + case 0b10: + return ir.CRC32ISO32(accumulator, data); + case 0b11: + default: + return ir.CRC32ISO64(accumulator, data); } }(); @@ -73,4 +73,4 @@ bool TranslatorVisitor::CRC32C(bool sf, Reg Rm, Imm<2> sz, Reg Rn, Reg Rd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/data_processing_logical.cpp b/src/dynarmic/frontend/A64/translate/impl/data_processing_logical.cpp index b9fd35c2..3f0d16bb 100644 --- a/src/dynarmic/frontend/A64/translate/impl/data_processing_logical.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/data_processing_logical.cpp @@ -233,4 +233,4 @@ bool TranslatorVisitor::BICS(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/data_processing_multiply.cpp b/src/dynarmic/frontend/A64/translate/impl/data_processing_multiply.cpp index 92791abf..60910803 100644 --- a/src/dynarmic/frontend/A64/translate/impl/data_processing_multiply.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/data_processing_multiply.cpp @@ -97,4 +97,4 @@ bool TranslatorVisitor::UMULH(Reg Rm, Reg Rn, Reg Rd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/data_processing_pcrel.cpp b/src/dynarmic/frontend/A64/translate/impl/data_processing_pcrel.cpp index 05a829e9..48b860a0 100644 --- a/src/dynarmic/frontend/A64/translate/impl/data_processing_pcrel.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/data_processing_pcrel.cpp @@ -21,4 +21,4 @@ bool TranslatorVisitor::ADRP(Imm<2> immlo, Imm<19> immhi, Reg Rd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/data_processing_register.cpp b/src/dynarmic/frontend/A64/translate/impl/data_processing_register.cpp index 7b95036a..3484a1e3 100644 --- a/src/dynarmic/frontend/A64/translate/impl/data_processing_register.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/data_processing_register.cpp @@ -71,7 +71,8 @@ bool TranslatorVisitor::RBIT_int(bool sf, Reg Rn, Reg Rd) { bool TranslatorVisitor::REV(bool sf, bool opc_0, Reg Rn, Reg Rd) { const size_t datasize = sf ? 64 : 32; - if (!sf && opc_0) return UnallocatedEncoding(); + if (!sf && opc_0) + return UnallocatedEncoding(); const IR::U32U64 operand = X(datasize, Rn); @@ -117,7 +118,7 @@ bool TranslatorVisitor::UDIV(bool sf, Reg Rm, Reg Rn, Reg Rd) { const IR::U32U64 m = X(datasize, Rm); const IR::U32U64 n = X(datasize, Rn); - const IR::U32U64 result = ir.UnsignedDiv(n,m); + const IR::U32U64 result = ir.UnsignedDiv(n, m); X(datasize, Rd, result); return true; @@ -129,10 +130,10 @@ bool TranslatorVisitor::SDIV(bool sf, Reg Rm, Reg Rn, Reg Rd) { const IR::U32U64 m = X(datasize, Rm); const IR::U32U64 n = X(datasize, Rn); - const IR::U32U64 result = ir.SignedDiv(n,m); + const IR::U32U64 result = ir.SignedDiv(n, m); X(datasize, Rd, result); return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/data_processing_shift.cpp b/src/dynarmic/frontend/A64/translate/impl/data_processing_shift.cpp index 19ef8fa9..1b48abd7 100644 --- a/src/dynarmic/frontend/A64/translate/impl/data_processing_shift.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/data_processing_shift.cpp @@ -55,4 +55,4 @@ bool TranslatorVisitor::RORV(bool sf, Reg Rm, Reg Rn, Reg Rd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/exception_generating.cpp b/src/dynarmic/frontend/A64/translate/impl/exception_generating.cpp index 7e106bc8..460ebfa6 100644 --- a/src/dynarmic/frontend/A64/translate/impl/exception_generating.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/exception_generating.cpp @@ -19,4 +19,4 @@ bool TranslatorVisitor::SVC(Imm<16> imm16) { return false; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/floating_point_compare.cpp b/src/dynarmic/frontend/A64/translate/impl/floating_point_compare.cpp index 63f18a81..c1835b81 100644 --- a/src/dynarmic/frontend/A64/translate/impl/floating_point_compare.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/floating_point_compare.cpp @@ -25,7 +25,7 @@ bool FPCompare(TranslatorVisitor& v, Imm<2> type, Vec Vm, Vec Vn, bool exc_on_qn v.ir.SetNZCV(nzcv); return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::FCMP_float(Imm<2> type, Vec Vm, Vec Vn, bool cmp_with_zero) { return FPCompare(*this, type, Vm, Vn, false, cmp_with_zero); @@ -35,4 +35,4 @@ bool TranslatorVisitor::FCMPE_float(Imm<2> type, Vec Vm, Vec Vn, bool cmp_with_z return FPCompare(*this, type, Vm, Vn, true, cmp_with_zero); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/floating_point_conditional_compare.cpp b/src/dynarmic/frontend/A64/translate/impl/floating_point_conditional_compare.cpp index e09cca13..a0b10224 100644 --- a/src/dynarmic/frontend/A64/translate/impl/floating_point_conditional_compare.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/floating_point_conditional_compare.cpp @@ -22,7 +22,7 @@ bool FPCompare(TranslatorVisitor& v, Imm<2> type, Vec Vm, Cond cond, Vec Vn, Imm v.ir.SetNZCV(v.ir.ConditionalSelect(cond, then_flags, else_flags)); return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::FCCMP_float(Imm<2> type, Vec Vm, Cond cond, Vec Vn, Imm<4> nzcv) { return FPCompare(*this, type, Vm, cond, Vn, nzcv, false); @@ -32,4 +32,4 @@ bool TranslatorVisitor::FCCMPE_float(Imm<2> type, Vec Vm, Cond cond, Vec Vn, Imm return FPCompare(*this, type, Vm, cond, Vn, nzcv, true); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/floating_point_conditional_select.cpp b/src/dynarmic/frontend/A64/translate/impl/floating_point_conditional_select.cpp index 4d0a6503..11ce6f62 100644 --- a/src/dynarmic/frontend/A64/translate/impl/floating_point_conditional_select.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/floating_point_conditional_select.cpp @@ -21,4 +21,4 @@ bool TranslatorVisitor::FCSEL_float(Imm<2> type, Vec Vm, Cond cond, Vec Vn, Vec return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp b/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp index e7b6b258..5fa7ac1f 100644 --- a/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp @@ -111,4 +111,4 @@ bool TranslatorVisitor::FCVTZU_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_integer.cpp b/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_integer.cpp index 0c134cb8..2f98ebfb 100644 --- a/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_integer.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/floating_point_conversion_integer.cpp @@ -196,4 +196,4 @@ bool TranslatorVisitor::FCVTMU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) { return FloaingPointConvertUnsignedInteger(*this, sf, type, Vn, Rd, FP::RoundingMode::TowardsMinusInfinity); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp b/src/dynarmic/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp index cd611e4c..187f0a89 100644 --- a/src/dynarmic/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp @@ -127,7 +127,7 @@ bool TranslatorVisitor::FCVT_float(Imm<2> type, Imm<2> opc, Vec Vn, Vec Vd) { } break; case 64: - switch (*dstsize) { + switch (*dstsize) { case 16: result = ir.FPDoubleToHalf(operand, rounding_mode); break; @@ -143,8 +143,7 @@ bool TranslatorVisitor::FCVT_float(Imm<2> type, Imm<2> opc, Vec Vn, Vec Vd) { return true; } -static bool FloatingPointRoundToIntegral(TranslatorVisitor& v, Imm<2> type, Vec Vn, Vec Vd, - FP::RoundingMode rounding_mode, bool exact) { +static bool FloatingPointRoundToIntegral(TranslatorVisitor& v, Imm<2> type, Vec Vn, Vec Vd, FP::RoundingMode rounding_mode, bool exact) { const auto datasize = FPGetDataSize(type); if (!datasize) { return v.UnallocatedEncoding(); @@ -184,4 +183,4 @@ bool TranslatorVisitor::FRINTI_float(Imm<2> type, Vec Vn, Vec Vd) { return FloatingPointRoundToIntegral(*this, type, Vn, Vd, ir.current_location->FPCR().RMode(), false); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/floating_point_data_processing_three_register.cpp b/src/dynarmic/frontend/A64/translate/impl/floating_point_data_processing_three_register.cpp index 0c8ebcf4..eaad58c8 100644 --- a/src/dynarmic/frontend/A64/translate/impl/floating_point_data_processing_three_register.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/floating_point_data_processing_three_register.cpp @@ -63,4 +63,4 @@ bool TranslatorVisitor::FNMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/floating_point_data_processing_two_register.cpp b/src/dynarmic/frontend/A64/translate/impl/floating_point_data_processing_two_register.cpp index 1d47df21..a4dbda9c 100644 --- a/src/dynarmic/frontend/A64/translate/impl/floating_point_data_processing_two_register.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/floating_point_data_processing_two_register.cpp @@ -142,4 +142,4 @@ bool TranslatorVisitor::FNMUL_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/impl.cpp b/src/dynarmic/frontend/A64/translate/impl/impl.cpp index 9148e159..23773727 100644 --- a/src/dynarmic/frontend/A64/translate/impl/impl.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/impl.cpp @@ -3,8 +3,9 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/bit_util.h" #include "dynarmic/frontend/A64/translate/impl/impl.h" + +#include "dynarmic/common/bit_util.h" #include "dynarmic/ir/terminal.h" namespace Dynarmic::A64 { @@ -335,19 +336,19 @@ IR::U32U64 TranslatorVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option, bool signed_extend; switch (option.ZeroExtend()) { - case 0b000: { // UXTB + case 0b000: { // UXTB val = ir.LeastSignificantByte(val); len = 8; signed_extend = false; break; } - case 0b001: { // UXTH + case 0b001: { // UXTH val = ir.LeastSignificantHalf(val); len = 16; signed_extend = false; break; } - case 0b010: { // UXTW + case 0b010: { // UXTW if (bitsize != 32) { val = ir.LeastSignificantWord(val); } @@ -355,24 +356,24 @@ IR::U32U64 TranslatorVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option, signed_extend = false; break; } - case 0b011: { // UXTX + case 0b011: { // UXTX len = 64; signed_extend = false; break; } - case 0b100: { // SXTB + case 0b100: { // SXTB val = ir.LeastSignificantByte(val); len = 8; signed_extend = true; break; } - case 0b101: { // SXTH + case 0b101: { // SXTH val = ir.LeastSignificantHalf(val); len = 16; signed_extend = true; break; } - case 0b110: { // SXTW + case 0b110: { // SXTW if (bitsize != 32) { val = ir.LeastSignificantWord(val); } @@ -380,7 +381,7 @@ IR::U32U64 TranslatorVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option, signed_extend = true; break; } - case 0b111: { // SXTX + case 0b111: { // SXTX len = 64; signed_extend = true; break; @@ -402,4 +403,4 @@ IR::U32U64 TranslatorVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option, return ir.LogicalShiftLeft(extended, ir.Imm8(shift)); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/impl.h b/src/dynarmic/frontend/A64/translate/impl/impl.h index 52749d31..e51f811e 100644 --- a/src/dynarmic/frontend/A64/translate/impl/impl.h +++ b/src/dynarmic/frontend/A64/translate/impl/impl.h @@ -7,18 +7,19 @@ #include -#include "dynarmic/frontend/imm.h" #include "dynarmic/frontend/A64/ir_emitter.h" #include "dynarmic/frontend/A64/location_descriptor.h" #include "dynarmic/frontend/A64/translate/translate.h" #include "dynarmic/frontend/A64/types.h" +#include "dynarmic/frontend/imm.h" namespace Dynarmic::A64 { struct TranslatorVisitor final { using instruction_return_type = bool; - explicit TranslatorVisitor(IR::Block& block, LocationDescriptor descriptor, TranslationOptions options) : ir(block, descriptor), options(std::move(options)) {} + explicit TranslatorVisitor(IR::Block& block, LocationDescriptor descriptor, TranslationOptions options) + : ir(block, descriptor), options(std::move(options)) {} A64::IREmitter ir; TranslationOptions options; @@ -1080,4 +1081,4 @@ inline std::optional FPGetDataSize(Imm<2> type) { return std::nullopt; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/load_store_exclusive.cpp b/src/dynarmic/frontend/A64/translate/impl/load_store_exclusive.cpp index 5fe2fb90..0e67e11b 100644 --- a/src/dynarmic/frontend/A64/translate/impl/load_store_exclusive.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/load_store_exclusive.cpp @@ -206,4 +206,4 @@ bool TranslatorVisitor::LDAR(Imm<2> sz, Reg Rn, Reg Rt) { return OrderedSharedDecodeAndOperation(*this, size, L, o0, Rn, Rt); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/load_store_load_literal.cpp b/src/dynarmic/frontend/A64/translate/impl/load_store_load_literal.cpp index a2226494..995aba42 100644 --- a/src/dynarmic/frontend/A64/translate/impl/load_store_load_literal.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/load_store_load_literal.cpp @@ -52,4 +52,4 @@ bool TranslatorVisitor::PRFM_lit(Imm<19> /*imm19*/, Imm<5> /*prfop*/) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/load_store_multiple_structures.cpp b/src/dynarmic/frontend/A64/translate/impl/load_store_multiple_structures.cpp index 6846c33b..77c57a96 100644 --- a/src/dynarmic/frontend/A64/translate/impl/load_store_multiple_structures.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/load_store_multiple_structures.cpp @@ -131,4 +131,4 @@ bool TranslatorVisitor::LDx_mult_2(bool Q, Reg Rm, Imm<4> opcode, Imm<2> size, R return SharedDecodeAndOperation(*this, wback, memop, Q, Rm, opcode, size, Rn, Vt); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/load_store_no_allocate_pair.cpp b/src/dynarmic/frontend/A64/translate/impl/load_store_no_allocate_pair.cpp index 22fa35c9..c85cc552 100644 --- a/src/dynarmic/frontend/A64/translate/impl/load_store_no_allocate_pair.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/load_store_no_allocate_pair.cpp @@ -19,4 +19,4 @@ bool TranslatorVisitor::STNP_LDNP_fpsimd(Imm<2> opc, Imm<1> L, Imm<7> imm7, Vec return STP_LDP_fpsimd(opc, true, false, L, imm7, Vt2, Rn, Vt); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp b/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp index 5f10946d..d939c45f 100644 --- a/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/load_store_register_immediate.cpp @@ -246,4 +246,4 @@ bool TranslatorVisitor::LDUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg return LoadStoreSIMD(*this, wback, postindex, scale, offset, IR::MemOp::LOAD, Rn, Vt); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/load_store_register_pair.cpp b/src/dynarmic/frontend/A64/translate/impl/load_store_register_pair.cpp index 62520a78..4c81564f 100644 --- a/src/dynarmic/frontend/A64/translate/impl/load_store_register_pair.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/load_store_register_pair.cpp @@ -151,4 +151,4 @@ bool TranslatorVisitor::STP_LDP_fpsimd(Imm<2> opc, bool not_postindex, bool wbac return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/load_store_register_register_offset.cpp b/src/dynarmic/frontend/A64/translate/impl/load_store_register_register_offset.cpp index 9e546c95..97910958 100644 --- a/src/dynarmic/frontend/A64/translate/impl/load_store_register_register_offset.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/load_store_register_register_offset.cpp @@ -157,4 +157,4 @@ bool TranslatorVisitor::LDR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> return VecSharedDecodeAndOperation(*this, scale, shift, opc_0, Rm, option, Rn, Vt); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/load_store_register_unprivileged.cpp b/src/dynarmic/frontend/A64/translate/impl/load_store_register_unprivileged.cpp index e11bf995..d3f4194f 100644 --- a/src/dynarmic/frontend/A64/translate/impl/load_store_register_unprivileged.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/load_store_register_unprivileged.cpp @@ -7,8 +7,7 @@ namespace Dynarmic::A64 { -static bool StoreRegister(TranslatorVisitor& v, const size_t datasize, - const Imm<9> imm9, const Reg Rn, const Reg Rt) { +static bool StoreRegister(TranslatorVisitor& v, const size_t datasize, const Imm<9> imm9, const Reg Rn, const Reg Rt) { const u64 offset = imm9.SignExtend(); const auto acctype = IR::AccType::UNPRIV; @@ -26,8 +25,7 @@ static bool StoreRegister(TranslatorVisitor& v, const size_t datasize, return true; } -static bool LoadRegister(TranslatorVisitor& v, const size_t datasize, - const Imm<9> imm9, const Reg Rn, const Reg Rt) { +static bool LoadRegister(TranslatorVisitor& v, const size_t datasize, const Imm<9> imm9, const Reg Rn, const Reg Rt) { const u64 offset = imm9.SignExtend(); const auto acctype = IR::AccType::UNPRIV; @@ -47,8 +45,7 @@ static bool LoadRegister(TranslatorVisitor& v, const size_t datasize, return true; } -static bool LoadRegisterSigned(TranslatorVisitor& v, const size_t datasize, - const Imm<2> opc, const Imm<9> imm9, const Reg Rn, const Reg Rt) { +static bool LoadRegisterSigned(TranslatorVisitor& v, const size_t datasize, const Imm<2> opc, const Imm<9> imm9, const Reg Rn, const Reg Rt) { const u64 offset = imm9.SignExtend(); const auto acctype = IR::AccType::UNPRIV; @@ -149,4 +146,4 @@ bool TranslatorVisitor::LDTRSW(Imm<9> imm9, Reg Rn, Reg Rt) { X(64, Rt, SignExtend(data, 64)); return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/load_store_single_structure.cpp b/src/dynarmic/frontend/A64/translate/impl/load_store_single_structure.cpp index 6bea7b8b..b4bc8429 100644 --- a/src/dynarmic/frontend/A64/translate/impl/load_store_single_structure.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/load_store_single_structure.cpp @@ -9,9 +9,7 @@ namespace Dynarmic::A64 { -static bool SharedDecodeAndOperation(TranslatorVisitor& v, bool wback, IR::MemOp memop, - bool Q, bool S, bool R, bool replicate, std::optional Rm, - Imm<3> opcode, Imm<2> size, Reg Rn, Vec Vt) { +static bool SharedDecodeAndOperation(TranslatorVisitor& v, bool wback, IR::MemOp memop, bool Q, bool S, bool R, bool replicate, std::optional Rm, Imm<3> opcode, Imm<2> size, Reg Rn, Vec Vt) { const size_t selem = (opcode.Bit<0>() << 1 | u32{R}) + 1; size_t scale = opcode.Bits<1, 2>(); size_t index = 0; @@ -24,7 +22,7 @@ static bool SharedDecodeAndOperation(TranslatorVisitor& v, bool wback, IR::MemOp if (size.Bit<0>()) { return v.UnallocatedEncoding(); } - index = Q << 2 | S << 1 | u32{size.Bit<1>()}; + index = Q << 2 | S << 1 | u32{size.Bit<1>()}; break; case 2: if (size.Bit<1>()) { @@ -223,4 +221,4 @@ bool TranslatorVisitor::ST4_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<3>{(upper_opcode.ZeroExtend() << 1) | 1}, size, Rn, Vt); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/move_wide.cpp b/src/dynarmic/frontend/A64/translate/impl/move_wide.cpp index cc953c44..7bd2e6e3 100644 --- a/src/dynarmic/frontend/A64/translate/impl/move_wide.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/move_wide.cpp @@ -56,5 +56,4 @@ bool TranslatorVisitor::MOVK(bool sf, Imm<2> hw, Imm<16> imm16, Reg Rd) { return true; } - -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_across_lanes.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_across_lanes.cpp index 1946404c..47aa5871 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_across_lanes.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_across_lanes.cpp @@ -107,8 +107,7 @@ enum class ScalarMinMaxOperation { Min, }; -bool ScalarMinMax(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, - ScalarMinMaxOperation operation, Signedness sign) { +bool ScalarMinMax(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, ScalarMinMaxOperation operation, Signedness sign) { if ((size == 0b10 && !Q) || size == 0b11) { return v.ReservedValue(); } @@ -163,7 +162,7 @@ bool ScalarMinMax(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::ADDV(bool Q, Imm<2> size, Vec Vn, Vec Vd) { if ((size == 0b10 && !Q) || size == 0b11) { @@ -235,4 +234,4 @@ bool TranslatorVisitor::UMAXV(bool Q, Imm<2> size, Vec Vn, Vec Vd) { bool TranslatorVisitor::UMINV(bool Q, Imm<2> size, Vec Vn, Vec Vd) { return ScalarMinMax(*this, Q, size, Vn, Vd, ScalarMinMaxOperation::Min, Signedness::Unsigned); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_aes.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_aes.cpp index d39af948..d604703e 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_aes.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_aes.cpp @@ -43,4 +43,4 @@ bool TranslatorVisitor::AESMC(Vec Vn, Vec Vd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_copy.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_copy.cpp index b8033091..e5a47ce2 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_copy.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_copy.cpp @@ -155,4 +155,4 @@ bool TranslatorVisitor::INS_elt(Imm<5> imm5, Imm<4> imm4, Vec Vn, Vec Vd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_crypto_four_register.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_crypto_four_register.cpp index c88c84a9..0e1bae79 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_crypto_four_register.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_crypto_four_register.cpp @@ -49,4 +49,4 @@ bool TranslatorVisitor::SM3SS1(Vec Vm, Vec Va, Vec Vn, Vec Vd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_crypto_three_register.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_crypto_three_register.cpp index fd0d918c..f4810f2d 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_crypto_three_register.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_crypto_three_register.cpp @@ -81,7 +81,7 @@ bool SM3TT2(TranslatorVisitor& v, Vec Vm, Imm<2> imm2, Vec Vn, Vec Vd, SM3TTVari v.ir.SetQ(Vd, result); return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::SM3TT1A(Vec Vm, Imm<2> imm2, Vec Vn, Vec Vd) { return SM3TT1(*this, Vm, imm2, Vn, Vd, SM3TTVariant::A); @@ -99,4 +99,4 @@ bool TranslatorVisitor::SM3TT2B(Vec Vm, Imm<2> imm2, Vec Vn, Vec Vd) { return SM3TT2(*this, Vm, imm2, Vn, Vd, SM3TTVariant::B); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_extract.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_extract.cpp index ea02bad6..bb5dcbe9 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_extract.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_extract.cpp @@ -24,4 +24,4 @@ bool TranslatorVisitor::EXT(bool Q, Vec Vm, Imm<4> imm4, Vec Vn, Vec Vd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp index ef801f2b..ed45bf59 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp @@ -13,7 +13,7 @@ bool TranslatorVisitor::MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm< // MOVI // also FMOV (vector, immediate) when cmode == 0b1111 - const auto movi = [&]{ + const auto movi = [&] { const u64 imm64 = AdvSIMDExpandImm(op, cmode, concatenate(a, b, c, d, e, f, g, h)); const IR::U128 imm = datasize == 64 ? ir.ZeroExtendToQuad(ir.Imm64(imm64)) : ir.VectorBroadcast(64, ir.Imm64(imm64)); V(128, Vd, imm); @@ -21,7 +21,7 @@ bool TranslatorVisitor::MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm< }; // MVNI - const auto mvni = [&]{ + const auto mvni = [&] { const u64 imm64 = ~AdvSIMDExpandImm(op, cmode, concatenate(a, b, c, d, e, f, g, h)); const IR::U128 imm = datasize == 64 ? ir.ZeroExtendToQuad(ir.Imm64(imm64)) : ir.VectorBroadcast(64, ir.Imm64(imm64)); V(128, Vd, imm); @@ -29,7 +29,7 @@ bool TranslatorVisitor::MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm< }; // ORR (vector, immediate) - const auto orr = [&]{ + const auto orr = [&] { const u64 imm64 = AdvSIMDExpandImm(op, cmode, concatenate(a, b, c, d, e, f, g, h)); const IR::U128 imm = datasize == 64 ? ir.ZeroExtendToQuad(ir.Imm64(imm64)) : ir.VectorBroadcast(64, ir.Imm64(imm64)); const IR::U128 operand = V(datasize, Vd); @@ -39,7 +39,7 @@ bool TranslatorVisitor::MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm< }; // BIC (vector, immediate) - const auto bic = [&]{ + const auto bic = [&] { const u64 imm64 = ~AdvSIMDExpandImm(op, cmode, concatenate(a, b, c, d, e, f, g, h)); const IR::U128 imm = datasize == 64 ? ir.ZeroExtendToQuad(ir.Imm64(imm64)) : ir.VectorBroadcast(64, ir.Imm64(imm64)); const IR::U128 operand = V(datasize, Vd); @@ -49,25 +49,45 @@ bool TranslatorVisitor::MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm< }; switch (concatenate(cmode, Imm<1>{op}).ZeroExtend()) { - case 0b00000: case 0b00100: case 0b01000: case 0b01100: - case 0b10000: case 0b10100: - case 0b11000: case 0b11010: - case 0b11100: case 0b11101: case 0b11110: + case 0b00000: + case 0b00100: + case 0b01000: + case 0b01100: + case 0b10000: + case 0b10100: + case 0b11000: + case 0b11010: + case 0b11100: + case 0b11101: + case 0b11110: return movi(); case 0b11111: if (!Q) { return UnallocatedEncoding(); } return movi(); - case 0b00001: case 0b00101: case 0b01001: case 0b01101: - case 0b10001: case 0b10101: - case 0b11001: case 0b11011: + case 0b00001: + case 0b00101: + case 0b01001: + case 0b01101: + case 0b10001: + case 0b10101: + case 0b11001: + case 0b11011: return mvni(); - case 0b00010: case 0b00110: case 0b01010: case 0b01110: - case 0b10010: case 0b10110: + case 0b00010: + case 0b00110: + case 0b01010: + case 0b01110: + case 0b10010: + case 0b10110: return orr(); - case 0b00011: case 0b00111: case 0b01011: case 0b01111: - case 0b10011: case 0b10111: + case 0b00011: + case 0b00111: + case 0b01011: + case 0b01111: + case 0b10011: + case 0b10111: return bic(); } @@ -92,7 +112,7 @@ bool TranslatorVisitor::FMOV_3(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, I const size_t datasize = Q ? 128 : 64; const Imm<8> imm8 = concatenate(a, b, c, d, e, f, g, h); - const u16 imm16 = [&imm8]{ + const u16 imm16 = [&imm8] { u16 imm16 = 0; imm16 |= imm8.Bit<7>() ? 0x8000 : 0; imm16 |= imm8.Bit<6>() ? 0x3000 : 0x4000; @@ -106,4 +126,4 @@ bool TranslatorVisitor::FMOV_3(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, I return true; } -} // namespace Dynarmic::A6 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_permute.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_permute.cpp index 6bd1a43d..95f3a37e 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_permute.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_permute.cpp @@ -4,6 +4,7 @@ */ #include + #include "dynarmic/frontend/A64/translate/impl/impl.h" namespace Dynarmic::A64 { @@ -45,13 +46,13 @@ bool VectorUnzip(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec const IR::U128 n = v.V(datasize, Vn); const IR::U128 m = v.V(datasize, Vm); const IR::U128 result = type == UnzipType::Even - ? (Q ? v.ir.VectorDeinterleaveEven(esize, n, m) : v.ir.VectorDeinterleaveEvenLower(esize, n, m)) - : (Q ? v.ir.VectorDeinterleaveOdd(esize, n, m) : v.ir.VectorDeinterleaveOddLower(esize, n, m)); + ? (Q ? v.ir.VectorDeinterleaveEven(esize, n, m) : v.ir.VectorDeinterleaveEvenLower(esize, n, m)) + : (Q ? v.ir.VectorDeinterleaveOdd(esize, n, m) : v.ir.VectorDeinterleaveOddLower(esize, n, m)); v.V(datasize, Vd, result); return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::TRN1(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { return VectorTranspose(*this, Q, size, Vm, Vn, Vd, Transposition::TRN1); @@ -95,7 +96,7 @@ bool TranslatorVisitor::ZIP2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { const IR::U128 operand1 = V(datasize, Vn); const IR::U128 operand2 = V(datasize, Vm); - const IR::U128 result = [&]{ + const IR::U128 result = [&] { if (Q) { return ir.VectorInterleaveUpper(esize, operand1, operand2); } @@ -109,4 +110,4 @@ bool TranslatorVisitor::ZIP2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp index 41bf991f..63615b0f 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_scalar_pairwise.cpp @@ -38,7 +38,7 @@ bool FPPairwiseMinMax(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, MinMaxOpera v.V(128, Vd, v.ir.ZeroExtendToQuad(result)); return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::ADDP_pair(Imm<2> size, Vec Vn, Vec Vd) { if (size != 0b11) { @@ -77,4 +77,4 @@ bool TranslatorVisitor::FMINNMP_pair_2(bool sz, Vec Vn, Vec Vd) { bool TranslatorVisitor::FMINP_pair_2(bool sz, Vec Vn, Vec Vd) { return FPPairwiseMinMax(*this, sz, Vn, Vd, MinMaxOperation::Min); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp index 8c809e04..df58c669 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp @@ -61,8 +61,7 @@ bool SaturatingShiftLeft(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, return true; } -bool ShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, - ShiftExtraBehavior behavior, Signedness signedness) { +bool ShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, ShiftExtraBehavior behavior, Signedness signedness) { if (!immh.Bit<3>()) { return v.ReservedValue(); } @@ -87,8 +86,7 @@ bool ShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, return true; } -bool RoundingShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, - ShiftExtraBehavior behavior, Signedness signedness) { +bool RoundingShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, ShiftExtraBehavior behavior, Signedness signedness) { if (!immh.Bit<3>()) { return v.ReservedValue(); } @@ -124,8 +122,7 @@ enum class ShiftDirection { Right, }; -bool ShiftAndInsert(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, - ShiftDirection direction) { +bool ShiftAndInsert(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, ShiftDirection direction) { if (!immh.Bit<3>()) { return v.ReservedValue(); } @@ -142,7 +139,7 @@ bool ShiftAndInsert(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec const u64 mask = [&] { if (direction == ShiftDirection::Right) { - return shift_amount == esize ? 0 : Common::Ones(esize) >> shift_amount; + return shift_amount == esize ? 0 : Common::Ones(esize) >> shift_amount; } return Common::Ones(esize) << shift_amount; @@ -164,8 +161,7 @@ bool ShiftAndInsert(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec return true; } -bool ShiftRightNarrowing(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, - Narrowing narrowing, Signedness signedness) { +bool ShiftRightNarrowing(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, Narrowing narrowing, Signedness signedness) { if (immh == 0b0000) { return v.ReservedValue(); } @@ -230,24 +226,24 @@ bool ScalarFPConvertWithRound(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Ve case FloatConversionDirection::FloatToFixed: if (esize == 64) { return sign == Signedness::Signed - ? v.ir.FPToFixedS64(operand, fbits, rounding_mode) - : v.ir.FPToFixedU64(operand, fbits, rounding_mode); + ? v.ir.FPToFixedS64(operand, fbits, rounding_mode) + : v.ir.FPToFixedU64(operand, fbits, rounding_mode); } return sign == Signedness::Signed - ? v.ir.FPToFixedS32(operand, fbits, rounding_mode) - : v.ir.FPToFixedU32(operand, fbits, rounding_mode); + ? v.ir.FPToFixedS32(operand, fbits, rounding_mode) + : v.ir.FPToFixedU32(operand, fbits, rounding_mode); case FloatConversionDirection::FixedToFloat: if (esize == 64) { return sign == Signedness::Signed - ? v.ir.FPSignedFixedToDouble(operand, fbits, rounding_mode) - : v.ir.FPUnsignedFixedToDouble(operand, fbits, rounding_mode); + ? v.ir.FPSignedFixedToDouble(operand, fbits, rounding_mode) + : v.ir.FPUnsignedFixedToDouble(operand, fbits, rounding_mode); } return sign == Signedness::Signed - ? v.ir.FPSignedFixedToSingle(operand, fbits, rounding_mode) - : v.ir.FPUnsignedFixedToSingle(operand, fbits, rounding_mode); + ? v.ir.FPSignedFixedToSingle(operand, fbits, rounding_mode) + : v.ir.FPUnsignedFixedToSingle(operand, fbits, rounding_mode); } UNREACHABLE(); @@ -256,7 +252,7 @@ bool ScalarFPConvertWithRound(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Ve v.V_scalar(esize, Vd, result); return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::FCVTZS_fix_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { return ScalarFPConvertWithRound(*this, immh, immb, Vn, Vd, Signedness::Signed, FloatConversionDirection::FloatToFixed, FP::RoundingMode::TowardsZero); @@ -353,4 +349,4 @@ bool TranslatorVisitor::USRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { return ShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate, Signedness::Unsigned); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp index 53af09cc..76ef26ad 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp @@ -49,8 +49,7 @@ bool RoundingShiftLeft(TranslatorVisitor& v, Imm<2> size, Vec Vm, Vec Vn, Vec Vd return true; } -bool ScalarCompare(TranslatorVisitor& v, Imm<2> size, std::optional Vm, Vec Vn, Vec Vd, - ComparisonType type, ComparisonVariant variant) { +bool ScalarCompare(TranslatorVisitor& v, Imm<2> size, std::optional Vm, Vec Vn, Vec Vd, ComparisonType type, ComparisonVariant variant) { if (size != 0b11) { return v.ReservedValue(); } @@ -123,7 +122,7 @@ bool ScalarFPCompareRegister(TranslatorVisitor& v, bool sz, Vec Vm, Vec Vn, Vec v.V_scalar(datasize, Vd, v.ir.VectorGetElement(esize, result, 0)); return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::SQADD_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { const size_t esize = 8 << size.ZeroExtend(); @@ -435,4 +434,4 @@ bool TranslatorVisitor::USHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp index 01021c85..2289f5cb 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp @@ -47,21 +47,20 @@ bool ScalarFPCompareAgainstZero(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, C return true; } -bool ScalarFPConvertWithRound(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, - FP::RoundingMode rmode, Signedness sign) { +bool ScalarFPConvertWithRound(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, FP::RoundingMode rmode, Signedness sign) { const size_t esize = sz ? 64 : 32; const IR::U32U64 operand = v.V_scalar(esize, Vn); const IR::U32U64 result = [&]() -> IR::U32U64 { if (sz) { return sign == Signedness::Signed - ? v.ir.FPToFixedS64(operand, 0, rmode) - : v.ir.FPToFixedU64(operand, 0, rmode); + ? v.ir.FPToFixedS64(operand, 0, rmode) + : v.ir.FPToFixedU64(operand, 0, rmode); } return sign == Signedness::Signed - ? v.ir.FPToFixedS32(operand, 0, rmode) - : v.ir.FPToFixedU32(operand, 0, rmode); + ? v.ir.FPToFixedS32(operand, 0, rmode) + : v.ir.FPToFixedU32(operand, 0, rmode); }(); v.V_scalar(esize, Vd, result); @@ -83,7 +82,7 @@ bool SaturatedNarrow(TranslatorVisitor& v, Imm<2> size, Vec Vn, Vec Vd, Narrowin v.V_scalar(64, Vd, v.ir.VectorGetElement(64, result, 0)); return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::ABS_1(Imm<2> size, Vec Vn, Vec Vd) { if (size != 0b11) { @@ -254,8 +253,8 @@ bool TranslatorVisitor::SCVTF_int_2(bool sz, Vec Vn, Vec Vd) { const IR::U32U64 element = V_scalar(esize, Vn); const IR::U32U64 result = esize == 32 - ? IR::U32U64(ir.FPSignedFixedToSingle(element, 0, ir.current_location->FPCR().RMode())) - : IR::U32U64(ir.FPSignedFixedToDouble(element, 0, ir.current_location->FPCR().RMode())); + ? IR::U32U64(ir.FPSignedFixedToSingle(element, 0, ir.current_location->FPCR().RMode())) + : IR::U32U64(ir.FPSignedFixedToDouble(element, 0, ir.current_location->FPCR().RMode())); V_scalar(esize, Vd, result); return true; @@ -306,8 +305,8 @@ bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) { const IR::U32U64 element = V_scalar(esize, Vn); const IR::U32U64 result = esize == 32 - ? IR::U32U64(ir.FPUnsignedFixedToSingle(element, 0, ir.current_location->FPCR().RMode())) - : IR::U32U64(ir.FPUnsignedFixedToDouble(element, 0, ir.current_location->FPCR().RMode())); + ? IR::U32U64(ir.FPUnsignedFixedToSingle(element, 0, ir.current_location->FPCR().RMode())) + : IR::U32U64(ir.FPUnsignedFixedToDouble(element, 0, ir.current_location->FPCR().RMode())); V_scalar(esize, Vd, result); return true; @@ -329,4 +328,4 @@ bool TranslatorVisitor::USQADD_1(Imm<2> size, Vec Vn, Vec Vd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp index 84b95adb..aca34057 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp @@ -4,6 +4,7 @@ */ #include + #include "dynarmic/frontend/A64/translate/impl/impl.h" namespace Dynarmic::A64 { @@ -23,8 +24,7 @@ enum class ExtraBehavior { MultiplyExtended, }; -bool MultiplyByElement(TranslatorVisitor& v, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, - Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { +bool MultiplyByElement(TranslatorVisitor& v, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { if (sz && L == 1) { return v.ReservedValue(); } @@ -58,8 +58,7 @@ bool MultiplyByElement(TranslatorVisitor& v, bool sz, Imm<1> L, Imm<1> M, Imm<4> return true; } -bool MultiplyByElementHalfPrecision(TranslatorVisitor& v, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, - Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { +bool MultiplyByElementHalfPrecision(TranslatorVisitor& v, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { const size_t esize = 16; const size_t idxsize = H == 1 ? 128 : 64; const size_t index = concatenate(H, L, M).ZeroExtend(); @@ -91,7 +90,7 @@ bool MultiplyByElementHalfPrecision(TranslatorVisitor& v, Imm<1> L, Imm<1> M, Im v.V_scalar(esize, Vd, result); return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::FMLA_elt_1(Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { return MultiplyByElementHalfPrecision(*this, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::Accumulate); @@ -170,4 +169,4 @@ bool TranslatorVisitor::SQDMULL_elt_1(Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vm return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_sha.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_sha.cpp index 61af2f85..8f0b68cf 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_sha.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_sha.cpp @@ -12,7 +12,7 @@ IR::U32 SHAchoose(IREmitter& ir, IR::U32 x, IR::U32 y, IR::U32 z) { } IR::U32 SHAmajority(IREmitter& ir, IR::U32 x, IR::U32 y, IR::U32 z) { - return ir.Or(ir.And(x, y), ir.And(ir.Or(x, y), z)) ; + return ir.Or(ir.And(x, y), ir.And(ir.Or(x, y), z)); } IR::U32 SHAparity(IREmitter& ir, IR::U32 x, IR::U32 y, IR::U32 z) { @@ -107,7 +107,7 @@ IR::U128 SHA256hash(IREmitter& ir, IR::U128 x, IR::U128 y, IR::U128 w, SHA256Has return y; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::SHA1C(Vec Vm, Vec Vn, Vec Vd) { const IR::U128 result = SHA1HashUpdate(ir, Vm, Vn, Vd, SHAchoose); @@ -258,4 +258,4 @@ bool TranslatorVisitor::SHA256H2(Vec Vm, Vec Vn, Vec Vd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_sha512.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_sha512.cpp index 723dbfcb..f87c29cb 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_sha512.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_sha512.cpp @@ -20,7 +20,7 @@ IR::U64 MakeMNSig(IREmitter& ir, IR::U64 data, u8 first_rot_amount, u8 second_ro const IR::U64 tmp2 = ir.RotateRight(data, ir.Imm8(second_rot_amount)); const IR::U64 tmp3 = ir.RotateRight(data, ir.Imm8(third_rot_amount)); - return ir.Eor(tmp1, ir.Eor(tmp2, tmp3)); + return ir.Eor(tmp1, ir.Eor(tmp2, tmp3)); } enum class SHA512HashPart { @@ -59,7 +59,7 @@ IR::U128 SHA512Hash(IREmitter& ir, Vec Vm, Vec Vn, Vec Vd, SHA512HashPart part) return ir.Eor(tmp1, ir.Eor(tmp2, tmp3)); }; - const IR::U64 Vtmp = [&] { + const IR::U64 Vtmp = [&] { const IR::U64 partial = [&] { if (part == SHA512HashPart::Part1) { return make_partial_half(upper_y, lower_x, upper_x); @@ -147,7 +147,7 @@ IR::U128 SM4Hash(IREmitter& ir, Vec Vn, Vec Vd, SM4RotationType type) { return roundresult; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::SHA512SU0(Vec Vn, Vec Vd) { const IR::U128 x = ir.GetQ(Vn); @@ -297,4 +297,4 @@ bool TranslatorVisitor::SM4EKEY(Vec Vm, Vec Vn, Vec Vd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp index 5185b917..6ffc7f6d 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp @@ -47,8 +47,7 @@ IR::U128 PerformRoundingCorrection(TranslatorVisitor& v, size_t esize, u64 round return v.ir.VectorSub(esize, shifted, round_correction); } -bool ShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, - Rounding rounding, Accumulating accumulating, Signedness signedness) { +bool ShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, Rounding rounding, Accumulating accumulating, Signedness signedness) { if (immh == 0b0000) { return v.DecodeError(); } @@ -85,8 +84,7 @@ bool ShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, return true; } -bool ShiftRightNarrowing(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, - Rounding rounding, Narrowing narrowing, Signedness signedness) { +bool ShiftRightNarrowing(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, Rounding rounding, Narrowing narrowing, Signedness signedness) { if (immh == 0b0000) { return v.DecodeError(); } @@ -135,8 +133,7 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, return true; } -bool ShiftLeftLong(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, - Signedness signedness) { +bool ShiftLeftLong(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, Signedness signedness) { if (immh == 0b0000) { return v.DecodeError(); } @@ -214,12 +211,12 @@ bool ConvertFloat(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn switch (direction) { case FloatConversionDirection::FixedToFloat: return signedness == Signedness::Signed - ? v.ir.FPVectorFromSignedFixed(esize, operand, fbits, rounding_mode) - : v.ir.FPVectorFromUnsignedFixed(esize, operand, fbits, rounding_mode); + ? v.ir.FPVectorFromSignedFixed(esize, operand, fbits, rounding_mode) + : v.ir.FPVectorFromUnsignedFixed(esize, operand, fbits, rounding_mode); case FloatConversionDirection::FloatToFixed: return signedness == Signedness::Signed - ? v.ir.FPVectorToSignedFixed(esize, operand, fbits, rounding_mode) - : v.ir.FPVectorToUnsignedFixed(esize, operand, fbits, rounding_mode); + ? v.ir.FPVectorToSignedFixed(esize, operand, fbits, rounding_mode) + : v.ir.FPVectorToUnsignedFixed(esize, operand, fbits, rounding_mode); } UNREACHABLE(); }(); @@ -228,7 +225,7 @@ bool ConvertFloat(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::SSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::None, Accumulating::None, Signedness::Signed); @@ -401,4 +398,4 @@ bool TranslatorVisitor::FCVTZU_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, V return ConvertFloat(*this, Q, immh, immb, Vn, Vd, Signedness::Unsigned, FloatConversionDirection::FloatToFixed, FP::RoundingMode::TowardsZero); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_table_lookup.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_table_lookup.cpp index 4565fdfd..319517d0 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_table_lookup.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_table_lookup.cpp @@ -10,7 +10,7 @@ namespace Dynarmic::A64 { static bool TableLookup(TranslatorVisitor& v, bool Q, Vec Vm, Imm<2> len, bool is_tbl, size_t Vn, Vec Vd) { const size_t datasize = Q ? 128 : 64; - const IR::Table table = v.ir.VectorTable([&]{ + const IR::Table table = v.ir.VectorTable([&] { std::vector result; for (size_t i = 0; i < len.ZeroExtend() + 1; ++i) { result.emplace_back(v.ir.GetQ(static_cast((Vn + i) % 32))); @@ -35,4 +35,4 @@ bool TranslatorVisitor::TBX(bool Q, Vec Vm, Imm<2> len, size_t Vn, Vec Vd) { return TableLookup(*this, Q, Vm, len, false, Vn, Vd); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_three_different.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_three_different.cpp index 5728c0b6..2de931ed 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_three_different.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_three_different.cpp @@ -17,8 +17,7 @@ enum class Signedness { Unsigned }; -bool AbsoluteDifferenceLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, - AbsoluteDifferenceBehavior behavior, Signedness sign) { +bool AbsoluteDifferenceLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, AbsoluteDifferenceBehavior behavior, Signedness sign) { if (size == 0b11) { return v.ReservedValue(); } @@ -46,8 +45,7 @@ enum class MultiplyLongBehavior { Subtract }; -bool MultiplyLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, - MultiplyLongBehavior behavior, Signedness sign) { +bool MultiplyLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, MultiplyLongBehavior behavior, Signedness sign) { if (size == 0b11) { return v.ReservedValue(); } @@ -90,8 +88,7 @@ enum class LongOperationBehavior { Subtraction }; -bool LongOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, - LongOperationBehavior behavior, Signedness sign) { +bool LongOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, LongOperationBehavior behavior, Signedness sign) { if (size == 0b11) { return v.ReservedValue(); } @@ -128,8 +125,7 @@ enum class WideOperationBehavior { Subtraction }; -bool WideOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, - WideOperationBehavior behavior, Signedness sign) { +bool WideOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, WideOperationBehavior behavior, Signedness sign) { if (size == 0b11) { return v.ReservedValue(); } @@ -158,7 +154,7 @@ bool WideOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Ve v.V(128, Vd, result); return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::PMULL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { if (size == 0b01 || size == 0b10) { @@ -264,4 +260,4 @@ bool TranslatorVisitor::SQDMULL_vec_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec V return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp index ade09a48..34939c83 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_three_same.cpp @@ -17,8 +17,7 @@ enum class ExtraBehavior { Round }; -bool HighNarrowingOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, - Operation op, ExtraBehavior behavior) { +bool HighNarrowingOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, Operation op, ExtraBehavior behavior) { if (size == 0b11) { return v.ReservedValue(); } @@ -171,8 +170,7 @@ enum class MinMaxOperation { Max, }; -bool VectorMinMaxOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, - MinMaxOperation operation, Signedness sign) { +bool VectorMinMaxOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, MinMaxOperation operation, Signedness sign) { if (size == 0b11) { return v.ReservedValue(); } @@ -227,8 +225,7 @@ bool FPMinMaxOperation(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Ve return true; } -bool FPMinMaxNumericOperation(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd, - IR::U32U64 (IREmitter::* fn)(const IR::U32U64&, const IR::U32U64&)) { +bool FPMinMaxNumericOperation(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd, IR::U32U64 (IREmitter::*fn)(const IR::U32U64&, const IR::U32U64&)) { if (sz && !Q) { return v.ReservedValue(); } @@ -253,8 +250,7 @@ bool FPMinMaxNumericOperation(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec return true; } -bool PairedMinMaxOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, - MinMaxOperation operation, Signedness sign) { +bool PairedMinMaxOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, MinMaxOperation operation, Signedness sign) { if (size == 0b11) { return v.ReservedValue(); } @@ -291,8 +287,7 @@ bool PairedMinMaxOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Ve return true; } -bool FPPairedMinMax(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd, - IR::U32U64 (IREmitter::* fn)(const IR::U32U64&, const IR::U32U64&)) { +bool FPPairedMinMax(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd, IR::U32U64 (IREmitter::*fn)(const IR::U32U64&, const IR::U32U64&)) { if (sz && !Q) { return v.ReservedValue(); } @@ -323,8 +318,7 @@ bool FPPairedMinMax(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Vec V return true; } -bool SaturatingArithmeticOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, - Operation op, Signedness sign) { +bool SaturatingArithmeticOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, Operation op, Signedness sign) { if (size == 0b11 && !Q) { return v.ReservedValue(); } @@ -377,7 +371,7 @@ bool SaturatingShiftLeft(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::CMGT_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { if (size == 0b11 && !Q) { @@ -1251,4 +1245,4 @@ bool TranslatorVisitor::BSL(bool Q, Vec Vm, Vec Vn, Vec Vd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_three_same_extra.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_three_same_extra.cpp index 068be030..d18f4b10 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_three_same_extra.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_three_same_extra.cpp @@ -10,8 +10,7 @@ namespace { using ExtensionFunction = IR::U32 (IREmitter::*)(const IR::UAny&); -bool DotProduct(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, - ExtensionFunction extension) { +bool DotProduct(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, ExtensionFunction extension) { if (size != 0b10) { return v.ReservedValue(); } @@ -42,7 +41,7 @@ bool DotProduct(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec V return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::SDOT_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { return DotProduct(*this, Q, size, Vm, Vn, Vd, &IREmitter::SignExtendToWord); @@ -86,25 +85,25 @@ bool TranslatorVisitor::FCMLA_vec(bool Q, Imm<2> size, Vec Vm, Imm<2> rot, Vec V const size_t second = first + 1; switch (rot.ZeroExtend()) { - case 0b00: // 0 degrees + case 0b00: // 0 degrees element1 = ir.VectorGetElement(esize, operand2, first); element2 = ir.VectorGetElement(esize, operand1, first); element3 = ir.VectorGetElement(esize, operand2, second); element4 = ir.VectorGetElement(esize, operand1, first); break; - case 0b01: // 90 degrees + case 0b01: // 90 degrees element1 = ir.FPNeg(ir.VectorGetElement(esize, operand2, second)); element2 = ir.VectorGetElement(esize, operand1, second); element3 = ir.VectorGetElement(esize, operand2, first); element4 = ir.VectorGetElement(esize, operand1, second); break; - case 0b10: // 180 degrees + case 0b10: // 180 degrees element1 = ir.FPNeg(ir.VectorGetElement(esize, operand2, first)); element2 = ir.VectorGetElement(esize, operand1, first); element3 = ir.FPNeg(ir.VectorGetElement(esize, operand2, second)); element4 = ir.VectorGetElement(esize, operand1, first); break; - case 0b11: // 270 degrees + case 0b11: // 270 degrees element1 = ir.VectorGetElement(esize, operand2, second); element2 = ir.VectorGetElement(esize, operand1, second); element3 = ir.FPNeg(ir.VectorGetElement(esize, operand2, first)); @@ -172,4 +171,4 @@ bool TranslatorVisitor::FCADD_vec(bool Q, Imm<2> size, Vec Vm, Imm<1> rot, Vec V return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp index 0a7dbc1a..77509754 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_two_register_misc.cpp @@ -97,8 +97,8 @@ bool IntegerConvertToFloat(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd const IR::U128 operand = v.V(datasize, Vn); const IR::U128 result = signedness == Signedness::Signed - ? v.ir.FPVectorFromSignedFixed(esize, operand, 0, rounding_mode) - : v.ir.FPVectorFromUnsignedFixed(esize, operand, 0, rounding_mode); + ? v.ir.FPVectorFromSignedFixed(esize, operand, 0, rounding_mode) + : v.ir.FPVectorFromUnsignedFixed(esize, operand, 0, rounding_mode); v.V(datasize, Vd, result); return true; @@ -114,8 +114,8 @@ bool FloatConvertToInteger(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd const IR::U128 operand = v.V(datasize, Vn); const IR::U128 result = signedness == Signedness::Signed - ? v.ir.FPVectorToSignedFixed(esize, operand, 0, rounding_mode) - : v.ir.FPVectorToUnsignedFixed(esize, operand, 0, rounding_mode); + ? v.ir.FPVectorToSignedFixed(esize, operand, 0, rounding_mode) + : v.ir.FPVectorToUnsignedFixed(esize, operand, 0, rounding_mode); v.V(datasize, Vd, result); return true; @@ -168,8 +168,7 @@ enum class PairedAddLongExtraBehavior { Accumulate, }; -bool PairedAddLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, Signedness sign, - PairedAddLongExtraBehavior behavior) { +bool PairedAddLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, Signedness sign, PairedAddLongExtraBehavior behavior) { if (size == 0b11) { return v.ReservedValue(); } @@ -198,7 +197,7 @@ bool PairedAddLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, Si return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::CLS_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) { if (size == 0b11) { @@ -524,7 +523,7 @@ bool TranslatorVisitor::FRINTI_1(bool Q, Vec Vn, Vec Vd) { } bool TranslatorVisitor::FRINTI_2(bool Q, bool sz, Vec Vn, Vec Vd) { - return FloatRoundToIntegral(*this, Q, sz, Vn, Vd,ir.current_location->FPCR().RMode(), false); + return FloatRoundToIntegral(*this, Q, sz, Vn, Vd, ir.current_location->FPCR().RMode(), false); } bool TranslatorVisitor::FRECPE_3(bool Q, Vec Vn, Vec Vd) { @@ -740,14 +739,14 @@ bool TranslatorVisitor::REV64_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) { ir.VectorLogicalShiftLeft(esize, data, shift)); switch (zext_size) { - case 0: // 8-bit elements - result = ir.VectorShuffleLowHalfwords(result, 0b00011011); - result = ir.VectorShuffleHighHalfwords(result, 0b00011011); - break; - case 1: // 16-bit elements - result = ir.VectorShuffleLowHalfwords(result, 0b01001110); - result = ir.VectorShuffleHighHalfwords(result, 0b01001110); - break; + case 0: // 8-bit elements + result = ir.VectorShuffleLowHalfwords(result, 0b00011011); + result = ir.VectorShuffleHighHalfwords(result, 0b00011011); + break; + case 1: // 16-bit elements + result = ir.VectorShuffleLowHalfwords(result, 0b01001110); + result = ir.VectorShuffleHighHalfwords(result, 0b01001110); + break; } V(datasize, Vd, result); @@ -882,4 +881,4 @@ bool TranslatorVisitor::SHLL(bool Q, Imm<2> size, Vec Vn, Vec Vd) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp index 1f3d58f5..d58e3119 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp @@ -4,6 +4,7 @@ */ #include + #include "dynarmic/common/assert.h" #include "dynarmic/frontend/A64/translate/impl/impl.h" @@ -24,8 +25,7 @@ enum class ExtraBehavior { Subtract, }; -bool MultiplyByElement(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, - ExtraBehavior extra_behavior) { +bool MultiplyByElement(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { if (size != 0b01 && size != 0b10) { return v.ReservedValue(); } @@ -50,8 +50,7 @@ bool MultiplyByElement(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm< return true; } -bool FPMultiplyByElement(TranslatorVisitor& v, bool Q, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, - ExtraBehavior extra_behavior) { +bool FPMultiplyByElement(TranslatorVisitor& v, bool Q, bool sz, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { if (sz && L == 1) { return v.ReservedValue(); } @@ -70,7 +69,7 @@ bool FPMultiplyByElement(TranslatorVisitor& v, bool Q, bool sz, Imm<1> L, Imm<1> const IR::U128 operand2 = Q ? v.ir.VectorBroadcast(esize, element2) : v.ir.VectorBroadcastLower(esize, element2); const IR::U128 operand3 = v.V(datasize, Vd); - const IR::U128 result = [&]{ + const IR::U128 result = [&] { switch (extra_behavior) { case ExtraBehavior::None: return v.ir.FPVectorMul(esize, operand1, operand2); @@ -87,8 +86,7 @@ bool FPMultiplyByElement(TranslatorVisitor& v, bool Q, bool sz, Imm<1> L, Imm<1> return true; } -bool FPMultiplyByElementHalfPrecision(TranslatorVisitor& v, bool Q, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, - Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { +bool FPMultiplyByElementHalfPrecision(TranslatorVisitor& v, bool Q, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { const size_t idxdsize = H == 1 ? 128 : 64; const size_t index = concatenate(H, L, M).ZeroExtend(); const Vec Vm = Vmlo.ZeroExtend(); @@ -102,7 +100,7 @@ bool FPMultiplyByElementHalfPrecision(TranslatorVisitor& v, bool Q, Imm<1> L, Im // TODO: We currently don't implement half-precision paths for // regular multiplies and extended multiplies. - const IR::U128 result = [&]{ + const IR::U128 result = [&] { switch (extra_behavior) { case ExtraBehavior::None: break; @@ -121,8 +119,7 @@ bool FPMultiplyByElementHalfPrecision(TranslatorVisitor& v, bool Q, Imm<1> L, Im using ExtensionFunction = IR::U32 (IREmitter::*)(const IR::UAny&); -bool DotProduct(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, - Vec Vn, Vec Vd, ExtensionFunction extension) { +bool DotProduct(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, ExtensionFunction extension) { if (size != 0b10) { return v.ReservedValue(); } @@ -160,8 +157,7 @@ enum class Signedness { Unsigned }; -bool MultiplyLong(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, - Imm<1> H, Vec Vn, Vec Vd, ExtraBehavior extra_behavior, Signedness sign) { +bool MultiplyLong(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd, ExtraBehavior extra_behavior, Signedness sign) { if (size == 0b00 || size == 0b11) { return v.ReservedValue(); } @@ -203,7 +199,7 @@ bool MultiplyLong(TranslatorVisitor& v, bool Q, Imm<2> size, Imm<1> L, Imm<1> M, v.V(2 * datasize, Vd, result); return true; } -} // Anonymous namespace +} // Anonymous namespace bool TranslatorVisitor::MLA_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4> Vmlo, Imm<1> H, Vec Vn, Vec Vd) { return MultiplyByElement(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::Accumulate); @@ -267,30 +263,30 @@ bool TranslatorVisitor::FCMLA_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4 const size_t index_second = index_first + 1; switch (rot.ZeroExtend()) { - case 0b00: // 0 degrees - element1 = ir.VectorGetElement(esize, operand2, index_first); - element2 = ir.VectorGetElement(esize, operand1, first); - element3 = ir.VectorGetElement(esize, operand2, index_second); - element4 = ir.VectorGetElement(esize, operand1, first); - break; - case 0b01: // 90 degrees - element1 = ir.FPNeg(ir.VectorGetElement(esize, operand2, index_second)); - element2 = ir.VectorGetElement(esize, operand1, second); - element3 = ir.VectorGetElement(esize, operand2, index_first); - element4 = ir.VectorGetElement(esize, operand1, second); - break; - case 0b10: // 180 degrees - element1 = ir.FPNeg(ir.VectorGetElement(esize, operand2, index_first)); - element2 = ir.VectorGetElement(esize, operand1, first); - element3 = ir.FPNeg(ir.VectorGetElement(esize, operand2, index_second)); - element4 = ir.VectorGetElement(esize, operand1, first); - break; - case 0b11: // 270 degrees - element1 = ir.VectorGetElement(esize, operand2, index_second); - element2 = ir.VectorGetElement(esize, operand1, second); - element3 = ir.FPNeg(ir.VectorGetElement(esize, operand2, index_first)); - element4 = ir.VectorGetElement(esize, operand1, second); - break; + case 0b00: // 0 degrees + element1 = ir.VectorGetElement(esize, operand2, index_first); + element2 = ir.VectorGetElement(esize, operand1, first); + element3 = ir.VectorGetElement(esize, operand2, index_second); + element4 = ir.VectorGetElement(esize, operand1, first); + break; + case 0b01: // 90 degrees + element1 = ir.FPNeg(ir.VectorGetElement(esize, operand2, index_second)); + element2 = ir.VectorGetElement(esize, operand1, second); + element3 = ir.VectorGetElement(esize, operand2, index_first); + element4 = ir.VectorGetElement(esize, operand1, second); + break; + case 0b10: // 180 degrees + element1 = ir.FPNeg(ir.VectorGetElement(esize, operand2, index_first)); + element2 = ir.VectorGetElement(esize, operand1, first); + element3 = ir.FPNeg(ir.VectorGetElement(esize, operand2, index_second)); + element4 = ir.VectorGetElement(esize, operand1, first); + break; + case 0b11: // 270 degrees + element1 = ir.VectorGetElement(esize, operand2, index_second); + element2 = ir.VectorGetElement(esize, operand1, second); + element3 = ir.FPNeg(ir.VectorGetElement(esize, operand2, index_first)); + element4 = ir.VectorGetElement(esize, operand1, second); + break; } const IR::U32U64 operand3_elem1 = ir.VectorGetElement(esize, operand3, first); @@ -419,4 +415,4 @@ bool TranslatorVisitor::UMULL_elt(bool Q, Imm<2> size, Imm<1> L, Imm<1> M, Imm<4 return MultiplyLong(*this, Q, size, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::None, Signedness::Unsigned); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/sys_dc.cpp b/src/dynarmic/frontend/A64/translate/impl/sys_dc.cpp index 7b0fcda2..aea3b5ba 100644 --- a/src/dynarmic/frontend/A64/translate/impl/sys_dc.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/sys_dc.cpp @@ -48,4 +48,4 @@ bool TranslatorVisitor::DC_CIVAC(Reg Rt) { return DataCacheInstruction(*this, DataCacheOperation::CleanAndInvalidateByVAToPoC, Rt); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/sys_ic.cpp b/src/dynarmic/frontend/A64/translate/impl/sys_ic.cpp index c06e5fa2..35fa2408 100644 --- a/src/dynarmic/frontend/A64/translate/impl/sys_ic.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/sys_ic.cpp @@ -22,4 +22,4 @@ bool TranslatorVisitor::IC_IVAU(Reg Rt) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/system.cpp b/src/dynarmic/frontend/A64/translate/impl/system.cpp index 82a3793f..9c35a8f3 100644 --- a/src/dynarmic/frontend/A64/translate/impl/system.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/system.cpp @@ -154,9 +154,8 @@ bool TranslatorVisitor::MRS(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3 case SystemRegisterEncoding::TPIDRRO_EL0: X(64, Rt, ir.GetTPIDRRO()); return true; - } return InterpretThisInstruction(); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/system_flag_format.cpp b/src/dynarmic/frontend/A64/translate/impl/system_flag_format.cpp index 12e3cbd1..402fe6c9 100644 --- a/src/dynarmic/frontend/A64/translate/impl/system_flag_format.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/system_flag_format.cpp @@ -43,4 +43,4 @@ bool TranslatorVisitor::XAFlag() { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/impl/system_flag_manipulation.cpp b/src/dynarmic/frontend/A64/translate/impl/system_flag_manipulation.cpp index 2be76f50..65ec23e7 100644 --- a/src/dynarmic/frontend/A64/translate/impl/system_flag_manipulation.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/system_flag_manipulation.cpp @@ -59,4 +59,4 @@ bool TranslatorVisitor::RMIF(Imm<6> lsb, Reg Rn, Imm<4> mask) { return true; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/translate.cpp b/src/dynarmic/frontend/A64/translate/translate.cpp index aa96d481..4f7d3efc 100644 --- a/src/dynarmic/frontend/A64/translate/translate.cpp +++ b/src/dynarmic/frontend/A64/translate/translate.cpp @@ -3,10 +3,11 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/frontend/A64/translate/translate.h" + #include "dynarmic/frontend/A64/decoder/a64.h" #include "dynarmic/frontend/A64/location_descriptor.h" #include "dynarmic/frontend/A64/translate/impl/impl.h" -#include "dynarmic/frontend/A64/translate/translate.h" #include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/terminal.h" @@ -62,4 +63,4 @@ bool TranslateSingleInstruction(IR::Block& block, LocationDescriptor descriptor, return should_continue; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/translate/translate.h b/src/dynarmic/frontend/A64/translate/translate.h index 9a564348..9ab6d264 100644 --- a/src/dynarmic/frontend/A64/translate/translate.h +++ b/src/dynarmic/frontend/A64/translate/translate.h @@ -12,7 +12,7 @@ namespace Dynarmic { namespace IR { class Block; -} // namespace IR +} // namespace IR namespace A64 { @@ -54,5 +54,5 @@ IR::Block Translate(LocationDescriptor descriptor, MemoryReadCodeFuncType memory */ bool TranslateSingleInstruction(IR::Block& block, LocationDescriptor descriptor, u32 instruction); -} // namespace A64 -} // namespace Dynarmic +} // namespace A64 +} // namespace Dynarmic diff --git a/src/dynarmic/frontend/A64/types.cpp b/src/dynarmic/frontend/A64/types.cpp index f4047811..b0dbfb2e 100644 --- a/src/dynarmic/frontend/A64/types.cpp +++ b/src/dynarmic/frontend/A64/types.cpp @@ -3,20 +3,19 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/frontend/A64/types.h" + #include #include #include -#include "dynarmic/frontend/A64/types.h" - namespace Dynarmic::A64 { const char* CondToString(Cond cond) { static constexpr std::array cond_strs = { "eq", "ne", "hs", "lo", "mi", "pl", "vs", "vc", - "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" - }; + "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"}; return cond_strs.at(static_cast(cond)); } @@ -41,4 +40,4 @@ std::ostream& operator<<(std::ostream& o, Vec vec) { return o; } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/A64/types.h b/src/dynarmic/frontend/A64/types.h index 3d585221..6e12754c 100644 --- a/src/dynarmic/frontend/A64/types.h +++ b/src/dynarmic/frontend/A64/types.h @@ -17,19 +17,76 @@ namespace Dynarmic::A64 { using Cond = IR::Cond; enum class Reg { - R0, R1, R2, R3, R4, R5, R6, R7, - R8, R9, R10, R11, R12, R13, R14, R15, - R16, R17, R18, R19, R20, R21, R22, R23, - R24, R25, R26, R27, R28, R29, R30, R31, + R0, + R1, + R2, + R3, + R4, + R5, + R6, + R7, + R8, + R9, + R10, + R11, + R12, + R13, + R14, + R15, + R16, + R17, + R18, + R19, + R20, + R21, + R22, + R23, + R24, + R25, + R26, + R27, + R28, + R29, + R30, + R31, LR = R30, - SP = R31, ZR = R31, + SP = R31, + ZR = R31, }; enum class Vec { - V0, V1, V2, V3, V4, V5, V6, V7, - V8, V9, V10, V11, V12, V13, V14, V15, - V16, V17, V18, V19, V20, V21, V22, V23, - V24, V25, V26, V27, V28, V29, V30, V31, + V0, + V1, + V2, + V3, + V4, + V5, + V6, + V7, + V8, + V9, + V10, + V11, + V12, + V13, + V14, + V15, + V16, + V17, + V18, + V19, + V20, + V21, + V22, + V23, + V24, + V25, + V26, + V27, + V28, + V29, + V30, + V31, }; enum class ShiftType { @@ -68,4 +125,4 @@ inline Vec operator+(Vec vec, size_t number) { return static_cast(new_vec); } -} // namespace Dynarmic::A64 +} // namespace Dynarmic::A64 diff --git a/src/dynarmic/frontend/decoder/decoder_detail.h b/src/dynarmic/frontend/decoder/decoder_detail.h index 1091dd70..9890dc6b 100644 --- a/src/dynarmic/frontend/decoder/decoder_detail.h +++ b/src/dynarmic/frontend/decoder/decoder_detail.h @@ -17,7 +17,7 @@ namespace Dynarmic::Decoder { namespace detail { -template +template inline constexpr std::array StringToArray(const char (&str)[N + 1]) { std::array result; for (size_t i = 0; i < N; i++) { @@ -33,7 +33,7 @@ inline constexpr std::array StringToArray(const char (&str)[N + 1]) { */ template struct detail { - using opcode_type = typename MatcherT::opcode_type; + using opcode_type = typename MatcherT::opcode_type; using visitor_type = typename MatcherT::visitor_type; static constexpr size_t opcode_bitsize = Common::BitSize(); @@ -93,7 +93,8 @@ struct detail { if constexpr (N > 0) { const size_t bit_position = opcode_bitsize - i - 1; - if (arg_index >= N) throw std::out_of_range("Unexpected field"); + if (arg_index >= N) + throw std::out_of_range("Unexpected field"); masks[arg_index] |= static_cast(1) << bit_position; shifts[arg_index] = bit_position; @@ -103,7 +104,7 @@ struct detail { } } - ASSERT(std::all_of(masks.begin(), masks.end(), [](auto m){ return m != 0; })); + ASSERT(std::all_of(masks.begin(), masks.end(), [](auto m) { return m != 0; })); return std::make_tuple(masks, shifts); } @@ -117,14 +118,14 @@ struct detail { struct VisitorCaller; #ifdef _MSC_VER -#pragma warning(push) -#pragma warning(disable:4800) // forcing value to bool 'true' or 'false' (performance warning) +# pragma warning(push) +# pragma warning(disable : 4800) // forcing value to bool 'true' or 'false' (performance warning) #endif - template - struct VisitorCaller { - template + template + struct VisitorCaller { + template static auto Make(std::integer_sequence, - CallRetT (Visitor::* const fn)(Args...), + CallRetT (Visitor::*const fn)(Args...), const std::array arg_masks, const std::array arg_shifts) { static_assert(std::is_same_v, "Member function is not from Matcher's Visitor"); @@ -137,11 +138,11 @@ struct detail { } }; - template - struct VisitorCaller { - template + template + struct VisitorCaller { + template static auto Make(std::integer_sequence, - CallRetT (Visitor::* const fn)(Args...) const, + CallRetT (Visitor::*const fn)(Args...) const, const std::array arg_masks, const std::array arg_shifts) { static_assert(std::is_same_v, "Member function is not from Matcher's Visitor"); @@ -154,7 +155,7 @@ struct detail { } }; #ifdef _MSC_VER -#pragma warning(pop) +# pragma warning(pop) #endif /** @@ -175,5 +176,5 @@ struct detail { #define DYNARMIC_DECODER_GET_MATCHER(MatcherT, fn, name, bitstring) Decoder::detail::detail>::GetMatcher(&V::fn, name, Decoder::detail::detail>::GetMaskAndExpect(bitstring), Decoder::detail::detail>::template GetArgInfo>(bitstring)) -} // namespace detail -} // namespace Dynarmic::Decoder +} // namespace detail +} // namespace Dynarmic::Decoder diff --git a/src/dynarmic/frontend/decoder/matcher.h b/src/dynarmic/frontend/decoder/matcher.h index 46052c3b..54c2d116 100644 --- a/src/dynarmic/frontend/decoder/matcher.h +++ b/src/dynarmic/frontend/decoder/matcher.h @@ -21,16 +21,16 @@ namespace Dynarmic::Decoder { * @tparam OpcodeType Type representing an opcode. This must be the * type of the second parameter in a handler function. */ -template +template class Matcher { public: - using opcode_type = OpcodeType; - using visitor_type = Visitor; + using opcode_type = OpcodeType; + using visitor_type = Visitor; using handler_return_type = typename Visitor::instruction_return_type; - using handler_function = std::function; + using handler_function = std::function; Matcher(const char* const name, opcode_type mask, opcode_type expected, handler_function func) - : name{name}, mask{mask}, expected{expected}, fn{std::move(func)} {} + : name{name}, mask{mask}, expected{expected}, fn{std::move(func)} {} /// Gets the name of this type of instruction. const char* GetName() const { @@ -73,4 +73,4 @@ private: handler_function fn; }; -} // namespace Dynarmic::Decoder +} // namespace Dynarmic::Decoder diff --git a/src/dynarmic/frontend/imm.cpp b/src/dynarmic/frontend/imm.cpp index 0bd305c1..72d1e8fe 100644 --- a/src/dynarmic/frontend/imm.cpp +++ b/src/dynarmic/frontend/imm.cpp @@ -3,10 +3,11 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/frontend/imm.h" + #include "dynarmic/common/assert.h" #include "dynarmic/common/bit_util.h" #include "dynarmic/common/common_types.h" -#include "dynarmic/frontend/imm.h" namespace Dynarmic { @@ -63,4 +64,4 @@ u64 AdvSIMDExpandImm(bool op, Imm<4> cmode, Imm<8> imm8) { UNREACHABLE(); } -} // namespace Dynarmic +} // namespace Dynarmic diff --git a/src/dynarmic/frontend/imm.h b/src/dynarmic/frontend/imm.h index d05c9f7c..d534d866 100644 --- a/src/dynarmic/frontend/imm.h +++ b/src/dynarmic/frontend/imm.h @@ -16,34 +16,35 @@ namespace Dynarmic { * Imm represents an immediate value in an AArch32/AArch64 instruction. * Imm is used during translation as a typesafe way of passing around immediates of fixed sizes. */ -template +template class Imm { public: static constexpr size_t bit_size = bit_size_; - explicit Imm(u32 value) : value(value) { - ASSERT_MSG((Common::Bits<0, bit_size-1>(value) == value), "More bits in value than expected"); + explicit Imm(u32 value) + : value(value) { + ASSERT_MSG((Common::Bits<0, bit_size - 1>(value) == value), "More bits in value than expected"); } - template + template T ZeroExtend() const { static_assert(Common::BitSize() >= bit_size); return static_cast(value); } - template + template T SignExtend() const { static_assert(Common::BitSize() >= bit_size); return Common::SignExtend(value); } - template + template bool Bit() const { static_assert(bit < bit_size); return Common::Bit(value); } - template + template T Bits() const { static_assert(begin_bit <= end_bit && end_bit < bit_size); static_assert(Common::BitSize() >= end_bit - begin_bit + 1); @@ -81,62 +82,62 @@ private: u32 value; }; -template +template bool operator==(u32 a, Imm b) { return Imm{a} == b; } -template +template bool operator==(Imm a, u32 b) { return Imm{b} == a; } -template +template bool operator!=(u32 a, Imm b) { return !operator==(a, b); } -template +template bool operator!=(Imm a, u32 b) { return !operator==(a, b); } -template +template bool operator<(u32 a, Imm b) { return Imm{a} < b; } -template +template bool operator<(Imm a, u32 b) { return a < Imm{b}; } -template +template bool operator<=(u32 a, Imm b) { return !operator<(b, a); } -template +template bool operator<=(Imm a, u32 b) { return !operator<(b, a); } -template +template bool operator>(u32 a, Imm b) { return operator<(b, a); } -template +template bool operator>(Imm a, u32 b) { return operator<(b, a); } -template +template bool operator>=(u32 a, Imm b) { return !operator<(a, b); } -template +template bool operator>=(Imm a, u32 b) { return !operator<(a, b); } @@ -146,8 +147,8 @@ bool operator>=(Imm a, u32 b) { * Left to right corresponds to most significant imm to least significant imm. * This is equivalent to a:b:...:z in ASL. */ -template -auto concatenate(Imm first, Imm ...rest) { +template +auto concatenate(Imm first, Imm... rest) { if constexpr (sizeof...(rest) == 0) { return first; } else { @@ -160,4 +161,4 @@ auto concatenate(Imm first, Imm ...rest) { /// Expands an Advanced SIMD modified immediate. u64 AdvSIMDExpandImm(bool op, Imm<4> cmode, Imm<8> imm8); -} // namespace Dynarmic +} // namespace Dynarmic diff --git a/src/dynarmic/interface/A32/a32.h b/src/dynarmic/interface/A32/a32.h index c8db60fe..26d55539 100644 --- a/src/dynarmic/interface/A32/a32.h +++ b/src/dynarmic/interface/A32/a32.h @@ -101,5 +101,5 @@ private: std::unique_ptr impl; }; -} // namespace A32 -} // namespace Dynarmic +} // namespace A32 +} // namespace Dynarmic diff --git a/src/dynarmic/interface/A32/arch_version.h b/src/dynarmic/interface/A32/arch_version.h index 86bb9e0f..240e40ee 100644 --- a/src/dynarmic/interface/A32/arch_version.h +++ b/src/dynarmic/interface/A32/arch_version.h @@ -19,5 +19,5 @@ enum class ArchVersion { v8, }; -} // namespace A32 -} // namespace Dynarmic +} // namespace A32 +} // namespace Dynarmic diff --git a/src/dynarmic/interface/A32/config.h b/src/dynarmic/interface/A32/config.h index 43a49c9d..1839eb1a 100644 --- a/src/dynarmic/interface/A32/config.h +++ b/src/dynarmic/interface/A32/config.h @@ -16,7 +16,7 @@ namespace Dynarmic { class ExclusiveMonitor; -} // namespace Dynarmic +} // namespace Dynarmic namespace Dynarmic { namespace A32 { @@ -205,11 +205,11 @@ struct UserConfig { // Minimum size is about 8MiB. Maximum size is about 2GiB. Maximum size is limited by // the maximum length of a x64 jump. - size_t code_cache_size = 256 * 1024 * 1024; // bytes + size_t code_cache_size = 256 * 1024 * 1024; // bytes // Determines the relative size of the near and far code caches. Must be smaller than // code_cache_size. - size_t far_code_offset = 200 * 1024 * 1024; // bytes + size_t far_code_offset = 200 * 1024 * 1024; // bytes }; -} // namespace A32 -} // namespace Dynarmic +} // namespace A32 +} // namespace Dynarmic diff --git a/src/dynarmic/interface/A32/context.h b/src/dynarmic/interface/A32/context.h index 7ee0c7ef..74876b1b 100644 --- a/src/dynarmic/interface/A32/context.h +++ b/src/dynarmic/interface/A32/context.h @@ -41,5 +41,5 @@ private: std::unique_ptr impl; }; -} // namespace A32 -} // namespace Dynarmic +} // namespace A32 +} // namespace Dynarmic diff --git a/src/dynarmic/interface/A32/coprocessor.h b/src/dynarmic/interface/A32/coprocessor.h index 0b69891c..71b3f5a4 100644 --- a/src/dynarmic/interface/A32/coprocessor.h +++ b/src/dynarmic/interface/A32/coprocessor.h @@ -106,5 +106,5 @@ public: virtual std::optional CompileStoreWords(bool two, bool long_transfer, CoprocReg CRd, std::optional option) = 0; }; -} // namespace A32 -} // namespace Dynarmic +} // namespace A32 +} // namespace Dynarmic diff --git a/src/dynarmic/interface/A32/coprocessor_util.h b/src/dynarmic/interface/A32/coprocessor_util.h index ec7c1abb..ed695d17 100644 --- a/src/dynarmic/interface/A32/coprocessor_util.h +++ b/src/dynarmic/interface/A32/coprocessor_util.h @@ -9,8 +9,23 @@ namespace Dynarmic { namespace A32 { enum class CoprocReg { - C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15 + C0, + C1, + C2, + C3, + C4, + C5, + C6, + C7, + C8, + C9, + C10, + C11, + C12, + C13, + C14, + C15 }; -} // namespace A32 -} // namespace Dynarmic +} // namespace A32 +} // namespace Dynarmic diff --git a/src/dynarmic/interface/A32/disassembler.h b/src/dynarmic/interface/A32/disassembler.h index 8273a30d..54058bf5 100644 --- a/src/dynarmic/interface/A32/disassembler.h +++ b/src/dynarmic/interface/A32/disassembler.h @@ -14,5 +14,5 @@ namespace A32 { std::string DisassembleArm(std::uint32_t instruction); std::string DisassembleThumb16(std::uint16_t instruction); -} // namespace A32 -} // namespace Dynarmic +} // namespace A32 +} // namespace Dynarmic diff --git a/src/dynarmic/interface/A64/a64.h b/src/dynarmic/interface/A64/a64.h index 541b449d..f098dcea 100644 --- a/src/dynarmic/interface/A64/a64.h +++ b/src/dynarmic/interface/A64/a64.h @@ -125,5 +125,5 @@ private: std::unique_ptr impl; }; -} // namespace A64 -} // namespace Dynarmic +} // namespace A64 +} // namespace Dynarmic diff --git a/src/dynarmic/interface/A64/config.h b/src/dynarmic/interface/A64/config.h index 6bc8bd41..5535580b 100644 --- a/src/dynarmic/interface/A64/config.h +++ b/src/dynarmic/interface/A64/config.h @@ -14,7 +14,7 @@ namespace Dynarmic { class ExclusiveMonitor; -} // namespace Dynarmic +} // namespace Dynarmic namespace Dynarmic { namespace A64 { @@ -248,11 +248,11 @@ struct UserConfig { // Minimum size is about 8MiB. Maximum size is about 2GiB. Maximum size is limited by // the maximum length of a x64 jump. - size_t code_cache_size = 256 * 1024 * 1024; // bytes + size_t code_cache_size = 256 * 1024 * 1024; // bytes // Determines the relative size of the near and far code caches. Must be smaller than // code_cache_size. - size_t far_code_offset = 200 * 1024 * 1024; // bytes + size_t far_code_offset = 200 * 1024 * 1024; // bytes }; -} // namespace A64 -} // namespace Dynarmic +} // namespace A64 +} // namespace Dynarmic diff --git a/src/dynarmic/interface/exclusive_monitor.h b/src/dynarmic/interface/exclusive_monitor.h index 9314cccb..70b0c7f8 100644 --- a/src/dynarmic/interface/exclusive_monitor.h +++ b/src/dynarmic/interface/exclusive_monitor.h @@ -5,8 +5,8 @@ #pragma once -#include #include +#include #include #include #include @@ -28,7 +28,7 @@ public: /// Marks a region containing [address, address+size) to be exclusive to /// processor processor_id. - template + template T ReadAndMark(size_t processor_id, VAddr address, Function op) { static_assert(std::is_trivially_copyable_v); const VAddr masked_address = address & RESERVATION_GRANULE_MASK; @@ -45,7 +45,7 @@ public: /// specified region. If it does, executes the operation then clears /// the exclusive state for processors if their exclusive region(s) /// contain [address, address+size). - template + template bool DoExclusiveOperation(size_t processor_id, VAddr address, Function op) { static_assert(std::is_trivially_copyable_v); if (!CheckAndClear(processor_id, address)) { @@ -78,4 +78,4 @@ private: std::vector exclusive_values; }; -} // namespace Dynarmic +} // namespace Dynarmic diff --git a/src/dynarmic/interface/optimization_flags.h b/src/dynarmic/interface/optimization_flags.h index 3a4ca56f..143edc5c 100644 --- a/src/dynarmic/interface/optimization_flags.h +++ b/src/dynarmic/interface/optimization_flags.h @@ -13,35 +13,35 @@ enum class OptimizationFlag : std::uint32_t { /// This optimization avoids dispatcher lookups by allowing emitted basic blocks to jump /// directly to other basic blocks if the destination PC is predictable at JIT-time. /// This is a safe optimization. - BlockLinking = 0x00000001, + BlockLinking = 0x00000001, /// This optimization avoids dispatcher lookups by emulating a return stack buffer. This /// allows for function returns and syscall returns to be predicted at runtime. /// This is a safe optimization. - ReturnStackBuffer = 0x00000002, + ReturnStackBuffer = 0x00000002, /// This optimization enables a two-tiered dispatch system. /// A fast dispatcher (written in assembly) first does a look-up in a small MRU cache. /// If this fails, it falls back to the usual slower dispatcher. /// This is a safe optimization. - FastDispatch = 0x00000004, + FastDispatch = 0x00000004, /// This is an IR optimization. This optimization eliminates unnecessary emulated CPU state /// context lookups. /// This is a safe optimization. - GetSetElimination = 0x00000008, + GetSetElimination = 0x00000008, /// This is an IR optimization. This optimization does constant propagation. /// This is a safe optimization. - ConstProp = 0x00000010, + ConstProp = 0x00000010, /// This is enables miscellaneous safe IR optimizations. - MiscIROpt = 0x00000020, + MiscIROpt = 0x00000020, /// This is an UNSAFE optimization that reduces accuracy of fused multiply-add operations. /// This unfuses fused instructions to improve performance on host CPUs without FMA support. - Unsafe_UnfuseFMA = 0x00010000, + Unsafe_UnfuseFMA = 0x00010000, /// This is an UNSAFE optimization that reduces accuracy of certain floating-point instructions. /// This allows results of FRECPE and FRSQRTE to have **less** error than spec allows. - Unsafe_ReducedErrorFP = 0x00020000, + Unsafe_ReducedErrorFP = 0x00020000, /// This is an UNSAFE optimization that causes floating-point instructions to not produce correct NaNs. /// This may also result in inaccurate results when instructions are given certain special values. - Unsafe_InaccurateNaN = 0x00040000, + Unsafe_InaccurateNaN = 0x00040000, }; constexpr OptimizationFlag no_optimizations = static_cast(0); @@ -71,4 +71,4 @@ constexpr bool operator!(OptimizationFlag f) { return f == no_optimizations; } -} // namespace Dynarmic +} // namespace Dynarmic diff --git a/src/dynarmic/ir/basic_block.cpp b/src/dynarmic/ir/basic_block.cpp index 07d39f2d..0e22cadf 100644 --- a/src/dynarmic/ir/basic_block.cpp +++ b/src/dynarmic/ir/basic_block.cpp @@ -3,6 +3,8 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/ir/basic_block.h" + #include #include #include @@ -15,15 +17,13 @@ #include "dynarmic/common/memory_pool.h" #include "dynarmic/frontend/A32/types.h" #include "dynarmic/frontend/A64/types.h" -#include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/cond.h" #include "dynarmic/ir/opcodes.h" namespace Dynarmic::IR { Block::Block(const LocationDescriptor& location) - : location{location}, end_location{location}, cond{Cond::AL}, - instruction_alloc_pool{std::make_unique(sizeof(Inst), 4096)} {} + : location{location}, end_location{location}, cond{Cond::AL}, instruction_alloc_pool{std::make_unique(sizeof(Inst), 4096)} {} Block::~Block() = default; @@ -36,7 +36,7 @@ void Block::AppendNewInst(Opcode opcode, std::initializer_list args) } Block::iterator Block::PrependNewInst(iterator insertion_point, Opcode opcode, std::initializer_list args) { - IR::Inst* inst = new(instruction_alloc_pool->Alloc()) IR::Inst(opcode); + IR::Inst* inst = new (instruction_alloc_pool->Alloc()) IR::Inst(opcode); ASSERT(args.size() == inst->NumArgs()); std::for_each(args.begin(), args.end(), [&inst, index = size_t(0)](const auto& arg) mutable { @@ -212,7 +212,7 @@ std::string DumpBlock(const IR::Block& block) { if (GetTypeOf(op) != Type::Void) { ret += fmt::format("%{:<5} = ", index); } else { - ret += " "; // '%00000 = ' -> 1 + 5 + 3 = 9 spaces + ret += " "; // '%00000 = ' -> 1 + 5 + 3 = 9 spaces } ret += GetNameOf(op); @@ -242,4 +242,4 @@ std::string DumpBlock(const IR::Block& block) { return ret; } -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR diff --git a/src/dynarmic/ir/basic_block.h b/src/dynarmic/ir/basic_block.h index 73f7324f..4f9a7805 100644 --- a/src/dynarmic/ir/basic_block.h +++ b/src/dynarmic/ir/basic_block.h @@ -34,11 +34,11 @@ enum class Opcode; */ class Block final { public: - using InstructionList = Common::IntrusiveList; - using size_type = InstructionList::size_type; - using iterator = InstructionList::iterator; - using const_iterator = InstructionList::const_iterator; - using reverse_iterator = InstructionList::reverse_iterator; + using InstructionList = Common::IntrusiveList; + using size_type = InstructionList::size_type; + using iterator = InstructionList::iterator; + using const_iterator = InstructionList::const_iterator; + using reverse_iterator = InstructionList::reverse_iterator; using const_reverse_iterator = InstructionList::const_reverse_iterator; explicit Block(const LocationDescriptor& location); @@ -50,30 +50,30 @@ public: Block(Block&&); Block& operator=(Block&&); - bool empty() const { return instructions.empty(); } - size_type size() const { return instructions.size(); } + bool empty() const { return instructions.empty(); } + size_type size() const { return instructions.size(); } - Inst& front() { return instructions.front(); } - const Inst& front() const { return instructions.front(); } + Inst& front() { return instructions.front(); } + const Inst& front() const { return instructions.front(); } - Inst& back() { return instructions.back(); } - const Inst& back() const { return instructions.back(); } + Inst& back() { return instructions.back(); } + const Inst& back() const { return instructions.back(); } - iterator begin() { return instructions.begin(); } - const_iterator begin() const { return instructions.begin(); } - iterator end() { return instructions.end(); } - const_iterator end() const { return instructions.end(); } + iterator begin() { return instructions.begin(); } + const_iterator begin() const { return instructions.begin(); } + iterator end() { return instructions.end(); } + const_iterator end() const { return instructions.end(); } - reverse_iterator rbegin() { return instructions.rbegin(); } - const_reverse_iterator rbegin() const { return instructions.rbegin(); } - reverse_iterator rend() { return instructions.rend(); } - const_reverse_iterator rend() const { return instructions.rend(); } + reverse_iterator rbegin() { return instructions.rbegin(); } + const_reverse_iterator rbegin() const { return instructions.rbegin(); } + reverse_iterator rend() { return instructions.rend(); } + const_reverse_iterator rend() const { return instructions.rend(); } - const_iterator cbegin() const { return instructions.cbegin(); } - const_iterator cend() const { return instructions.cend(); } + const_iterator cbegin() const { return instructions.cbegin(); } + const_iterator cend() const { return instructions.cend(); } const_reverse_iterator crbegin() const { return instructions.crbegin(); } - const_reverse_iterator crend() const { return instructions.crend(); } + const_reverse_iterator crend() const { return instructions.crend(); } /** * Appends a new instruction to the end of this basic block, @@ -164,4 +164,4 @@ private: /// Returns a string representation of the contents of block. Intended for debugging. std::string DumpBlock(const IR::Block& block); -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR diff --git a/src/dynarmic/ir/cond.h b/src/dynarmic/ir/cond.h index c408b10d..5bdd05ed 100644 --- a/src/dynarmic/ir/cond.h +++ b/src/dynarmic/ir/cond.h @@ -8,8 +8,24 @@ namespace Dynarmic::IR { enum class Cond { - EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV, - HS = CS, LO = CC, + EQ, + NE, + CS, + CC, + MI, + PL, + VS, + VC, + HI, + LS, + GE, + LT, + GT, + LE, + AL, + NV, + HS = CS, + LO = CC, }; -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR diff --git a/src/dynarmic/ir/ir_emitter.cpp b/src/dynarmic/ir/ir_emitter.cpp index fcd36ed2..2477067c 100644 --- a/src/dynarmic/ir/ir_emitter.cpp +++ b/src/dynarmic/ir/ir_emitter.cpp @@ -3,8 +3,9 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/assert.h" #include "dynarmic/ir/ir_emitter.h" + +#include "dynarmic/common/assert.h" #include "dynarmic/ir/opcodes.h" namespace Dynarmic::IR { @@ -2655,4 +2656,4 @@ void IREmitter::SetTerm(const Terminal& terminal) { block.SetTerminal(terminal); } -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR diff --git a/src/dynarmic/ir/ir_emitter.h b/src/dynarmic/ir/ir_emitter.h index 6687c18c..7e2ea317 100644 --- a/src/dynarmic/ir/ir_emitter.h +++ b/src/dynarmic/ir/ir_emitter.h @@ -13,7 +13,7 @@ namespace Dynarmic::FP { enum class RoundingMode; -} // namespace Dynarmic::FP +} // namespace Dynarmic::FP // ARM JIT Microinstruction Intermediate Representation // @@ -26,26 +26,26 @@ namespace Dynarmic::IR { enum class Opcode; -template +template struct ResultAndCarry { T result; U1 carry; }; -template +template struct ResultAndOverflow { T result; U1 overflow; }; -template +template struct ResultAndCarryAndOverflow { T result; U1 carry; U1 overflow; }; -template +template struct ResultAndGE { T result; U32 ge; @@ -57,13 +57,27 @@ struct UpperAndLower { }; enum class AccType { - NORMAL, VEC, STREAM, VECSTREAM, - ATOMIC, ORDERED, ORDEREDRW, LIMITEDORDERED, - UNPRIV, IFETCH, PTW, DC, IC, DCZVA, AT, + NORMAL, + VEC, + STREAM, + VECSTREAM, + ATOMIC, + ORDERED, + ORDEREDRW, + LIMITEDORDERED, + UNPRIV, + IFETCH, + PTW, + DC, + IC, + DCZVA, + AT, }; enum class MemOp { - LOAD, STORE, PREFETCH, + LOAD, + STORE, + PREFETCH, }; /** @@ -73,7 +87,8 @@ enum class MemOp { */ class IREmitter { public: - explicit IREmitter(Block& block) : block(block), insertion_point(block.end()) {} + explicit IREmitter(Block& block) + : block(block), insertion_point(block.end()) {} Block& block; @@ -392,11 +407,11 @@ public: protected: IR::Block::iterator insertion_point; - template - T Inst(Opcode op, Args ...args) { + template + T Inst(Opcode op, Args... args) { auto iter = block.PrependNewInst(insertion_point, op, {Value(args)...}); return T(Value(&*iter)); } }; -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR diff --git a/src/dynarmic/ir/location_descriptor.cpp b/src/dynarmic/ir/location_descriptor.cpp index 38f40657..19e67ea2 100644 --- a/src/dynarmic/ir/location_descriptor.cpp +++ b/src/dynarmic/ir/location_descriptor.cpp @@ -3,11 +3,12 @@ * SPDX-License-Identifier: 0BSD */ -#include -#include - #include "dynarmic/ir/location_descriptor.h" +#include + +#include + namespace Dynarmic::IR { std::ostream& operator<<(std::ostream& o, const LocationDescriptor& descriptor) { @@ -15,4 +16,4 @@ std::ostream& operator<<(std::ostream& o, const LocationDescriptor& descriptor) return o; } -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR diff --git a/src/dynarmic/ir/location_descriptor.h b/src/dynarmic/ir/location_descriptor.h index e253d15d..cd47b80b 100644 --- a/src/dynarmic/ir/location_descriptor.h +++ b/src/dynarmic/ir/location_descriptor.h @@ -14,13 +14,14 @@ namespace Dynarmic::IR { class LocationDescriptor { public: - explicit LocationDescriptor(u64 value) : value(value) {} + explicit LocationDescriptor(u64 value) + : value(value) {} - bool operator == (const LocationDescriptor& o) const { + bool operator==(const LocationDescriptor& o) const { return value == o.Value(); } - bool operator != (const LocationDescriptor& o) const { + bool operator!=(const LocationDescriptor& o) const { return !operator==(o); } @@ -36,19 +37,19 @@ inline bool operator<(const LocationDescriptor& x, const LocationDescriptor& y) return x.Value() < y.Value(); } -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR namespace std { -template <> +template<> struct less { bool operator()(const Dynarmic::IR::LocationDescriptor& x, const Dynarmic::IR::LocationDescriptor& y) const noexcept { return x < y; } }; -template <> +template<> struct hash { size_t operator()(const Dynarmic::IR::LocationDescriptor& x) const noexcept { return std::hash()(x.Value()); } }; -} // namespace std +} // namespace std diff --git a/src/dynarmic/ir/microinstruction.cpp b/src/dynarmic/ir/microinstruction.cpp index 439ffa68..48e5be35 100644 --- a/src/dynarmic/ir/microinstruction.cpp +++ b/src/dynarmic/ir/microinstruction.cpp @@ -3,26 +3,27 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/ir/microinstruction.h" + #include #include #include "dynarmic/common/assert.h" -#include "dynarmic/ir/microinstruction.h" #include "dynarmic/ir/opcodes.h" #include "dynarmic/ir/type.h" namespace Dynarmic::IR { bool Inst::IsArithmeticShift() const { - return op == Opcode::ArithmeticShiftRight32 || - op == Opcode::ArithmeticShiftRight64; + return op == Opcode::ArithmeticShiftRight32 + || op == Opcode::ArithmeticShiftRight64; } bool Inst::IsCircularShift() const { - return op == Opcode::RotateRight32 || - op == Opcode::RotateRight64 || - op == Opcode::RotateRightExtended; + return op == Opcode::RotateRight32 + || op == Opcode::RotateRight64 + || op == Opcode::RotateRightExtended; } bool Inst::IsLogicalShift() const { @@ -39,9 +40,9 @@ bool Inst::IsLogicalShift() const { } bool Inst::IsShift() const { - return IsArithmeticShift() || - IsCircularShift() || - IsLogicalShift(); + return IsArithmeticShift() + || IsCircularShift() + || IsLogicalShift(); } bool Inst::IsBarrier() const { @@ -96,7 +97,8 @@ bool Inst::IsSharedMemoryWrite() const { } bool Inst::IsSharedMemoryReadOrWrite() const { - return IsSharedMemoryRead() || IsSharedMemoryWrite(); + return IsSharedMemoryRead() + || IsSharedMemoryWrite(); } bool Inst::IsExclusiveMemoryRead() const { @@ -136,15 +138,18 @@ bool Inst::IsExclusiveMemoryWrite() const { } bool Inst::IsMemoryRead() const { - return IsSharedMemoryRead() || IsExclusiveMemoryRead(); + return IsSharedMemoryRead() + || IsExclusiveMemoryRead(); } bool Inst::IsMemoryWrite() const { - return IsSharedMemoryWrite() || IsExclusiveMemoryWrite(); + return IsSharedMemoryWrite() + || IsExclusiveMemoryWrite(); } bool Inst::IsMemoryReadOrWrite() const { - return IsMemoryRead() || IsMemoryWrite(); + return IsMemoryRead() + || IsMemoryWrite(); } bool Inst::ReadsFromCPSR() const { @@ -264,19 +269,19 @@ bool Inst::WritesToFPCR() const { } bool Inst::ReadsFromFPSR() const { - return op == Opcode::A32GetFpscr || - op == Opcode::A32GetFpscrNZCV || - op == Opcode::A64GetFPSR || - ReadsFromFPSRCumulativeExceptionBits() || - ReadsFromFPSRCumulativeSaturationBit(); + return op == Opcode::A32GetFpscr + || op == Opcode::A32GetFpscrNZCV + || op == Opcode::A64GetFPSR + || ReadsFromFPSRCumulativeExceptionBits() + || ReadsFromFPSRCumulativeSaturationBit(); } bool Inst::WritesToFPSR() const { - return op == Opcode::A32SetFpscr || - op == Opcode::A32SetFpscrNZCV || - op == Opcode::A64SetFPSR || - WritesToFPSRCumulativeExceptionBits() || - WritesToFPSRCumulativeSaturationBit(); + return op == Opcode::A32SetFpscr + || op == Opcode::A32SetFpscrNZCV + || op == Opcode::A64SetFPSR + || WritesToFPSRCumulativeExceptionBits() + || WritesToFPSRCumulativeSaturationBit(); } bool Inst::ReadsFromFPSRCumulativeExceptionBits() const { @@ -484,18 +489,18 @@ bool Inst::WritesToFPSRCumulativeSaturationBit() const { } bool Inst::CausesCPUException() const { - return op == Opcode::Breakpoint || - op == Opcode::A32CallSupervisor || - op == Opcode::A32ExceptionRaised || - op == Opcode::A64CallSupervisor || - op == Opcode::A64ExceptionRaised; + return op == Opcode::Breakpoint + || op == Opcode::A32CallSupervisor + || op == Opcode::A32ExceptionRaised + || op == Opcode::A64CallSupervisor + || op == Opcode::A64ExceptionRaised; } bool Inst::AltersExclusiveState() const { - return op == Opcode::A32ClearExclusive || - op == Opcode::A64ClearExclusive || - IsExclusiveMemoryRead() || - IsExclusiveMemoryWrite(); + return op == Opcode::A32ClearExclusive + || op == Opcode::A64ClearExclusive + || IsExclusiveMemoryRead() + || IsExclusiveMemoryWrite(); } bool Inst::IsCoprocessorInstruction() const { @@ -515,25 +520,25 @@ bool Inst::IsCoprocessorInstruction() const { } bool Inst::IsSetCheckBitOperation() const { - return op == Opcode::A32SetCheckBit || - op == Opcode::A64SetCheckBit; + return op == Opcode::A32SetCheckBit + || op == Opcode::A64SetCheckBit; } bool Inst::MayHaveSideEffects() const { - return op == Opcode::PushRSB || - op == Opcode::A64DataCacheOperationRaised || - op == Opcode::A64InstructionCacheOperationRaised || - IsSetCheckBitOperation() || - IsBarrier() || - CausesCPUException() || - WritesToCoreRegister() || - WritesToSystemRegister() || - WritesToCPSR() || - WritesToFPCR() || - WritesToFPSR() || - AltersExclusiveState() || - IsMemoryWrite() || - IsCoprocessorInstruction(); + return op == Opcode::PushRSB + || op == Opcode::A64DataCacheOperationRaised + || op == Opcode::A64InstructionCacheOperationRaised + || IsSetCheckBitOperation() + || IsBarrier() + || CausesCPUException() + || WritesToCoreRegister() + || WritesToSystemRegister() + || WritesToCPSR() + || WritesToFPCR() + || WritesToFPSR() + || AltersExclusiveState() + || IsMemoryWrite() + || IsCoprocessorInstruction(); } bool Inst::IsAPseudoOperation() const { @@ -573,11 +578,16 @@ bool Inst::MayGetNZCVFromOp() const { } bool Inst::AreAllArgsImmediates() const { - return std::all_of(args.begin(), args.begin() + NumArgs(), [](const auto& value){ return value.IsImmediate(); }); + return std::all_of(args.begin(), args.begin() + NumArgs(), [](const auto& value) { return value.IsImmediate(); }); } bool Inst::HasAssociatedPseudoOperation() const { - return carry_inst || overflow_inst || ge_inst || nzcv_inst || upper_inst || lower_inst; + return carry_inst + || overflow_inst + || ge_inst + || nzcv_inst + || upper_inst + || lower_inst; } Inst* Inst::GetAssociatedPseudoOperation(Opcode opcode) { @@ -668,7 +678,7 @@ void Inst::ReplaceUsesWith(Value replacement) { void Inst::Use(const Value& value) { value.GetInst()->use_count++; - switch (op){ + switch (op) { case Opcode::GetCarryFromOp: ASSERT_MSG(!value.GetInst()->carry_inst, "Only one of each type of pseudo-op allowed"); value.GetInst()->carry_inst = this; @@ -702,7 +712,7 @@ void Inst::Use(const Value& value) { void Inst::UndoUse(const Value& value) { value.GetInst()->use_count--; - switch (op){ + switch (op) { case Opcode::GetCarryFromOp: ASSERT(value.GetInst()->carry_inst->GetOpcode() == Opcode::GetCarryFromOp); value.GetInst()->carry_inst = nullptr; @@ -732,4 +742,4 @@ void Inst::UndoUse(const Value& value) { } } -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR diff --git a/src/dynarmic/ir/microinstruction.h b/src/dynarmic/ir/microinstruction.h index 433e6bdd..de3db2e5 100644 --- a/src/dynarmic/ir/microinstruction.h +++ b/src/dynarmic/ir/microinstruction.h @@ -24,7 +24,8 @@ constexpr size_t max_arg_count = 4; */ class Inst final : public Common::IntrusiveListNode { public: - explicit Inst(Opcode op) : op(op) {} + explicit Inst(Opcode op) + : op(op) {} /// Determines whether or not this instruction performs an arithmetic shift. bool IsArithmeticShift() const; @@ -161,4 +162,4 @@ private: }; }; -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR diff --git a/src/dynarmic/ir/opcodes.cpp b/src/dynarmic/ir/opcodes.cpp index b2f8aaa4..354b8c59 100644 --- a/src/dynarmic/ir/opcodes.cpp +++ b/src/dynarmic/ir/opcodes.cpp @@ -3,6 +3,8 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/ir/opcodes.h" + #include #include #include @@ -11,7 +13,6 @@ #include #include -#include "dynarmic/ir/opcodes.h" #include "dynarmic/ir/type.h" namespace Dynarmic::IR { @@ -43,7 +44,7 @@ constexpr Type NZCV = Type::NZCVFlags; constexpr Type Cond = Type::Cond; constexpr Type Table = Type::Table; -static const std::array opcode_info { +static const std::array opcode_info{ #define OPCODE(name, type, ...) Meta{#name, type, {__VA_ARGS__}}, #define A32OPC(name, type, ...) Meta{#name, type, {__VA_ARGS__}}, #define A64OPC(name, type, ...) Meta{#name, type, {__VA_ARGS__}}, @@ -53,7 +54,7 @@ static const std::array opcode_info { #undef A64OPC }; -} // namespace OpcodeInfo +} // namespace OpcodeInfo Type GetTypeOf(Opcode op) { return OpcodeInfo::opcode_info.at(static_cast(op)).type; @@ -75,4 +76,4 @@ std::ostream& operator<<(std::ostream& o, Opcode opcode) { return o << GetNameOf(opcode); } -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR diff --git a/src/dynarmic/ir/opcodes.h b/src/dynarmic/ir/opcodes.h index f0c3f442..2923511d 100644 --- a/src/dynarmic/ir/opcodes.h +++ b/src/dynarmic/ir/opcodes.h @@ -45,4 +45,4 @@ std::string GetNameOf(Opcode op); std::ostream& operator<<(std::ostream& o, Opcode opcode); -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR diff --git a/src/dynarmic/ir/opt/a32_constant_memory_reads_pass.cpp b/src/dynarmic/ir/opt/a32_constant_memory_reads_pass.cpp index f8bb291e..a3ff8568 100644 --- a/src/dynarmic/ir/opt/a32_constant_memory_reads_pass.cpp +++ b/src/dynarmic/ir/opt/a32_constant_memory_reads_pass.cpp @@ -74,4 +74,4 @@ void A32ConstantMemoryReads(IR::Block& block, A32::UserCallbacks* cb) { } } -} // namespace Dynarmic::Optimization +} // namespace Dynarmic::Optimization diff --git a/src/dynarmic/ir/opt/a32_get_set_elimination_pass.cpp b/src/dynarmic/ir/opt/a32_get_set_elimination_pass.cpp index cb6d8328..03550c82 100644 --- a/src/dynarmic/ir/opt/a32_get_set_elimination_pass.cpp +++ b/src/dynarmic/ir/opt/a32_get_set_elimination_pass.cpp @@ -216,4 +216,4 @@ void A32GetSetElimination(IR::Block& block) { } } -} // namespace Dynarmic::Optimization +} // namespace Dynarmic::Optimization diff --git a/src/dynarmic/ir/opt/a64_callback_config_pass.cpp b/src/dynarmic/ir/opt/a64_callback_config_pass.cpp index 8149be47..e49fdebd 100644 --- a/src/dynarmic/ir/opt/a64_callback_config_pass.cpp +++ b/src/dynarmic/ir/opt/a64_callback_config_pass.cpp @@ -53,4 +53,4 @@ void A64CallbackConfigPass(IR::Block& block, const A64::UserConfig& conf) { } } -} // namespace Dynarmic::Optimization +} // namespace Dynarmic::Optimization diff --git a/src/dynarmic/ir/opt/a64_get_set_elimination_pass.cpp b/src/dynarmic/ir/opt/a64_get_set_elimination_pass.cpp index 7e0ad7c3..a2f14bd7 100644 --- a/src/dynarmic/ir/opt/a64_get_set_elimination_pass.cpp +++ b/src/dynarmic/ir/opt/a64_get_set_elimination_pass.cpp @@ -18,9 +18,14 @@ void A64GetSetElimination(IR::Block& block) { using Iterator = IR::Block::iterator; enum class TrackingType { - W, X, - S, D, Q, - SP, NZCV, NZCVRaw, + W, + X, + S, + D, + Q, + SP, + NZCV, + NZCVRaw, }; struct RegisterInfo { IR::Value register_value; @@ -152,4 +157,4 @@ void A64GetSetElimination(IR::Block& block) { } } -} // namespace Dynarmic::Optimization +} // namespace Dynarmic::Optimization diff --git a/src/dynarmic/ir/opt/a64_merge_interpret_blocks.cpp b/src/dynarmic/ir/opt/a64_merge_interpret_blocks.cpp index a888c00f..ccf15c59 100644 --- a/src/dynarmic/ir/opt/a64_merge_interpret_blocks.cpp +++ b/src/dynarmic/ir/opt/a64_merge_interpret_blocks.cpp @@ -49,4 +49,4 @@ void A64MergeInterpretBlocksPass(IR::Block& block, A64::UserCallbacks* cb) { block.CycleCount() += num_instructions - 1; } -} // namespace Dynarmic::Optimization +} // namespace Dynarmic::Optimization diff --git a/src/dynarmic/ir/opt/constant_propagation_pass.cpp b/src/dynarmic/ir/opt/constant_propagation_pass.cpp index aef06bc5..f4eeba0a 100644 --- a/src/dynarmic/ir/opt/constant_propagation_pass.cpp +++ b/src/dynarmic/ir/opt/constant_propagation_pass.cpp @@ -34,7 +34,7 @@ IR::Value Value(bool is_32_bit, u64 value) { return is_32_bit ? IR::Value{static_cast(value)} : IR::Value{value}; } -template +template bool FoldCommutative(IR::Inst& inst, bool is_32_bit, ImmFn imm_fn) { const auto lhs = inst.GetArg(0); const auto rhs = inst.GetArg(1); @@ -361,7 +361,7 @@ void FoldZeroExtendXToLong(IR::Inst& inst) { const u64 value = inst.GetArg(0).GetImmediateAsU64(); inst.ReplaceUsesWith(IR::Value{value}); } -} // Anonymous namespace +} // Anonymous namespace void ConstantPropagation(IR::Block& block) { for (auto& inst : block) { @@ -538,4 +538,4 @@ void ConstantPropagation(IR::Block& block) { } } -} // namespace Dynarmic::Optimization +} // namespace Dynarmic::Optimization diff --git a/src/dynarmic/ir/opt/dead_code_elimination_pass.cpp b/src/dynarmic/ir/opt/dead_code_elimination_pass.cpp index 9513d297..4f882077 100644 --- a/src/dynarmic/ir/opt/dead_code_elimination_pass.cpp +++ b/src/dynarmic/ir/opt/dead_code_elimination_pass.cpp @@ -19,4 +19,4 @@ void DeadCodeElimination(IR::Block& block) { } } -} // namespace Dynarmic +} // namespace Dynarmic::Optimization diff --git a/src/dynarmic/ir/opt/identity_removal_pass.cpp b/src/dynarmic/ir/opt/identity_removal_pass.cpp index 9cb3c793..2b79b8a7 100644 --- a/src/dynarmic/ir/opt/identity_removal_pass.cpp +++ b/src/dynarmic/ir/opt/identity_removal_pass.cpp @@ -42,4 +42,4 @@ void IdentityRemovalPass(IR::Block& block) { } } -} // namespace Dynarmic +} // namespace Dynarmic::Optimization diff --git a/src/dynarmic/ir/opt/ir_matcher.h b/src/dynarmic/ir/opt/ir_matcher.h index ce1ff300..5eb1a551 100644 --- a/src/dynarmic/ir/opt/ir_matcher.h +++ b/src/dynarmic/ir/opt/ir_matcher.h @@ -56,7 +56,7 @@ struct CaptureSImm { } }; -template +template struct UImm { using ReturnType = std::tuple<>; @@ -67,7 +67,7 @@ struct UImm { } }; -template +template struct SImm { using ReturnType = std::tuple<>; @@ -78,7 +78,7 @@ struct SImm { } }; -template +template struct Inst { public: using ReturnType = mp::concat, typename Args::ReturnType...>; @@ -98,7 +98,7 @@ public: } private: - template + template static auto MatchArgs(const IR::Inst& inst) -> std::optional>, std::tuple<>>>> { if constexpr (I >= sizeof...(Args)) { return std::tuple(); @@ -124,4 +124,4 @@ inline bool IsSameInst(std::tuple t) { return std::get<0>(t) == std::get<1>(t) && std::get<0>(t) == std::get<2>(t); } -} // namespace Dynarmic::Optimization::IRMatcher +} // namespace Dynarmic::Optimization::IRMatcher diff --git a/src/dynarmic/ir/opt/passes.h b/src/dynarmic/ir/opt/passes.h index 3b8fd698..fb19017c 100644 --- a/src/dynarmic/ir/opt/passes.h +++ b/src/dynarmic/ir/opt/passes.h @@ -12,7 +12,7 @@ struct UserCallbacks; namespace Dynarmic::A64 { struct UserCallbacks; struct UserConfig; -} +} // namespace Dynarmic::A64 namespace Dynarmic::IR { class Block; @@ -30,4 +30,4 @@ void DeadCodeElimination(IR::Block& block); void IdentityRemovalPass(IR::Block& block); void VerificationPass(const IR::Block& block); -} // namespace Dynarmic::Optimization +} // namespace Dynarmic::Optimization diff --git a/src/dynarmic/ir/opt/verification_pass.cpp b/src/dynarmic/ir/opt/verification_pass.cpp index 7a1a0390..0a391f11 100644 --- a/src/dynarmic/ir/opt/verification_pass.cpp +++ b/src/dynarmic/ir/opt/verification_pass.cpp @@ -43,4 +43,4 @@ void VerificationPass(const IR::Block& block) { } } -} // namespace Dynarmic::Optimization +} // namespace Dynarmic::Optimization diff --git a/src/dynarmic/ir/terminal.h b/src/dynarmic/ir/terminal.h index ab8a90e1..6a017e35 100644 --- a/src/dynarmic/ir/terminal.h +++ b/src/dynarmic/ir/terminal.h @@ -21,8 +21,9 @@ struct Invalid {}; * The interpreter must interpret exactly `num_instructions` instructions. */ struct Interpret { - explicit Interpret(const LocationDescriptor& next_) : next(next_) {} - LocationDescriptor next; ///< Location at which interpretation starts. + explicit Interpret(const LocationDescriptor& next_) + : next(next_) {} + LocationDescriptor next; ///< Location at which interpretation starts. size_t num_instructions = 1; }; @@ -38,8 +39,9 @@ struct ReturnToDispatch {}; * dispatcher, which will return control to the host. */ struct LinkBlock { - explicit LinkBlock(const LocationDescriptor& next_) : next(next_) {} - LocationDescriptor next; ///< Location descriptor for next block. + explicit LinkBlock(const LocationDescriptor& next_) + : next(next_) {} + LocationDescriptor next; ///< Location descriptor for next block. }; /** @@ -51,8 +53,9 @@ struct LinkBlock { * as LinkBlock. */ struct LinkBlockFast { - explicit LinkBlockFast(const LocationDescriptor& next_) : next(next_) {} - LocationDescriptor next; ///< Location descriptor for next block. + explicit LinkBlockFast(const LocationDescriptor& next_) + : next(next_) {} + LocationDescriptor next; ///< Location descriptor for next block. }; /** @@ -76,24 +79,24 @@ struct CheckBit; struct CheckHalt; /// A Terminal is the terminal instruction in a MicroBlock. using Terminal = boost::variant< - Invalid, - Interpret, - ReturnToDispatch, - LinkBlock, - LinkBlockFast, - PopRSBHint, - FastDispatchHint, - boost::recursive_wrapper, - boost::recursive_wrapper, - boost::recursive_wrapper ->; + Invalid, + Interpret, + ReturnToDispatch, + LinkBlock, + LinkBlockFast, + PopRSBHint, + FastDispatchHint, + boost::recursive_wrapper, + boost::recursive_wrapper, + boost::recursive_wrapper>; /** * This terminal instruction conditionally executes one terminal or another depending * on the run-time state of the ARM flags. */ struct If { - If(Cond if_, Terminal then_, Terminal else_) : if_(if_), then_(std::move(then_)), else_(std::move(else_)) {} + If(Cond if_, Terminal then_, Terminal else_) + : if_(if_), then_(std::move(then_)), else_(std::move(else_)) {} Cond if_; Terminal then_; Terminal else_; @@ -105,7 +108,8 @@ struct If { * then_ is executed if the check bit is non-zero, otherwise else_ is executed. */ struct CheckBit { - CheckBit(Terminal then_, Terminal else_) : then_(std::move(then_)), else_(std::move(else_)) {} + CheckBit(Terminal then_, Terminal else_) + : then_(std::move(then_)), else_(std::move(else_)) {} Terminal then_; Terminal else_; }; @@ -115,12 +119,13 @@ struct CheckBit { * executed. */ struct CheckHalt { - explicit CheckHalt(Terminal else_) : else_(std::move(else_)) {} + explicit CheckHalt(Terminal else_) + : else_(std::move(else_)) {} Terminal else_; }; -} // namespace Term +} // namespace Term using Term::Terminal; -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR diff --git a/src/dynarmic/ir/type.cpp b/src/dynarmic/ir/type.cpp index 9c9ceba2..bf1a35c4 100644 --- a/src/dynarmic/ir/type.cpp +++ b/src/dynarmic/ir/type.cpp @@ -3,12 +3,12 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/ir/type.h" + #include #include #include -#include "dynarmic/ir/type.h" - namespace Dynarmic::IR { std::string GetNameOf(Type type) { @@ -20,8 +20,7 @@ std::string GetNameOf(Type type) { "CoprocInfo", "NZCVFlags", "Cond", - "Table" - }; + "Table"}; const size_t bits = static_cast(type); if (bits == 0) { @@ -48,4 +47,4 @@ std::ostream& operator<<(std::ostream& o, Type type) { return o << GetNameOf(type); } -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR diff --git a/src/dynarmic/ir/type.h b/src/dynarmic/ir/type.h index a7d1c7c6..0c9eda9f 100644 --- a/src/dynarmic/ir/type.h +++ b/src/dynarmic/ir/type.h @@ -50,4 +50,4 @@ bool AreTypesCompatible(Type t1, Type t2); std::ostream& operator<<(std::ostream& o, Type type); -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR diff --git a/src/dynarmic/ir/value.cpp b/src/dynarmic/ir/value.cpp index d809470f..2132b5be 100644 --- a/src/dynarmic/ir/value.cpp +++ b/src/dynarmic/ir/value.cpp @@ -3,60 +3,73 @@ * SPDX-License-Identifier: 0BSD */ +#include "dynarmic/ir/value.h" + #include "dynarmic/common/assert.h" #include "dynarmic/common/bit_util.h" #include "dynarmic/ir/microinstruction.h" #include "dynarmic/ir/opcodes.h" #include "dynarmic/ir/type.h" -#include "dynarmic/ir/value.h" namespace Dynarmic::IR { -Value::Value(Inst* value) : type(Type::Opaque) { +Value::Value(Inst* value) + : type(Type::Opaque) { inner.inst = value; } -Value::Value(A32::Reg value) : type(Type::A32Reg) { +Value::Value(A32::Reg value) + : type(Type::A32Reg) { inner.imm_a32regref = value; } -Value::Value(A32::ExtReg value) : type(Type::A32ExtReg) { +Value::Value(A32::ExtReg value) + : type(Type::A32ExtReg) { inner.imm_a32extregref = value; } -Value::Value(A64::Reg value) : type(Type::A64Reg) { +Value::Value(A64::Reg value) + : type(Type::A64Reg) { inner.imm_a64regref = value; } -Value::Value(A64::Vec value) : type(Type::A64Vec) { +Value::Value(A64::Vec value) + : type(Type::A64Vec) { inner.imm_a64vecref = value; } -Value::Value(bool value) : type(Type::U1) { +Value::Value(bool value) + : type(Type::U1) { inner.imm_u1 = value; } -Value::Value(u8 value) : type(Type::U8) { +Value::Value(u8 value) + : type(Type::U8) { inner.imm_u8 = value; } -Value::Value(u16 value) : type(Type::U16) { +Value::Value(u16 value) + : type(Type::U16) { inner.imm_u16 = value; } -Value::Value(u32 value) : type(Type::U32) { +Value::Value(u32 value) + : type(Type::U32) { inner.imm_u32 = value; } -Value::Value(u64 value) : type(Type::U64) { +Value::Value(u64 value) + : type(Type::U64) { inner.imm_u64 = value; } -Value::Value(CoprocessorInfo value) : type(Type::CoprocInfo) { +Value::Value(CoprocessorInfo value) + : type(Type::CoprocInfo) { inner.imm_coproc = value; } -Value::Value(Cond value) : type(Type::Cond) { +Value::Value(Cond value) + : type(Type::Cond) { inner.imm_cond = value; } @@ -219,4 +232,4 @@ bool Value::IsZero() const { return IsUnsignedImmediate(0); } -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR diff --git a/src/dynarmic/ir/value.h b/src/dynarmic/ir/value.h index b6031749..e907614d 100644 --- a/src/dynarmic/ir/value.h +++ b/src/dynarmic/ir/value.h @@ -5,6 +5,7 @@ #pragma once +#include #include #include "dynarmic/common/assert.h" @@ -14,12 +15,12 @@ namespace Dynarmic::A32 { enum class ExtReg; enum class Reg; -} +} // namespace Dynarmic::A32 namespace Dynarmic::A64 { enum class Reg; enum class Vec; -} +} // namespace Dynarmic::A64 namespace Dynarmic::IR { @@ -34,7 +35,8 @@ class Value { public: using CoprocessorInfo = std::array; - Value() : type(Type::Void) {} + Value() + : type(Type::Void) {} explicit Value(Inst* value); explicit Value(A32::Reg value); explicit Value(A32::ExtReg value); @@ -126,7 +128,7 @@ private: Type type; union { - Inst* inst; // type == Type::Opaque + Inst* inst; // type == Type::Opaque A32::Reg imm_a32regref; A32::ExtReg imm_a32extregref; A64::Reg imm_a64regref; @@ -142,21 +144,24 @@ private: }; static_assert(sizeof(Value) <= 2 * sizeof(u64), "IR::Value should be kept small in size"); -template +template class TypedValue final : public Value { public: TypedValue() = default; - template > - /* implicit */ TypedValue(const TypedValue& value) : Value(value) { + template> + /* implicit */ TypedValue(const TypedValue& value) + : Value(value) { ASSERT((value.GetType() & type_) != Type::Void); } - explicit TypedValue(const Value& value) : Value(value) { + explicit TypedValue(const Value& value) + : Value(value) { ASSERT((value.GetType() & type_) != Type::Void); } - explicit TypedValue(Inst* inst) : TypedValue(Value(inst)) {} + explicit TypedValue(Inst* inst) + : TypedValue(Value(inst)) {} }; using U1 = TypedValue; @@ -172,4 +177,4 @@ using UAnyU128 = TypedValue; using Table = TypedValue; -} // namespace Dynarmic::IR +} // namespace Dynarmic::IR diff --git a/tests/A32/fuzz_arm.cpp b/tests/A32/fuzz_arm.cpp index 19dae24b..c25eb9f8 100644 --- a/tests/A32/fuzz_arm.cpp +++ b/tests/A32/fuzz_arm.cpp @@ -79,8 +79,8 @@ u32 GenRandomArmInst(u32 pc, bool is_last_inst) { static const struct InstructionGeneratorInfo { std::vector generators; std::vector invalid; - } instructions = []{ - const std::vector> list { + } instructions = [] { + const std::vector> list{ #define INST(fn, name, bitstring) {#fn, bitstring}, #include "dynarmic/frontend/A32/decoder/arm.inc" #include "dynarmic/frontend/A32/decoder/asimd.inc" @@ -92,7 +92,7 @@ u32 GenRandomArmInst(u32 pc, bool is_last_inst) { std::vector invalid; // List of instructions not to test - static constexpr std::array do_not_test { + static constexpr std::array do_not_test{ // Translating load/stores "arm_LDRBT", "arm_LDRBT", "arm_LDRHT", "arm_LDRHT", "arm_LDRSBT", "arm_LDRSBT", "arm_LDRSHT", "arm_LDRSHT", "arm_LDRT", "arm_LDRT", "arm_STRBT", "arm_STRBT", "arm_STRHT", "arm_STRHT", "arm_STRT", "arm_STRT", @@ -117,9 +117,9 @@ u32 GenRandomArmInst(u32 pc, bool is_last_inst) { // FPSCR is inaccurate "vfp_VMRS", // Incorrect Unicorn implementations - "asimd_VRECPS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP. - "asimd_VRSQRTS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP. - "vfp_VCVT_from_fixed", // Unicorn does not do round-to-nearest-even for this instruction correctly. + "asimd_VRECPS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP. + "asimd_VRSQRTS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP. + "vfp_VCVT_from_fixed", // Unicorn does not do round-to-nearest-even for this instruction correctly. }; for (const auto& [fn, bitstring] : list) { @@ -150,21 +150,21 @@ std::vector GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s static const struct InstructionGeneratorInfo { std::vector generators; std::vector invalid; - } instructions = []{ - const std::vector> list { + } instructions = [] { + const std::vector> list{ #define INST(fn, name, bitstring) {#fn, bitstring}, #include "dynarmic/frontend/A32/decoder/thumb16.inc" #include "dynarmic/frontend/A32/decoder/thumb32.inc" #undef INST }; - const std::vector> vfp_list { + const std::vector> vfp_list{ #define INST(fn, name, bitstring) {#fn, bitstring}, #include "dynarmic/frontend/A32/decoder/vfp.inc" #undef INST }; - const std::vector> asimd_list { + const std::vector> asimd_list{ #define INST(fn, name, bitstring) {#fn, bitstring}, #include "dynarmic/frontend/A32/decoder/asimd.inc" #undef INST @@ -174,7 +174,7 @@ std::vector GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s std::vector invalid; // List of instructions not to test - static constexpr std::array do_not_test { + static constexpr std::array do_not_test{ "thumb16_BKPT", "thumb16_IT", "thumb16_SETEND", @@ -198,11 +198,17 @@ std::vector GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s // Unicorn has incorrect implementation (incorrect rounding and unsets CPSR.T??) "vfp_VCVT_to_fixed", "vfp_VCVT_from_fixed", - "asimd_VRECPS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP. - "asimd_VRSQRTS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP. + "asimd_VRECPS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP. + "asimd_VRSQRTS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP. // Coprocessor - "thumb32_CDP", "thumb32_LDC", "thumb32_MCR", "thumb32_MCRR", "thumb32_MRC", "thumb32_MRRC", "thumb32_STC", + "thumb32_CDP", + "thumb32_LDC", + "thumb32_MCR", + "thumb32_MCRR", + "thumb32_MRC", + "thumb32_MRRC", + "thumb32_STC", }; for (const auto& [fn, bitstring] : list) { @@ -250,13 +256,13 @@ std::vector GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s if (ShouldTestInst(is_four_bytes ? Common::SwapHalves32(inst) : inst, pc, true, is_last_inst, it_state)) { if (is_four_bytes) - return { static_cast(inst >> 16), static_cast(inst) }; - return { static_cast(inst) }; + return {static_cast(inst >> 16), static_cast(inst)}; + return {static_cast(inst)}; } } } -template +template Dynarmic::A32::UserConfig GetUserConfig(TestEnv& testenv) { Dynarmic::A32::UserConfig user_config; user_config.optimizations &= ~OptimizationFlag::FastDispatch; @@ -265,7 +271,7 @@ Dynarmic::A32::UserConfig GetUserConfig(TestEnv& testenv) { return user_config; } -template +template static void RunTestInstance(Dynarmic::A32::Jit& jit, A32Unicorn& uni, TestEnv& jit_env, @@ -309,7 +315,7 @@ static void RunTestInstance(Dynarmic::A32::Jit& jit, jit_env.ticks_left = ticks_left; jit.Run(); - uni_env.ticks_left = instructions.size(); // Unicorn counts thumb instructions weirdly. + uni_env.ticks_left = instructions.size(); // Unicorn counts thumb instructions weirdly. uni.Run(); SCOPE_FAIL { @@ -394,7 +400,7 @@ static void RunTestInstance(Dynarmic::A32::Jit& jit, REQUIRE(uni_env.modified_memory == jit_env.modified_memory); REQUIRE(uni_env.interrupts.empty()); } -} // Anonymous namespace +} // Anonymous namespace TEST_CASE("A32: Single random arm instruction", "[arm]") { ArmTestEnv jit_env{}; @@ -574,7 +580,7 @@ TEST_CASE("A32: Test thumb IT instruction", "[thumb]") { } // Emit IT instruction - A32::ITState it_state = [&]{ + A32::ITState it_state = [&] { while (true) { const u16 imm8 = RandInt(0, 0xFF); if (Common::Bits<0, 3>(imm8) == 0b0000 || Common::Bits<4, 7>(imm8) == 0b1111 || (Common::Bits<4, 7>(imm8) == 0b1110 && Common::BitCount(Common::Bits<0, 3>(imm8)) != 1)) { diff --git a/tests/A32/fuzz_thumb.cpp b/tests/A32/fuzz_thumb.cpp index e40e175f..85094c79 100644 --- a/tests/A32/fuzz_thumb.cpp +++ b/tests/A32/fuzz_thumb.cpp @@ -41,7 +41,9 @@ using WriteRecords = std::map; struct ThumbInstGen final { public: - ThumbInstGen(std::string_view format, std::function is_valid = [](u32){ return true; }) : is_valid(is_valid) { + ThumbInstGen( + std::string_view format, std::function is_valid = [](u32) { return true; }) + : is_valid(is_valid) { REQUIRE((format.size() == 16 || format.size() == 32)); const auto bit_size = format.size(); @@ -95,18 +97,14 @@ private: std::function is_valid; }; -static bool DoesBehaviorMatch(const A32Unicorn& uni, const A32::Jit& jit, - const WriteRecords& interp_write_records, const WriteRecords& jit_write_records) { +static bool DoesBehaviorMatch(const A32Unicorn& uni, const A32::Jit& jit, const WriteRecords& interp_write_records, const WriteRecords& jit_write_records) { const auto interp_regs = uni.GetRegisters(); const auto jit_regs = jit.Regs(); - return std::equal(interp_regs.begin(), interp_regs.end(), jit_regs.begin(), jit_regs.end()) && - uni.GetCpsr() == jit.Cpsr() && - interp_write_records == jit_write_records; + return std::equal(interp_regs.begin(), interp_regs.end(), jit_regs.begin(), jit_regs.end()) && uni.GetCpsr() == jit.Cpsr() && interp_write_records == jit_write_records; } -static void RunInstance(size_t run_number, ThumbTestEnv& test_env, A32Unicorn& uni, A32::Jit& jit, const ThumbTestEnv::RegisterArray& initial_regs, - size_t instruction_count, size_t instructions_to_execute_count) { +static void RunInstance(size_t run_number, ThumbTestEnv& test_env, A32Unicorn& uni, A32::Jit& jit, const ThumbTestEnv::RegisterArray& initial_regs, size_t instruction_count, size_t instructions_to_execute_count) { uni.ClearPageCache(); jit.ClearCache(); @@ -201,7 +199,7 @@ void FuzzJitThumb16(const size_t instruction_count, const size_t instructions_to // Prepare memory. test_env.code_mem.resize(instruction_count + 1); - test_env.code_mem.back() = 0xE7FE; // b +#0 + test_env.code_mem.back() = 0xE7FE; // b +#0 // Prepare test subjects A32Unicorn uni{test_env}; @@ -209,7 +207,7 @@ void FuzzJitThumb16(const size_t instruction_count, const size_t instructions_to for (size_t run_number = 0; run_number < run_count; run_number++) { ThumbTestEnv::RegisterArray initial_regs; - std::generate_n(initial_regs.begin(), initial_regs.size() - 1, []{ return RandInt(0, 0xFFFFFFFF); }); + std::generate_n(initial_regs.begin(), initial_regs.size() - 1, [] { return RandInt(0, 0xFFFFFFFF); }); initial_regs[15] = 0; std::generate_n(test_env.code_mem.begin(), instruction_count, instruction_generator); @@ -224,7 +222,7 @@ void FuzzJitThumb32(const size_t instruction_count, const size_t instructions_to // Prepare memory. // A Thumb-32 instruction is 32-bits so we multiply our count test_env.code_mem.resize(instruction_count * 2 + 1); - test_env.code_mem.back() = 0xE7FE; // b +#0 + test_env.code_mem.back() = 0xE7FE; // b +#0 // Prepare test subjects A32Unicorn uni{test_env}; @@ -232,7 +230,7 @@ void FuzzJitThumb32(const size_t instruction_count, const size_t instructions_to for (size_t run_number = 0; run_number < run_count; run_number++) { ThumbTestEnv::RegisterArray initial_regs; - std::generate_n(initial_regs.begin(), initial_regs.size() - 1, []{ return RandInt(0, 0xFFFFFFFF); }); + std::generate_n(initial_regs.begin(), initial_regs.size() - 1, [] { return RandInt(0, 0xFFFFFFFF); }); initial_regs[15] = 0; for (size_t i = 0; i < instruction_count; i++) { @@ -250,44 +248,44 @@ void FuzzJitThumb32(const size_t instruction_count, const size_t instructions_to TEST_CASE("Fuzz Thumb instructions set 1", "[JitX64][Thumb][Thumb16]") { const std::array instructions = { - ThumbInstGen("00000xxxxxxxxxxx"), // LSL , , # - ThumbInstGen("00001xxxxxxxxxxx"), // LSR , , # - ThumbInstGen("00010xxxxxxxxxxx"), // ASR , , # - ThumbInstGen("000110oxxxxxxxxx"), // ADD/SUB_reg - ThumbInstGen("000111oxxxxxxxxx"), // ADD/SUB_imm - ThumbInstGen("001ooxxxxxxxxxxx"), // ADD/SUB/CMP/MOV_imm - ThumbInstGen("010000ooooxxxxxx"), // Data Processing - ThumbInstGen("010001000hxxxxxx"), // ADD (high registers) - ThumbInstGen("0100010101xxxxxx", // CMP (high registers) - [](u32 inst){ return Common::Bits<3, 5>(inst) != 0b111; }), // R15 is UNPREDICTABLE - ThumbInstGen("0100010110xxxxxx", // CMP (high registers) - [](u32 inst){ return Common::Bits<0, 2>(inst) != 0b111; }), // R15 is UNPREDICTABLE - ThumbInstGen("010001100hxxxxxx"), // MOV (high registers) - ThumbInstGen("10110000oxxxxxxx"), // Adjust stack pointer - ThumbInstGen("10110010ooxxxxxx"), // SXT/UXT - ThumbInstGen("1011101000xxxxxx"), // REV - ThumbInstGen("1011101001xxxxxx"), // REV16 - ThumbInstGen("1011101011xxxxxx"), // REVSH - ThumbInstGen("01001xxxxxxxxxxx"), // LDR Rd, [PC, #] - ThumbInstGen("0101oooxxxxxxxxx"), // LDR/STR Rd, [Rn, Rm] - ThumbInstGen("011xxxxxxxxxxxxx"), // LDR(B)/STR(B) Rd, [Rn, #] - ThumbInstGen("1000xxxxxxxxxxxx"), // LDRH/STRH Rd, [Rn, #offset] - ThumbInstGen("1001xxxxxxxxxxxx"), // LDR/STR Rd, [SP, #] - ThumbInstGen("1011010xxxxxxxxx", // PUSH - [](u32 inst){ return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE - ThumbInstGen("10111100xxxxxxxx", // POP (P = 0) - [](u32 inst){ return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE - ThumbInstGen("1100xxxxxxxxxxxx", // STMIA/LDMIA + ThumbInstGen("00000xxxxxxxxxxx"), // LSL , , # + ThumbInstGen("00001xxxxxxxxxxx"), // LSR , , # + ThumbInstGen("00010xxxxxxxxxxx"), // ASR , , # + ThumbInstGen("000110oxxxxxxxxx"), // ADD/SUB_reg + ThumbInstGen("000111oxxxxxxxxx"), // ADD/SUB_imm + ThumbInstGen("001ooxxxxxxxxxxx"), // ADD/SUB/CMP/MOV_imm + ThumbInstGen("010000ooooxxxxxx"), // Data Processing + ThumbInstGen("010001000hxxxxxx"), // ADD (high registers) + ThumbInstGen("0100010101xxxxxx", // CMP (high registers) + [](u32 inst) { return Common::Bits<3, 5>(inst) != 0b111; }), // R15 is UNPREDICTABLE + ThumbInstGen("0100010110xxxxxx", // CMP (high registers) + [](u32 inst) { return Common::Bits<0, 2>(inst) != 0b111; }), // R15 is UNPREDICTABLE + ThumbInstGen("010001100hxxxxxx"), // MOV (high registers) + ThumbInstGen("10110000oxxxxxxx"), // Adjust stack pointer + ThumbInstGen("10110010ooxxxxxx"), // SXT/UXT + ThumbInstGen("1011101000xxxxxx"), // REV + ThumbInstGen("1011101001xxxxxx"), // REV16 + ThumbInstGen("1011101011xxxxxx"), // REVSH + ThumbInstGen("01001xxxxxxxxxxx"), // LDR Rd, [PC, #] + ThumbInstGen("0101oooxxxxxxxxx"), // LDR/STR Rd, [Rn, Rm] + ThumbInstGen("011xxxxxxxxxxxxx"), // LDR(B)/STR(B) Rd, [Rn, #] + ThumbInstGen("1000xxxxxxxxxxxx"), // LDRH/STRH Rd, [Rn, #offset] + ThumbInstGen("1001xxxxxxxxxxxx"), // LDR/STR Rd, [SP, #] + ThumbInstGen("1011010xxxxxxxxx", // PUSH + [](u32 inst) { return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE + ThumbInstGen("10111100xxxxxxxx", // POP (P = 0) + [](u32 inst) { return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE + ThumbInstGen("1100xxxxxxxxxxxx", // STMIA/LDMIA [](u32 inst) { // Ensure that the architecturally undefined case of // the base register being within the list isn't hit. const u32 rn = Common::Bits<8, 10>(inst); return (inst & (1U << rn)) == 0 && Common::Bits<0, 7>(inst) != 0; }), - // TODO: We should properly test against swapped - // endianness cases, however Unicorn doesn't - // expose the intended endianness of a load/store - // operation to memory through its hooks. + // TODO: We should properly test against swapped + // endianness cases, however Unicorn doesn't + // expose the intended endianness of a load/store + // operation to memory through its hooks. #if 0 ThumbInstGen("101101100101x000"), // SETEND #endif @@ -318,11 +316,11 @@ TEST_CASE("Fuzz Thumb instructions set 1", "[JitX64][Thumb][Thumb16]") { TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb][Thumb16]") { const std::array instructions = { - // TODO: We currently can't test BX/BLX as we have - // no way of preventing the unpredictable - // condition from occurring with the current interface. - // (bits zero and one within the specified register - // must not be address<1:0> == '10'. + // TODO: We currently can't test BX/BLX as we have + // no way of preventing the unpredictable + // condition from occurring with the current interface. + // (bits zero and one within the specified register + // must not be address<1:0> == '10'. #if 0 ThumbInstGen("01000111xmmmm000", // BLX/BX [](u32 inst){ @@ -330,21 +328,21 @@ TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb][Thumb16 return Rm != 15; }), #endif - ThumbInstGen("1010oxxxxxxxxxxx"), // add to pc/sp - ThumbInstGen("11100xxxxxxxxxxx"), // B - ThumbInstGen("01000100h0xxxxxx"), // ADD (high registers) - ThumbInstGen("01000110h0xxxxxx"), // MOV (high registers) - ThumbInstGen("1101ccccxxxxxxxx", // B - [](u32 inst){ + ThumbInstGen("1010oxxxxxxxxxxx"), // add to pc/sp + ThumbInstGen("11100xxxxxxxxxxx"), // B + ThumbInstGen("01000100h0xxxxxx"), // ADD (high registers) + ThumbInstGen("01000110h0xxxxxx"), // MOV (high registers) + ThumbInstGen("1101ccccxxxxxxxx", // B + [](u32 inst) { const u32 c = Common::Bits<9, 12>(inst); - return c < 0b1110; // Don't want SWI or undefined instructions. + return c < 0b1110; // Don't want SWI or undefined instructions. }), - ThumbInstGen("1011o0i1iiiiinnn"), // CBZ/CBNZ - ThumbInstGen("10110110011x0xxx"), // CPS + ThumbInstGen("1011o0i1iiiiinnn"), // CBZ/CBNZ + ThumbInstGen("10110110011x0xxx"), // CPS - // TODO: We currently have no control over the generated - // values when creating new pages, so we can't - // reliably test this yet. + // TODO: We currently have no control over the generated + // values when creating new pages, so we can't + // reliably test this yet. #if 0 ThumbInstGen("10111101xxxxxxxx"), // POP (R = 1) #endif @@ -368,122 +366,122 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") { }; const std::array instructions = { - ThumbInstGen("111110101011nnnn1111dddd1000mmmm", // CLZ + ThumbInstGen("111110101011nnnn1111dddd1000mmmm", // CLZ [](u32 inst) { const auto d = Common::Bits<8, 11>(inst); const auto m = Common::Bits<0, 3>(inst); const auto n = Common::Bits<16, 19>(inst); return m == n && d != 15 && m != 15; }), - ThumbInstGen("111110101000nnnn1111dddd1000mmmm", // QADD + ThumbInstGen("111110101000nnnn1111dddd1000mmmm", // QADD three_reg_not_r15), - ThumbInstGen("111110101000nnnn1111dddd0001mmmm", // QADD8 + ThumbInstGen("111110101000nnnn1111dddd0001mmmm", // QADD8 three_reg_not_r15), - ThumbInstGen("111110101001nnnn1111dddd0001mmmm", // QADD16 + ThumbInstGen("111110101001nnnn1111dddd0001mmmm", // QADD16 three_reg_not_r15), - ThumbInstGen("111110101010nnnn1111dddd0001mmmm", // QASX + ThumbInstGen("111110101010nnnn1111dddd0001mmmm", // QASX three_reg_not_r15), - ThumbInstGen("111110101000nnnn1111dddd1001mmmm", // QDADD + ThumbInstGen("111110101000nnnn1111dddd1001mmmm", // QDADD three_reg_not_r15), - ThumbInstGen("111110101000nnnn1111dddd1011mmmm", // QDSUB + ThumbInstGen("111110101000nnnn1111dddd1011mmmm", // QDSUB three_reg_not_r15), - ThumbInstGen("111110101110nnnn1111dddd0001mmmm", // QSAX + ThumbInstGen("111110101110nnnn1111dddd0001mmmm", // QSAX three_reg_not_r15), - ThumbInstGen("111110101000nnnn1111dddd1010mmmm", // QSUB + ThumbInstGen("111110101000nnnn1111dddd1010mmmm", // QSUB three_reg_not_r15), - ThumbInstGen("111110101100nnnn1111dddd0001mmmm", // QSUB8 + ThumbInstGen("111110101100nnnn1111dddd0001mmmm", // QSUB8 three_reg_not_r15), - ThumbInstGen("111110101101nnnn1111dddd0001mmmm", // QSUB16 + ThumbInstGen("111110101101nnnn1111dddd0001mmmm", // QSUB16 three_reg_not_r15), - ThumbInstGen("111110101001nnnn1111dddd1010mmmm", // RBIT + ThumbInstGen("111110101001nnnn1111dddd1010mmmm", // RBIT [](u32 inst) { const auto d = Common::Bits<8, 11>(inst); const auto m = Common::Bits<0, 3>(inst); const auto n = Common::Bits<16, 19>(inst); return m == n && d != 15 && m != 15; }), - ThumbInstGen("111110101001nnnn1111dddd1000mmmm", // REV + ThumbInstGen("111110101001nnnn1111dddd1000mmmm", // REV [](u32 inst) { const auto d = Common::Bits<8, 11>(inst); const auto m = Common::Bits<0, 3>(inst); const auto n = Common::Bits<16, 19>(inst); return m == n && d != 15 && m != 15; }), - ThumbInstGen("111110101001nnnn1111dddd1001mmmm", // REV16 + ThumbInstGen("111110101001nnnn1111dddd1001mmmm", // REV16 [](u32 inst) { const auto d = Common::Bits<8, 11>(inst); const auto m = Common::Bits<0, 3>(inst); const auto n = Common::Bits<16, 19>(inst); return m == n && d != 15 && m != 15; }), - ThumbInstGen("111110101001nnnn1111dddd1011mmmm", // REVSH + ThumbInstGen("111110101001nnnn1111dddd1011mmmm", // REVSH [](u32 inst) { const auto d = Common::Bits<8, 11>(inst); const auto m = Common::Bits<0, 3>(inst); const auto n = Common::Bits<16, 19>(inst); return m == n && d != 15 && m != 15; }), - ThumbInstGen("111110101000nnnn1111dddd0000mmmm", // SADD8 + ThumbInstGen("111110101000nnnn1111dddd0000mmmm", // SADD8 three_reg_not_r15), - ThumbInstGen("111110101001nnnn1111dddd0000mmmm", // SADD16 + ThumbInstGen("111110101001nnnn1111dddd0000mmmm", // SADD16 three_reg_not_r15), - ThumbInstGen("111110101010nnnn1111dddd0000mmmm", // SASX + ThumbInstGen("111110101010nnnn1111dddd0000mmmm", // SASX three_reg_not_r15), - ThumbInstGen("111110101010nnnn1111dddd1000mmmm", // SEL + ThumbInstGen("111110101010nnnn1111dddd1000mmmm", // SEL three_reg_not_r15), - ThumbInstGen("111110101000nnnn1111dddd0010mmmm", // SHADD8 + ThumbInstGen("111110101000nnnn1111dddd0010mmmm", // SHADD8 three_reg_not_r15), - ThumbInstGen("111110101001nnnn1111dddd0010mmmm", // SHADD16 + ThumbInstGen("111110101001nnnn1111dddd0010mmmm", // SHADD16 three_reg_not_r15), - ThumbInstGen("111110101010nnnn1111dddd0010mmmm", // SHASX + ThumbInstGen("111110101010nnnn1111dddd0010mmmm", // SHASX three_reg_not_r15), - ThumbInstGen("111110101110nnnn1111dddd0010mmmm", // SHSAX + ThumbInstGen("111110101110nnnn1111dddd0010mmmm", // SHSAX three_reg_not_r15), - ThumbInstGen("111110101100nnnn1111dddd0010mmmm", // SHSUB8 + ThumbInstGen("111110101100nnnn1111dddd0010mmmm", // SHSUB8 three_reg_not_r15), - ThumbInstGen("111110101101nnnn1111dddd0010mmmm", // SHSUB16 + ThumbInstGen("111110101101nnnn1111dddd0010mmmm", // SHSUB16 three_reg_not_r15), - ThumbInstGen("111110101110nnnn1111dddd0000mmmm", // SSAX + ThumbInstGen("111110101110nnnn1111dddd0000mmmm", // SSAX three_reg_not_r15), - ThumbInstGen("111110101100nnnn1111dddd0000mmmm", // SSUB8 + ThumbInstGen("111110101100nnnn1111dddd0000mmmm", // SSUB8 three_reg_not_r15), - ThumbInstGen("111110101101nnnn1111dddd0000mmmm", // SSUB16 + ThumbInstGen("111110101101nnnn1111dddd0000mmmm", // SSUB16 three_reg_not_r15), - ThumbInstGen("111110101000nnnn1111dddd0100mmmm", // UADD8 + ThumbInstGen("111110101000nnnn1111dddd0100mmmm", // UADD8 three_reg_not_r15), - ThumbInstGen("111110101001nnnn1111dddd0100mmmm", // UADD16 + ThumbInstGen("111110101001nnnn1111dddd0100mmmm", // UADD16 three_reg_not_r15), - ThumbInstGen("111110101010nnnn1111dddd0100mmmm", // UASX + ThumbInstGen("111110101010nnnn1111dddd0100mmmm", // UASX three_reg_not_r15), - ThumbInstGen("111110101000nnnn1111dddd0110mmmm", // UHADD8 + ThumbInstGen("111110101000nnnn1111dddd0110mmmm", // UHADD8 three_reg_not_r15), - ThumbInstGen("111110101001nnnn1111dddd0110mmmm", // UHADD16 + ThumbInstGen("111110101001nnnn1111dddd0110mmmm", // UHADD16 three_reg_not_r15), - ThumbInstGen("111110101010nnnn1111dddd0110mmmm", // UHASX + ThumbInstGen("111110101010nnnn1111dddd0110mmmm", // UHASX three_reg_not_r15), - ThumbInstGen("111110101110nnnn1111dddd0110mmmm", // UHSAX + ThumbInstGen("111110101110nnnn1111dddd0110mmmm", // UHSAX three_reg_not_r15), - ThumbInstGen("111110101100nnnn1111dddd0110mmmm", // UHSUB8 + ThumbInstGen("111110101100nnnn1111dddd0110mmmm", // UHSUB8 three_reg_not_r15), - ThumbInstGen("111110101101nnnn1111dddd0110mmmm", // UHSUB16 + ThumbInstGen("111110101101nnnn1111dddd0110mmmm", // UHSUB16 three_reg_not_r15), - ThumbInstGen("111110101000nnnn1111dddd0101mmmm", // UQADD8 + ThumbInstGen("111110101000nnnn1111dddd0101mmmm", // UQADD8 three_reg_not_r15), - ThumbInstGen("111110101001nnnn1111dddd0101mmmm", // UQADD16 + ThumbInstGen("111110101001nnnn1111dddd0101mmmm", // UQADD16 three_reg_not_r15), - ThumbInstGen("111110101010nnnn1111dddd0101mmmm", // UQASX + ThumbInstGen("111110101010nnnn1111dddd0101mmmm", // UQASX three_reg_not_r15), - ThumbInstGen("111110101110nnnn1111dddd0101mmmm", // UQSAX + ThumbInstGen("111110101110nnnn1111dddd0101mmmm", // UQSAX three_reg_not_r15), - ThumbInstGen("111110101100nnnn1111dddd0101mmmm", // UQSUB8 + ThumbInstGen("111110101100nnnn1111dddd0101mmmm", // UQSUB8 three_reg_not_r15), - ThumbInstGen("111110101101nnnn1111dddd0101mmmm", // UQSUB16 + ThumbInstGen("111110101101nnnn1111dddd0101mmmm", // UQSUB16 three_reg_not_r15), - ThumbInstGen("111110101110nnnn1111dddd0100mmmm", // USAX + ThumbInstGen("111110101110nnnn1111dddd0100mmmm", // USAX three_reg_not_r15), - ThumbInstGen("111110101100nnnn1111dddd0100mmmm", // USUB8 + ThumbInstGen("111110101100nnnn1111dddd0100mmmm", // USUB8 three_reg_not_r15), - ThumbInstGen("111110101101nnnn1111dddd0100mmmm", // USUB16 + ThumbInstGen("111110101101nnnn1111dddd0100mmmm", // USUB16 three_reg_not_r15), }; @@ -509,7 +507,7 @@ TEST_CASE("Verify fix for off by one error in MemoryRead32 worked", "[Thumb][Thu A32Unicorn uni{test_env}; A32::Jit jit{GetUserConfig(&test_env)}; - constexpr ThumbTestEnv::RegisterArray initial_regs { + constexpr ThumbTestEnv::RegisterArray initial_regs{ 0xe90ecd70, 0x3e3b73c3, 0x571616f9, @@ -529,12 +527,12 @@ TEST_CASE("Verify fix for off by one error in MemoryRead32 worked", "[Thumb][Thu }; test_env.code_mem = { - 0x40B8, // lsls r0, r7, #0 - 0x01CA, // lsls r2, r1, #7 - 0x83A1, // strh r1, [r4, #28] - 0x708A, // strb r2, [r1, #2] - 0xBCC4, // pop {r2, r6, r7} - 0xE7FE, // b +#0 + 0x40B8, // lsls r0, r7, #0 + 0x01CA, // lsls r2, r1, #7 + 0x83A1, // strh r1, [r4, #28] + 0x708A, // strb r2, [r1, #2] + 0xBCC4, // pop {r2, r6, r7} + 0xE7FE, // b +#0 }; RunInstance(1, test_env, uni, jit, initial_regs, 5, 5); diff --git a/tests/A32/test_arm_instructions.cpp b/tests/A32/test_arm_instructions.cpp index ec8aa1a8..450a6813 100644 --- a/tests/A32/test_arm_instructions.cpp +++ b/tests/A32/test_arm_instructions.cpp @@ -27,15 +27,15 @@ TEST_CASE("arm: Opt Failure: Const folding in MostSignificantWord", "[arm][A32]" ArmTestEnv test_env; A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0xe30ad071, // movw, sp, #41073 - 0xe75efd3d, // smmulr lr, sp, sp - 0xa637af1e, // shadd16ge r10, r7, lr - 0xf57ff01f, // clrex - 0x86b98879, // sxtahhi r8, r9, r9, ror #16 - 0xeafffffe, // b +#0 + 0xe30ad071, // movw, sp, #41073 + 0xe75efd3d, // smmulr lr, sp, sp + 0xa637af1e, // shadd16ge r10, r7, lr + 0xf57ff01f, // clrex + 0x86b98879, // sxtahhi r8, r9, r9, ror #16 + 0xeafffffe, // b +#0 }; - jit.SetCpsr(0x000001d0); // User-mode + jit.SetCpsr(0x000001d0); // User-mode test_env.ticks_left = 6; jit.Run(); @@ -69,19 +69,18 @@ TEST_CASE("arm: Unintended modification in SetCFlag", "[arm][A32]") { ArmTestEnv test_env; A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0xe35f0cd9, // cmp pc, #55552 - 0xe11c0474, // tst r12, r4, ror r4 - 0xe1a006a7, // mov r0, r7, lsr #13 - 0xe35107fa, // cmp r1, #0x3E80000 - 0xe2a54c8a, // adc r4, r5, #35328 - 0xeafffffe, // b +#0 + 0xe35f0cd9, // cmp pc, #55552 + 0xe11c0474, // tst r12, r4, ror r4 + 0xe1a006a7, // mov r0, r7, lsr #13 + 0xe35107fa, // cmp r1, #0x3E80000 + 0xe2a54c8a, // adc r4, r5, #35328 + 0xeafffffe, // b +#0 }; jit.Regs() = { - 0x6973b6bb, 0x267ea626, 0x69debf49, 0x8f976895, 0x4ecd2d0d, 0xcf89b8c7, 0xb6713f85, 0x15e2aa5, - 0xcd14336a, 0xafca0f3e, 0xace2efd9, 0x68fb82cd, 0x775447c0, 0xc9e1f8cd, 0xebe0e626, 0x0 - }; - jit.SetCpsr(0x000001d0); // User-mode + 0x6973b6bb, 0x267ea626, 0x69debf49, 0x8f976895, 0x4ecd2d0d, 0xcf89b8c7, 0xb6713f85, 0x15e2aa5, + 0xcd14336a, 0xafca0f3e, 0xace2efd9, 0x68fb82cd, 0x775447c0, 0xc9e1f8cd, 0xebe0e626, 0x0}; + jit.SetCpsr(0x000001d0); // User-mode test_env.ticks_left = 6; jit.Run(); @@ -105,7 +104,7 @@ TEST_CASE("arm: Unintended modification in SetCFlag", "[arm][A32]") { REQUIRE(jit.Cpsr() == 0x200001d0); } -TEST_CASE( "arm: shsax (Edge-case)", "[arm][A32]" ) { +TEST_CASE("arm: shsax (Edge-case)", "[arm][A32]") { // This was a randomized test-case that was failing. // // The issue here was one of the words to be subtracted was 0x8000. @@ -114,15 +113,14 @@ TEST_CASE( "arm: shsax (Edge-case)", "[arm][A32]" ) { ArmTestEnv test_env; A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0xe63dbf59, // shsax r11, sp, r9 - 0xeafffffe, // b +#0 + 0xe63dbf59, // shsax r11, sp, r9 + 0xeafffffe, // b +#0 }; jit.Regs() = { - 0x3a3b8b18, 0x96156555, 0xffef039f, 0xafb946f2, 0x2030a69a, 0xafe09b2a, 0x896823c8, 0xabde0ded, - 0x9825d6a6, 0x17498000, 0x999d2c95, 0x8b812a59, 0x209bdb58, 0x2f7fb1d4, 0x0f378107, 0x00000000 - }; - jit.SetCpsr(0x000001d0); // User-mode + 0x3a3b8b18, 0x96156555, 0xffef039f, 0xafb946f2, 0x2030a69a, 0xafe09b2a, 0x896823c8, 0xabde0ded, + 0x9825d6a6, 0x17498000, 0x999d2c95, 0x8b812a59, 0x209bdb58, 0x2f7fb1d4, 0x0f378107, 0x00000000}; + jit.SetCpsr(0x000001d0); // User-mode test_env.ticks_left = 2; jit.Run(); @@ -146,7 +144,7 @@ TEST_CASE( "arm: shsax (Edge-case)", "[arm][A32]" ) { REQUIRE(jit.Cpsr() == 0x000001d0); } -TEST_CASE( "arm: uasx (Edge-case)", "[arm][A32]" ) { +TEST_CASE("arm: uasx (Edge-case)", "[arm][A32]") { // UASX's Rm<31:16> == 0x0000. // An implementation that depends on addition overflow to detect // if diff >= 0 will fail this testcase. @@ -154,14 +152,14 @@ TEST_CASE( "arm: uasx (Edge-case)", "[arm][A32]" ) { ArmTestEnv test_env; A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0xe6549f35, // uasx r9, r4, r5 - 0xeafffffe, // b +#0 + 0xe6549f35, // uasx r9, r4, r5 + 0xeafffffe, // b +#0 }; jit.Regs()[4] = 0x8ed38f4c; jit.Regs()[5] = 0x0000261d; jit.Regs()[15] = 0x00000000; - jit.SetCpsr(0x000001d0); // User-mode + jit.SetCpsr(0x000001d0); // User-mode test_env.ticks_left = 2; jit.Run(); @@ -177,20 +175,29 @@ TEST_CASE("arm: smuad (Edge-case)", "[arm][A32]") { ArmTestEnv test_env; A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0xE700F211, // smuad r0, r1, r2 - 0xeafffffe, // b +#0 + 0xE700F211, // smuad r0, r1, r2 + 0xeafffffe, // b +#0 }; jit.Regs() = { - 0, // Rd - 0x80008000, // Rn - 0x80008000, // Rm - 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, + 0, // Rd + 0x80008000, // Rn + 0x80008000, // Rm + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, }; - jit.SetCpsr(0x000001d0); // User-mode + jit.SetCpsr(0x000001d0); // User-mode test_env.ticks_left = 2; jit.Run(); @@ -205,14 +212,14 @@ TEST_CASE("arm: Test InvalidateCacheRange", "[arm][A32]") { ArmTestEnv test_env; A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0xe3a00005, // mov r0, #5 - 0xe3a0100D, // mov r1, #13 - 0xe0812000, // add r2, r1, r0 - 0xeafffffe, // b +#0 (infinite loop) + 0xe3a00005, // mov r0, #5 + 0xe3a0100D, // mov r1, #13 + 0xe0812000, // add r2, r1, r0 + 0xeafffffe, // b +#0 (infinite loop) }; jit.Regs() = {}; - jit.SetCpsr(0x000001d0); // User-mode + jit.SetCpsr(0x000001d0); // User-mode test_env.ticks_left = 4; jit.Run(); @@ -224,7 +231,7 @@ TEST_CASE("arm: Test InvalidateCacheRange", "[arm][A32]") { REQUIRE(jit.Cpsr() == 0x000001d0); // Change the code - test_env.code_mem[1] = 0xe3a01007; // mov r1, #7 + test_env.code_mem[1] = 0xe3a01007; // mov r1, #7 jit.InvalidateCacheRange(/*start_memory_location = */ 4, /* length_in_bytes = */ 4); // Reset position of PC @@ -246,18 +253,18 @@ TEST_CASE("arm: Step blx", "[arm]") { config.optimizations |= OptimizationFlag::FastDispatch; Dynarmic::A32::Jit jit{config}; test_env.code_mem = { - 0xe12fff30, // blx r0 - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xeafffffe, // b +#0 (infinite loop) + 0xe12fff30, // blx r0 + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xeafffffe, // b +#0 (infinite loop) }; jit.Regs()[0] = 8; - jit.Regs()[15] = 0; // PC = 0 - jit.SetCpsr(0x000001d0); // User-mode + jit.Regs()[15] = 0; // PC = 0 + jit.SetCpsr(0x000001d0); // User-mode test_env.ticks_left = 10; jit.Step(); @@ -274,18 +281,18 @@ TEST_CASE("arm: Step bx", "[arm]") { config.optimizations |= OptimizationFlag::FastDispatch; Dynarmic::A32::Jit jit{config}; test_env.code_mem = { - 0xe12fff10, // bx r0 - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xeafffffe, // b +#0 (infinite loop) + 0xe12fff10, // bx r0 + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xeafffffe, // b +#0 (infinite loop) }; jit.Regs()[0] = 8; - jit.Regs()[15] = 0; // PC = 0 - jit.SetCpsr(0x000001d0); // User-mode + jit.Regs()[15] = 0; // PC = 0 + jit.SetCpsr(0x000001d0); // User-mode test_env.ticks_left = 10; jit.Step(); @@ -295,41 +302,40 @@ TEST_CASE("arm: Step bx", "[arm]") { REQUIRE(jit.Cpsr() == 0x000001d0); } - TEST_CASE("arm: Test stepping", "[arm]") { ArmTestEnv test_env; Dynarmic::A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop - 0xeafffffe, // b +#0 (infinite loop) + 0xeafffffe, // b +#0 (infinite loop) }; jit.Regs()[0] = 8; - jit.Regs()[15] = 0; // PC = 0 - jit.SetCpsr(0x000001d0); // User-mode + jit.Regs()[15] = 0; // PC = 0 + jit.SetCpsr(0x000001d0); // User-mode for (size_t i = 0; i < 5; ++i) { test_env.ticks_left = 10; @@ -350,36 +356,36 @@ TEST_CASE("arm: Test stepping 2", "[arm]") { ArmTestEnv test_env; Dynarmic::A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0xe12fff10, // bx r0 - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop + 0xe12fff10, // bx r0 + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop - 0xeafffffe, // b +#0 (infinite loop) + 0xeafffffe, // b +#0 (infinite loop) }; jit.Regs()[0] = 4; - jit.Regs()[15] = 0; // PC = 0 - jit.SetCpsr(0x000001d0); // User-mode + jit.Regs()[15] = 0; // PC = 0 + jit.SetCpsr(0x000001d0); // User-mode for (size_t i = 0; i < 5; ++i) { test_env.ticks_left = 10; @@ -400,18 +406,18 @@ TEST_CASE("arm: Test stepping 3", "[arm]") { ArmTestEnv test_env; Dynarmic::A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0xe12fff10, // bx r0 - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop - 0xe320f000, // nop + 0xe12fff10, // bx r0 + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop + 0xe320f000, // nop - 0xeafffffe, // b +#0 (infinite loop) + 0xeafffffe, // b +#0 (infinite loop) }; jit.Regs()[0] = 4; - jit.Regs()[15] = 0; // PC = 0 - jit.SetCpsr(0x000001d0); // User-mode + jit.Regs()[15] = 0; // PC = 0 + jit.SetCpsr(0x000001d0); // User-mode test_env.ticks_left = 10; jit.Step(); @@ -433,14 +439,28 @@ TEST_CASE("arm: PackedAbsDiffSumS8", "[arm][A32]") { ArmTestEnv test_env; A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0x87414354, // smlsldhi r4, r1, r4, r3 - 0xe7886412, // usad8a r8, r2, r4, r6 - 0xeafffffe, // b +#0 + 0x87414354, // smlsldhi r4, r1, r4, r3 + 0xe7886412, // usad8a r8, r2, r4, r6 + 0xeafffffe, // b +#0 }; jit.Regs() = { - 0xea85297c, 0x417ad918, 0x64f8b70b, 0xcca0373e, 0xbc722361, 0xc528c69e, 0xca926de8, 0xd665d210, - 0xb5650555, 0x4a24b25b, 0xaed44144, 0xe87230b2, 0x98e391de, 0x126efc0c, 0xe591fd11, 0x00000000, + 0xea85297c, + 0x417ad918, + 0x64f8b70b, + 0xcca0373e, + 0xbc722361, + 0xc528c69e, + 0xca926de8, + 0xd665d210, + 0xb5650555, + 0x4a24b25b, + 0xaed44144, + 0xe87230b2, + 0x98e391de, + 0x126efc0c, + 0xe591fd11, + 0x00000000, }; jit.SetCpsr(0xb0000010); @@ -470,14 +490,14 @@ TEST_CASE("arm: vclt.f32 with zero", "[arm][A32]") { ArmTestEnv test_env; A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0xf3b93628, // vclt.f32 d3, d24, #0 - 0xeafffffe, // b +#0 + 0xf3b93628, // vclt.f32 d3, d24, #0 + 0xeafffffe, // b +#0 }; jit.ExtRegs()[48] = 0x3a87d9f1; jit.ExtRegs()[49] = 0x80796dc0; - jit.SetCpsr(0x000001d0); // User-mode + jit.SetCpsr(0x000001d0); // User-mode test_env.ticks_left = 2; jit.Run(); @@ -490,14 +510,14 @@ TEST_CASE("arm: vcvt.s16.f64", "[arm][A32]") { ArmTestEnv test_env; A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0xeebe8b45, // vcvt.s16.f64 d8, d8, #6 - 0xeafffffe, // b +#0 + 0xeebe8b45, // vcvt.s16.f64 d8, d8, #6 + 0xeafffffe, // b +#0 }; jit.ExtRegs()[16] = 0x9a7110b0; jit.ExtRegs()[17] = 0xcd78f4e7; - jit.SetCpsr(0x000001d0); // User-mode + jit.SetCpsr(0x000001d0); // User-mode test_env.ticks_left = 2; jit.Run(); diff --git a/tests/A32/test_thumb_instructions.cpp b/tests/A32/test_thumb_instructions.cpp index a7dbd1f3..48d9e1fc 100644 --- a/tests/A32/test_thumb_instructions.cpp +++ b/tests/A32/test_thumb_instructions.cpp @@ -19,14 +19,14 @@ TEST_CASE("thumb: lsls r0, r1, #2", "[thumb]") { ThumbTestEnv test_env; Dynarmic::A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0x0088, // lsls r0, r1, #2 - 0xE7FE, // b +#0 + 0x0088, // lsls r0, r1, #2 + 0xE7FE, // b +#0 }; jit.Regs()[0] = 1; jit.Regs()[1] = 2; - jit.Regs()[15] = 0; // PC = 0 - jit.SetCpsr(0x00000030); // Thumb, User-mode + jit.Regs()[15] = 0; // PC = 0 + jit.SetCpsr(0x00000030); // Thumb, User-mode test_env.ticks_left = 1; jit.Run(); @@ -41,14 +41,14 @@ TEST_CASE("thumb: lsls r0, r1, #31", "[thumb]") { ThumbTestEnv test_env; Dynarmic::A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0x07C8, // lsls r0, r1, #31 - 0xE7FE, // b +#0 + 0x07C8, // lsls r0, r1, #31 + 0xE7FE, // b +#0 }; jit.Regs()[0] = 1; jit.Regs()[1] = 0xFFFFFFFF; - jit.Regs()[15] = 0; // PC = 0 - jit.SetCpsr(0x00000030); // Thumb, User-mode + jit.Regs()[15] = 0; // PC = 0 + jit.SetCpsr(0x00000030); // Thumb, User-mode test_env.ticks_left = 1; jit.Run(); @@ -56,20 +56,20 @@ TEST_CASE("thumb: lsls r0, r1, #31", "[thumb]") { REQUIRE(jit.Regs()[0] == 0x80000000); REQUIRE(jit.Regs()[1] == 0xffffffff); REQUIRE(jit.Regs()[15] == 2); - REQUIRE(jit.Cpsr() == 0xA0000030); // N, C flags, Thumb, User-mode + REQUIRE(jit.Cpsr() == 0xA0000030); // N, C flags, Thumb, User-mode } TEST_CASE("thumb: revsh r4, r3", "[thumb]") { ThumbTestEnv test_env; Dynarmic::A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0xBADC, // revsh r4, r3 - 0xE7FE, // b +#0 + 0xBADC, // revsh r4, r3 + 0xE7FE, // b +#0 }; jit.Regs()[3] = 0x12345678; - jit.Regs()[15] = 0; // PC = 0 - jit.SetCpsr(0x00000030); // Thumb, User-mode + jit.Regs()[15] = 0; // PC = 0 + jit.SetCpsr(0x00000030); // Thumb, User-mode test_env.ticks_left = 1; jit.Run(); @@ -77,82 +77,82 @@ TEST_CASE("thumb: revsh r4, r3", "[thumb]") { REQUIRE(jit.Regs()[3] == 0x12345678); REQUIRE(jit.Regs()[4] == 0x00007856); REQUIRE(jit.Regs()[15] == 2); - REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode + REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode } TEST_CASE("thumb: ldr r3, [r3, #28]", "[thumb]") { ThumbTestEnv test_env; Dynarmic::A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0x69DB, // ldr r3, [r3, #28] - 0xE7FE, // b +#0 + 0x69DB, // ldr r3, [r3, #28] + 0xE7FE, // b +#0 }; jit.Regs()[3] = 0x12345678; - jit.Regs()[15] = 0; // PC = 0 - jit.SetCpsr(0x00000030); // Thumb, User-mode + jit.Regs()[15] = 0; // PC = 0 + jit.SetCpsr(0x00000030); // Thumb, User-mode test_env.ticks_left = 1; jit.Run(); - REQUIRE(jit.Regs()[3] == 0x97969594); // Memory location 0x12345694 + REQUIRE(jit.Regs()[3] == 0x97969594); // Memory location 0x12345694 REQUIRE(jit.Regs()[15] == 2); - REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode + REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode } TEST_CASE("thumb: blx +#67712", "[thumb]") { ThumbTestEnv test_env; Dynarmic::A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0xF010, 0xEC3E, // blx +#67712 - 0xE7FE // b +#0 + 0xF010, 0xEC3E, // blx +#67712 + 0xE7FE // b +#0 }; - jit.Regs()[15] = 0; // PC = 0 - jit.SetCpsr(0x00000030); // Thumb, User-mode + jit.Regs()[15] = 0; // PC = 0 + jit.SetCpsr(0x00000030); // Thumb, User-mode test_env.ticks_left = 1; jit.Run(); REQUIRE(jit.Regs()[14] == (0x4 | 1)); REQUIRE(jit.Regs()[15] == 0x10880); - REQUIRE(jit.Cpsr() == 0x00000010); // User-mode + REQUIRE(jit.Cpsr() == 0x00000010); // User-mode } TEST_CASE("thumb: bl +#234584", "[thumb]") { ThumbTestEnv test_env; Dynarmic::A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0xF039, 0xFA2A, // bl +#234584 - 0xE7FE // b +#0 + 0xF039, 0xFA2A, // bl +#234584 + 0xE7FE // b +#0 }; - jit.Regs()[15] = 0; // PC = 0 - jit.SetCpsr(0x00000030); // Thumb, User-mode + jit.Regs()[15] = 0; // PC = 0 + jit.SetCpsr(0x00000030); // Thumb, User-mode test_env.ticks_left = 1; jit.Run(); REQUIRE(jit.Regs()[14] == (0x4 | 1)); REQUIRE(jit.Regs()[15] == 0x39458); - REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode + REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode } TEST_CASE("thumb: bl -#42", "[thumb]") { ThumbTestEnv test_env; Dynarmic::A32::Jit jit{GetUserConfig(&test_env)}; test_env.code_mem = { - 0xF7FF, 0xFFE9, // bl -#42 - 0xE7FE // b +#0 + 0xF7FF, 0xFFE9, // bl -#42 + 0xE7FE // b +#0 }; - jit.Regs()[15] = 0; // PC = 0 - jit.SetCpsr(0x00000030); // Thumb, User-mode + jit.Regs()[15] = 0; // PC = 0 + jit.SetCpsr(0x00000030); // Thumb, User-mode test_env.ticks_left = 1; jit.Run(); REQUIRE(jit.Regs()[14] == (0x4 | 1)); REQUIRE(jit.Regs()[15] == 0xFFFFFFD6); - REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode + REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode } diff --git a/tests/A32/testenv.h b/tests/A32/testenv.h index a71cc188..1a1c6520 100644 --- a/tests/A32/testenv.h +++ b/tests/A32/testenv.h @@ -15,7 +15,7 @@ #include "dynarmic/common/common_types.h" #include "dynarmic/interface/A32/a32.h" -template +template class A32TestEnv final : public Dynarmic::A32::UserCallbacks { public: using InstructionType = InstructionType_; @@ -23,12 +23,12 @@ public: using ExtRegsArray = std::array; #ifdef _MSC_VER -#pragma warning(push) -#pragma warning(disable:4309) // C4309: 'static_cast': truncation of constant value +# pragma warning(push) +# pragma warning(disable : 4309) // C4309: 'static_cast': truncation of constant value #endif static constexpr InstructionType infinite_loop = static_cast(infinite_loop_u32); #ifdef _MSC_VER -#pragma warning(pop) +# pragma warning(pop) #endif u64 ticks_left = 0; @@ -53,7 +53,7 @@ public: std::memcpy(&value, &code_mem[vaddr / sizeof(InstructionType)], sizeof(u32)); return value; } - return infinite_loop_u32; // B . + return infinite_loop_u32; // B . } std::uint8_t MemoryRead8(u32 vaddr) override { diff --git a/tests/A64/a64.cpp b/tests/A64/a64.cpp index 25dbc261..e4ebf6a5 100644 --- a/tests/A64/a64.cpp +++ b/tests/A64/a64.cpp @@ -15,8 +15,8 @@ TEST_CASE("A64: ADD", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x8b020020); // ADD X0, X1, X2 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x8b020020); // ADD X0, X1, X2 + env.code_mem.emplace_back(0x14000000); // B . jit.SetRegister(0, 0); jit.SetRegister(1, 1); @@ -36,9 +36,9 @@ TEST_CASE("A64: REV", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0xdac00c00); // REV X0, X0 - env.code_mem.emplace_back(0x5ac00821); // REV W1, W1 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0xdac00c00); // REV X0, X0 + env.code_mem.emplace_back(0x5ac00821); // REV W1, W1 + env.code_mem.emplace_back(0x14000000); // B . jit.SetRegister(0, 0xaabbccddeeff1100); jit.SetRegister(1, 0xaabbccdd); @@ -56,8 +56,8 @@ TEST_CASE("A64: REV32", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0xdac00800); // REV32 X0, X0 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0xdac00800); // REV32 X0, X0 + env.code_mem.emplace_back(0x14000000); // B . jit.SetRegister(0, 0xaabbccddeeff1100); jit.SetPC(0); @@ -72,9 +72,9 @@ TEST_CASE("A64: REV16", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0xdac00400); // REV16 X0, X0 - env.code_mem.emplace_back(0x5ac00421); // REV16 W1, W1 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0xdac00400); // REV16 X0, X0 + env.code_mem.emplace_back(0x5ac00421); // REV16 W1, W1 + env.code_mem.emplace_back(0x14000000); // B . jit.SetRegister(0, 0xaabbccddeeff1100); jit.SetRegister(1, 0xaabbccdd); @@ -92,10 +92,10 @@ TEST_CASE("A64: XTN", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x0e212803); // XTN v3.8b, v0.8h - env.code_mem.emplace_back(0x0e612824); // XTN v4.4h, v1.4s - env.code_mem.emplace_back(0x0ea12845); // XTN v5.2s, v2.2d - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x0e212803); // XTN v3.8b, v0.8h + env.code_mem.emplace_back(0x0e612824); // XTN v4.4h, v1.4s + env.code_mem.emplace_back(0x0ea12845); // XTN v5.2s, v2.2d + env.code_mem.emplace_back(0x14000000); // B . jit.SetPC(0); jit.SetVector(0, {0x3333222211110000, 0x7777666655554444}); @@ -114,8 +114,8 @@ TEST_CASE("A64: AND", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x8a020020); // AND X0, X1, X2 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x8a020020); // AND X0, X1, X2 + env.code_mem.emplace_back(0x14000000); // B . jit.SetRegister(0, 0); jit.SetRegister(1, 1); @@ -135,10 +135,10 @@ TEST_CASE("A64: Bitmasks", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x3200c3e0); // ORR W0, WZR, #0x01010101 - env.code_mem.emplace_back(0x320c8fe1); // ORR W1, WZR, #0x00F000F0 - env.code_mem.emplace_back(0x320003e2); // ORR W2, WZR, #1 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x3200c3e0); // ORR W0, WZR, #0x01010101 + env.code_mem.emplace_back(0x320c8fe1); // ORR W1, WZR, #0x00F000F0 + env.code_mem.emplace_back(0x320003e2); // ORR W2, WZR, #1 + env.code_mem.emplace_back(0x14000000); // B . jit.SetPC(0); @@ -155,8 +155,8 @@ TEST_CASE("A64: ANDS NZCV", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x6a020020); // ANDS W0, W1, W2 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x6a020020); // ANDS W0, W1, W2 + env.code_mem.emplace_back(0x14000000); // B . SECTION("N=1, Z=0") { jit.SetRegister(0, 0); @@ -210,11 +210,11 @@ TEST_CASE("A64: CBZ", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x34000060); // 0x00 : CBZ X0, label - env.code_mem.emplace_back(0x320003e2); // 0x04 : MOV X2, 1 - env.code_mem.emplace_back(0x14000000); // 0x08 : B. - env.code_mem.emplace_back(0x321f03e2); // 0x0C : label: MOV X2, 2 - env.code_mem.emplace_back(0x14000000); // 0x10 : B . + env.code_mem.emplace_back(0x34000060); // 0x00 : CBZ X0, label + env.code_mem.emplace_back(0x320003e2); // 0x04 : MOV X2, 1 + env.code_mem.emplace_back(0x14000000); // 0x08 : B. + env.code_mem.emplace_back(0x321f03e2); // 0x0C : label: MOV X2, 2 + env.code_mem.emplace_back(0x14000000); // 0x10 : B . SECTION("no branch") { jit.SetPC(0); @@ -243,11 +243,11 @@ TEST_CASE("A64: TBZ", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x36180060); // 0x00 : TBZ X0, 3, label - env.code_mem.emplace_back(0x320003e2); // 0x04 : MOV X2, 1 - env.code_mem.emplace_back(0x14000000); // 0x08 : B . - env.code_mem.emplace_back(0x321f03e2); // 0x0C : label: MOV X2, 2 - env.code_mem.emplace_back(0x14000000); // 0x10 : B . + env.code_mem.emplace_back(0x36180060); // 0x00 : TBZ X0, 3, label + env.code_mem.emplace_back(0x320003e2); // 0x04 : MOV X2, 1 + env.code_mem.emplace_back(0x14000000); // 0x08 : B . + env.code_mem.emplace_back(0x321f03e2); // 0x0C : label: MOV X2, 2 + env.code_mem.emplace_back(0x14000000); // 0x10 : B . SECTION("no branch") { jit.SetPC(0); @@ -287,8 +287,8 @@ TEST_CASE("A64: FABD", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x6eb5d556); // FABD.4S V22, V10, V21 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x6eb5d556); // FABD.4S V22, V10, V21 + env.code_mem.emplace_back(0x14000000); // B . jit.SetPC(0); jit.SetVector(10, {0xb4858ac77ff39a87, 0x9fce5e14c4873176}); @@ -314,9 +314,9 @@ TEST_CASE("A64: 128-bit exclusive read/write", "[a64]") { A64::Jit jit{conf}; - env.code_mem.emplace_back(0xc87f0861); // LDXP X1, X2, [X3] - env.code_mem.emplace_back(0xc8241865); // STXP W4, X5, X6, [X3] - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0xc87f0861); // LDXP X1, X2, [X3] + env.code_mem.emplace_back(0xc8241865); // STXP W4, X5, X6, [X3] + env.code_mem.emplace_back(0x14000000); // B . jit.SetPC(0); jit.SetRegister(3, 0x1234567812345678); @@ -338,16 +338,16 @@ TEST_CASE("A64: CNTPCT_EL0", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0xd53be021); // MRS X1, CNTPCT_EL0 - env.code_mem.emplace_back(0xd503201f); // NOP - env.code_mem.emplace_back(0xd503201f); // NOP - env.code_mem.emplace_back(0xd503201f); // NOP - env.code_mem.emplace_back(0xd503201f); // NOP - env.code_mem.emplace_back(0xd503201f); // NOP - env.code_mem.emplace_back(0xd503201f); // NOP - env.code_mem.emplace_back(0xd53be022); // MRS X2, CNTPCT_EL0 - env.code_mem.emplace_back(0xcb010043); // SUB X3, X2, X1 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0xd53be021); // MRS X1, CNTPCT_EL0 + env.code_mem.emplace_back(0xd503201f); // NOP + env.code_mem.emplace_back(0xd503201f); // NOP + env.code_mem.emplace_back(0xd503201f); // NOP + env.code_mem.emplace_back(0xd503201f); // NOP + env.code_mem.emplace_back(0xd503201f); // NOP + env.code_mem.emplace_back(0xd503201f); // NOP + env.code_mem.emplace_back(0xd53be022); // MRS X2, CNTPCT_EL0 + env.code_mem.emplace_back(0xcb010043); // SUB X3, X2, X1 + env.code_mem.emplace_back(0x14000000); // B . env.ticks_left = 10; jit.Run(); @@ -359,8 +359,8 @@ TEST_CASE("A64: FNMSUB 1", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x1f618a9c); // FNMSUB D28, D20, D1, D2 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x1f618a9c); // FNMSUB D28, D20, D1, D2 + env.code_mem.emplace_back(0x14000000); // B . jit.SetPC(0); jit.SetVector(20, {0xe73a51346164bd6c, 0x8080000000002b94}); @@ -377,8 +377,8 @@ TEST_CASE("A64: FNMSUB 2", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x1f2ab88e); // FNMSUB S14, S4, S10, S14 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x1f2ab88e); // FNMSUB S14, S4, S10, S14 + env.code_mem.emplace_back(0x14000000); // B . jit.SetPC(0); jit.SetVector(4, {0x3c9623b101398437, 0x7ff0abcd0ba98d27}); @@ -396,8 +396,8 @@ TEST_CASE("A64: FMADD", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x1f5e0e4a); // FMADD D10, D18, D30, D3 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x1f5e0e4a); // FMADD D10, D18, D30, D3 + env.code_mem.emplace_back(0x14000000); // B . jit.SetPC(0); jit.SetVector(18, {0x8000007600800000, 0x7ff812347f800000}); @@ -415,8 +415,8 @@ TEST_CASE("A64: FMLA.4S (denormal)", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x4e2fcccc); // FMLA.4S V12, V6, V15 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x4e2fcccc); // FMLA.4S V12, V6, V15 + env.code_mem.emplace_back(0x14000000); // B . jit.SetPC(0); jit.SetVector(12, {0x3c9623b17ff80000, 0xbff0000080000076}); @@ -434,8 +434,8 @@ TEST_CASE("A64: FMLA.4S (0x80800000)", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x4e38cc2b); // FMLA.4S V11, V1, V24 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x4e38cc2b); // FMLA.4S V11, V1, V24 + env.code_mem.emplace_back(0x14000000); // B . jit.SetPC(0); jit.SetVector(11, {0xc79b271efff05678, 0xffc0000080800000}); @@ -456,8 +456,8 @@ TEST_CASE("A64: FMADD (0x80800000)", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x1f0f7319); // FMADD S25, S24, S15, S28 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x1f0f7319); // FMADD S25, S24, S15, S28 + env.code_mem.emplace_back(0x14000000); // B . jit.SetPC(0); jit.SetVector(24, {0x00800000, 0}); @@ -475,9 +475,9 @@ TEST_CASE("A64: FNEG failed to zero upper", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x2ea0fb50); // FNEG.2S V16, V26 - env.code_mem.emplace_back(0x2e207a1c); // SQNEG.8B V28, V16 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x2ea0fb50); // FNEG.2S V16, V26 + env.code_mem.emplace_back(0x2e207a1c); // SQNEG.8B V28, V16 + env.code_mem.emplace_back(0x14000000); // B . jit.SetPC(0); jit.SetVector(26, {0x071286fde8f34a90, 0x837cffa8be382f60}); @@ -494,8 +494,8 @@ TEST_CASE("A64: FRSQRTS", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x5eb8fcad); // FRSQRTS S13, S5, S24 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x5eb8fcad); // FRSQRTS S13, S5, S24 + env.code_mem.emplace_back(0x14000000); // B . // These particular values result in an intermediate value during // the calculation that is close to infinity. We want to verify @@ -516,8 +516,8 @@ TEST_CASE("A64: SQDMULH.8H (saturate)", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x4e62b420); // SQDMULH.8H V0, V1, V2 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x4e62b420); // SQDMULH.8H V0, V1, V2 + env.code_mem.emplace_back(0x14000000); // B . // Make sure that saturating values are tested @@ -537,8 +537,8 @@ TEST_CASE("A64: SQDMULH.4S (saturate)", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0x4ea2b420); // SQDMULH.4S V0, V1, V2 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x4ea2b420); // SQDMULH.4S V0, V1, V2 + env.code_mem.emplace_back(0x14000000); // B . // Make sure that saturating values are tested @@ -564,8 +564,8 @@ TEST_CASE("A64: This is an infinite loop if fast dispatch is enabled", "[a64]") env.code_mem.emplace_back(0x2ef41c11); env.code_mem.emplace_back(0x0f07fdd8); env.code_mem.emplace_back(0x9ac90d09); - env.code_mem.emplace_back(0xd63f0120); // BLR X9 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0xd63f0120); // BLR X9 + env.code_mem.emplace_back(0x14000000); // B . env.ticks_left = 6; jit.Run(); @@ -575,12 +575,12 @@ TEST_CASE("A64: Optimization failure when folding ADD", "[a64]") { A64TestEnv env; A64::Jit jit{A64::UserConfig{&env}}; - env.code_mem.emplace_back(0xbc4f84be); // LDR S30, [X5], #248 - env.code_mem.emplace_back(0x9a0c00ea); // ADC X10, X7, X12 - env.code_mem.emplace_back(0x5a1a0079); // SBC W25, W3, W26 - env.code_mem.emplace_back(0x9b0e2be9); // MADD X9, XZR, X14, X10 - env.code_mem.emplace_back(0xfa5fe8a9); // CCMP X5, #31, #9, AL - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0xbc4f84be); // LDR S30, [X5], #248 + env.code_mem.emplace_back(0x9a0c00ea); // ADC X10, X7, X12 + env.code_mem.emplace_back(0x5a1a0079); // SBC W25, W3, W26 + env.code_mem.emplace_back(0x9b0e2be9); // MADD X9, XZR, X14, X10 + env.code_mem.emplace_back(0xfa5fe8a9); // CCMP X5, #31, #9, AL + env.code_mem.emplace_back(0x14000000); // B . jit.SetPC(0); jit.SetRegister(0, 0x46e15845dba57924); @@ -676,9 +676,9 @@ TEST_CASE("A64: Cache Maintenance Instructions", "[a64]") { jit.SetRegister(0, 0xcafed00d); jit.SetRegister(1, 0xcafebabe); - env.code_mem.emplace_back(0xd50b7520); // ic ivau, x0 - env.code_mem.emplace_back(0xd5087621); // dc ivac, x1 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0xd50b7520); // ic ivau, x0 + env.code_mem.emplace_back(0xd5087621); // dc ivac, x1 + env.code_mem.emplace_back(0x14000000); // B . env.ticks_left = 3; jit.Run(); diff --git a/tests/A64/fuzz_with_unicorn.cpp b/tests/A64/fuzz_with_unicorn.cpp index ae01c40c..ec6e6f8c 100644 --- a/tests/A64/fuzz_with_unicorn.cpp +++ b/tests/A64/fuzz_with_unicorn.cpp @@ -59,8 +59,8 @@ static u32 GenRandomInst(u64 pc, bool is_last_inst) { static const struct InstructionGeneratorInfo { std::vector generators; std::vector invalid; - } instructions = []{ - const std::vector> list { + } instructions = [] { + const std::vector> list{ #define INST(fn, name, bitstring) {#fn, bitstring}, #include "dynarmic/frontend/A64/decoder/a64.inc" #undef INST @@ -70,15 +70,24 @@ static u32 GenRandomInst(u64 pc, bool is_last_inst) { std::vector invalid; // List of instructions not to test - const std::vector do_not_test { + const std::vector do_not_test{ // Unimplemented in QEMU "STLLR", // Unimplemented in QEMU "LDLAR", // Dynarmic and QEMU currently differ on how the exclusive monitor's address range works. - "STXR", "STLXR", "STXP", "STLXP", "LDXR", "LDAXR", "LDXP", "LDAXP", + "STXR", + "STLXR", + "STXP", + "STLXP", + "LDXR", + "LDAXR", + "LDXP", + "LDAXP", // Behaviour differs from QEMU - "MSR_reg", "MSR_imm", "MRS", + "MSR_reg", + "MSR_imm", + "MRS", }; for (const auto& [fn, bitstring] : list) { @@ -108,16 +117,15 @@ static u32 GenRandomInst(u64 pc, bool is_last_inst) { } static u32 GenFloatInst(u64 pc, bool is_last_inst) { - static const std::vector instruction_generators = []{ - const std::vector> list { + static const std::vector instruction_generators = [] { + const std::vector> list{ #define INST(fn, name, bitstring) {#fn, #name, bitstring}, #include "dynarmic/frontend/A64/decoder/a64.inc" #undef INST }; // List of instructions not to test - const std::vector do_not_test { - }; + const std::vector do_not_test{}; std::vector result; @@ -154,13 +162,11 @@ static Dynarmic::A64::UserConfig GetUserConfig(A64TestEnv& jit_env) { return jit_user_config; } -static void RunTestInstance(Dynarmic::A64::Jit& jit, A64Unicorn& uni, A64TestEnv& jit_env, A64TestEnv& uni_env, - const A64Unicorn::RegisterArray& regs, const A64Unicorn::VectorArray& vecs, const size_t instructions_start, - const std::vector& instructions, const u32 pstate, const u32 fpcr) { +static void RunTestInstance(Dynarmic::A64::Jit& jit, A64Unicorn& uni, A64TestEnv& jit_env, A64TestEnv& uni_env, const A64Unicorn::RegisterArray& regs, const A64Unicorn::VectorArray& vecs, const size_t instructions_start, const std::vector& instructions, const u32 pstate, const u32 fpcr) { jit_env.code_mem = instructions; uni_env.code_mem = instructions; - jit_env.code_mem.emplace_back(0x14000000); // B . - uni_env.code_mem.emplace_back(0x14000000); // B . + jit_env.code_mem.emplace_back(0x14000000); // B . + uni_env.code_mem.emplace_back(0x14000000); // B . jit_env.code_mem_start_address = instructions_start; uni_env.code_mem_start_address = instructions_start; jit_env.modified_memory.clear(); @@ -302,7 +308,7 @@ TEST_CASE("A64: Single random instruction", "[a64]") { std::vector instructions(1); for (size_t iteration = 0; iteration < 100000; ++iteration) { - std::generate(regs.begin(), regs.end(), []{ return RandInt(0, ~u64(0)); }); + std::generate(regs.begin(), regs.end(), [] { return RandInt(0, ~u64(0)); }); std::generate(vecs.begin(), vecs.end(), RandomVector); instructions[0] = GenRandomInst(0, true); @@ -324,49 +330,49 @@ TEST_CASE("A64: Floating point instructions", "[a64]") { Dynarmic::A64::Jit jit{GetUserConfig(jit_env)}; A64Unicorn uni{uni_env}; - static constexpr std::array float_numbers { - 0x00000000, // positive zero - 0x00000001, // smallest positive denormal - 0x00000076, // - 0x00002b94, // - 0x00636d24, // - 0x007fffff, // largest positive denormal - 0x00800000, // smallest positive normalised real - 0x00800002, // - 0x01398437, // - 0x0ba98d27, // - 0x0ba98d7a, // - 0x751f853a, // - 0x7f7ffff0, // - 0x7f7fffff, // largest positive normalised real - 0x7f800000, // positive infinity - 0x7f800001, // first positive SNaN - 0x7f984a37, // - 0x7fbfffff, // last positive SNaN - 0x7fc00000, // first positive QNaN - 0x7fd9ba98, // - 0x7fffffff, // last positive QNaN - 0x80000000, // negative zero - 0x80000001, // smallest negative denormal - 0x80000076, // - 0x80002b94, // - 0x80636d24, // - 0x807fffff, // largest negative denormal - 0x80800000, // smallest negative normalised real - 0x80800002, // - 0x81398437, // - 0x8ba98d27, // - 0x8ba98d7a, // - 0xf51f853a, // - 0xff7ffff0, // - 0xff7fffff, // largest negative normalised real - 0xff800000, // negative infinity - 0xff800001, // first negative SNaN - 0xff984a37, // - 0xffbfffff, // last negative SNaN - 0xffc00000, // first negative QNaN - 0xffd9ba98, // - 0xffffffff, // last negative QNaN + static constexpr std::array float_numbers{ + 0x00000000, // positive zero + 0x00000001, // smallest positive denormal + 0x00000076, // + 0x00002b94, // + 0x00636d24, // + 0x007fffff, // largest positive denormal + 0x00800000, // smallest positive normalised real + 0x00800002, // + 0x01398437, // + 0x0ba98d27, // + 0x0ba98d7a, // + 0x751f853a, // + 0x7f7ffff0, // + 0x7f7fffff, // largest positive normalised real + 0x7f800000, // positive infinity + 0x7f800001, // first positive SNaN + 0x7f984a37, // + 0x7fbfffff, // last positive SNaN + 0x7fc00000, // first positive QNaN + 0x7fd9ba98, // + 0x7fffffff, // last positive QNaN + 0x80000000, // negative zero + 0x80000001, // smallest negative denormal + 0x80000076, // + 0x80002b94, // + 0x80636d24, // + 0x807fffff, // largest negative denormal + 0x80800000, // smallest negative normalised real + 0x80800002, // + 0x81398437, // + 0x8ba98d27, // + 0x8ba98d7a, // + 0xf51f853a, // + 0xff7ffff0, // + 0xff7fffff, // largest negative normalised real + 0xff800000, // negative infinity + 0xff800001, // first negative SNaN + 0xff984a37, // + 0xffbfffff, // last negative SNaN + 0xffc00000, // first negative QNaN + 0xffd9ba98, // + 0xffffffff, // last negative QNaN // some random numbers follow 0x4f3495cb, 0xe73a5134, @@ -397,26 +403,26 @@ TEST_CASE("A64: Floating point instructions", "[a64]") { 0xc79b271e, 0x460e8c84, // some 64-bit-float upper-halves - 0x7ff00000, // +SNaN / +Inf - 0x7ff0abcd, // +SNaN - 0x7ff80000, // +QNaN - 0x7ff81234, // +QNaN - 0xfff00000, // -SNaN / -Inf - 0xfff05678, // -SNaN - 0xfff80000, // -QNaN - 0xfff809ef, // -QNaN - 0x3ff00000, // Number near +1.0 - 0xbff00000, // Number near -1.0 + 0x7ff00000, // +SNaN / +Inf + 0x7ff0abcd, // +SNaN + 0x7ff80000, // +QNaN + 0x7ff81234, // +QNaN + 0xfff00000, // -SNaN / -Inf + 0xfff05678, // -SNaN + 0xfff80000, // -QNaN + 0xfff809ef, // -QNaN + 0x3ff00000, // Number near +1.0 + 0xbff00000, // Number near -1.0 }; - const auto gen_float = [&]{ + const auto gen_float = [&] { if (RandInt(0, 1) == 0) { return RandInt(0, 0xffffffff); } return float_numbers[RandInt(0, float_numbers.size() - 1)]; }; - const auto gen_vector = [&]{ + const auto gen_vector = [&] { u64 upper = (gen_float() << 32) | gen_float(); u64 lower = (gen_float() << 32) | gen_float(); return Vector{lower, upper}; @@ -477,7 +483,6 @@ TEST_CASE("A64: Small random block", "[a64]") { } } - TEST_CASE("A64: Large random block", "[a64]") { A64TestEnv jit_env{}; A64TestEnv uni_env{}; diff --git a/tests/A64/misaligned_page_table.cpp b/tests/A64/misaligned_page_table.cpp index 21662de5..896f1a46 100644 --- a/tests/A64/misaligned_page_table.cpp +++ b/tests/A64/misaligned_page_table.cpp @@ -16,8 +16,8 @@ TEST_CASE("misaligned load/store do not use page_table when detect_misaligned_ac conf.only_detect_misalignment_via_page_table_on_page_boundary = true; Dynarmic::A64::Jit jit{conf}; - env.code_mem.emplace_back(0x3c800400); // STR Q0, [X0], #0 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x3c800400); // STR Q0, [X0], #0 + env.code_mem.emplace_back(0x14000000); // B . jit.SetPC(0); jit.SetRegister(0, 0x000000000b0afff8); diff --git a/tests/A64/testenv.h b/tests/A64/testenv.h index c7c891fb..88743e10 100644 --- a/tests/A64/testenv.h +++ b/tests/A64/testenv.h @@ -31,7 +31,7 @@ public: std::uint32_t MemoryReadCode(u64 vaddr) override { if (!IsInCodeMem(vaddr)) { - return 0x14000000; // B . + return 0x14000000; // B . } const size_t index = (vaddr - code_mem_start_address) / 4; diff --git a/tests/A64/verify_unicorn.cpp b/tests/A64/verify_unicorn.cpp index f580ae9a..1ac30031 100644 --- a/tests/A64/verify_unicorn.cpp +++ b/tests/A64/verify_unicorn.cpp @@ -16,15 +16,14 @@ using namespace Dynarmic; TEST_CASE("Unicorn: Sanity test", "[a64]") { A64TestEnv env; - env.code_mem.emplace_back(0x8b020020); // ADD X0, X1, X2 - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x8b020020); // ADD X0, X1, X2 + env.code_mem.emplace_back(0x14000000); // B . constexpr A64Unicorn::RegisterArray regs{ 0, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0 - }; + 0, 0, 0, 0, 0, 0, 0}; A64Unicorn unicorn{env}; @@ -43,8 +42,8 @@ TEST_CASE("Unicorn: Sanity test", "[a64]") { TEST_CASE("Unicorn: Ensure 0xFFFF'FFFF'FFFF'FFFF is readable", "[a64]") { A64TestEnv env; - env.code_mem.emplace_back(0x385fed99); // LDRB W25, [X12, #0xfffffffffffffffe]! - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0x385fed99); // LDRB W25, [X12, #0xfffffffffffffffe]! + env.code_mem.emplace_back(0x14000000); // B . A64Unicorn::RegisterArray regs{}; regs[12] = 1; @@ -63,8 +62,8 @@ TEST_CASE("Unicorn: Ensure 0xFFFF'FFFF'FFFF'FFFF is readable", "[a64]") { TEST_CASE("Unicorn: Ensure is able to read across page boundaries", "[a64]") { A64TestEnv env; - env.code_mem.emplace_back(0xb85f93d9); // LDUR W25, [X30, #0xfffffffffffffff9] - env.code_mem.emplace_back(0x14000000); // B . + env.code_mem.emplace_back(0xb85f93d9); // LDUR W25, [X30, #0xfffffffffffffff9] + env.code_mem.emplace_back(0x14000000); // B . A64Unicorn::RegisterArray regs{}; regs[30] = 4; diff --git a/tests/decoder_tests.cpp b/tests/decoder_tests.cpp index f76826ca..e4ea2b46 100644 --- a/tests/decoder_tests.cpp +++ b/tests/decoder_tests.cpp @@ -4,8 +4,8 @@ */ #include -#include #include +#include #include @@ -31,7 +31,7 @@ TEST_CASE("ASIMD Decoder: Ensure table order correctness", "[decode][a32][.]") { return block; }; - const auto is_decode_error = [&get_ir](const A32::ASIMDMatcher& matcher, u32 instruction){ + const auto is_decode_error = [&get_ir](const A32::ASIMDMatcher& matcher, u32 instruction) { const auto block = get_ir(matcher, instruction); for (const auto& ir_inst : block) { diff --git a/tests/fp/FPToFixed.cpp b/tests/fp/FPToFixed.cpp index 0aa7a82f..547e58c6 100644 --- a/tests/fp/FPToFixed.cpp +++ b/tests/fp/FPToFixed.cpp @@ -19,7 +19,7 @@ using namespace Dynarmic; using namespace Dynarmic::FP; TEST_CASE("FPToFixed", "[fp]") { - const std::vector> test_cases { + const std::vector> test_cases{ {0x447A0000, 64, 0x000003E8, 0x00}, {0xC47A0000, 32, 0xFFFFFC18, 0x00}, {0x4479E000, 64, 0x000003E8, 0x10}, diff --git a/tests/fp/mantissa_util_tests.cpp b/tests/fp/mantissa_util_tests.cpp index ee925170..8cec4a19 100644 --- a/tests/fp/mantissa_util_tests.cpp +++ b/tests/fp/mantissa_util_tests.cpp @@ -17,7 +17,7 @@ using namespace Dynarmic; using namespace Dynarmic::FP; TEST_CASE("ResidualErrorOnRightShift", "[fp]") { - const std::vector> test_cases { + const std::vector> test_cases{ {0x00000001, 1, ResidualError::Half}, {0x00000002, 1, ResidualError::Zero}, {0x00000001, 2, ResidualError::LessThanHalf}, @@ -43,7 +43,7 @@ TEST_CASE("ResidualErrorOnRightShift Randomized", "[fp]") { const ResidualError result = ResidualErrorOnRightShift(mantissa, shift); const u64 calculated_error = Safe::ArithmeticShiftRightDouble(mantissa, u64(0), shift); - const ResidualError expected_result = [&]{ + const ResidualError expected_result = [&] { constexpr u64 half_error = 0x8000'0000'0000'0000ull; if (calculated_error == 0) { return ResidualError::Zero; diff --git a/tests/fp/unpacked_tests.cpp b/tests/fp/unpacked_tests.cpp index 8212878c..0998aae3 100644 --- a/tests/fp/unpacked_tests.cpp +++ b/tests/fp/unpacked_tests.cpp @@ -18,7 +18,7 @@ using namespace Dynarmic; using namespace Dynarmic::FP; TEST_CASE("FPUnpack Tests", "[fp]") { - const static std::vector, u32>> test_cases { + const static std::vector, u32>> test_cases{ {0x00000000, {FPType::Zero, false, ToNormalized(false, 0, 0)}, 0}, {0x7F800000, {FPType::Infinity, false, ToNormalized(false, 1000000, 1)}, 0}, {0xFF800000, {FPType::Infinity, true, ToNormalized(true, 1000000, 1)}, 0}, @@ -26,8 +26,8 @@ TEST_CASE("FPUnpack Tests", "[fp]") { {0xFF800001, {FPType::SNaN, true, ToNormalized(true, 0, 0)}, 0}, {0x7FC00001, {FPType::QNaN, false, ToNormalized(false, 0, 0)}, 0}, {0xFFC00001, {FPType::QNaN, true, ToNormalized(true, 0, 0)}, 0}, - {0x00000001, {FPType::Nonzero, false, ToNormalized(false, -149, 1)}, 0}, // Smallest single precision denormal is 2^-149. - {0x3F7FFFFF, {FPType::Nonzero, false, ToNormalized(false, -24, 0xFFFFFF)}, 0}, // 1.0 - epsilon + {0x00000001, {FPType::Nonzero, false, ToNormalized(false, -149, 1)}, 0}, // Smallest single precision denormal is 2^-149. + {0x3F7FFFFF, {FPType::Nonzero, false, ToNormalized(false, -24, 0xFFFFFF)}, 0}, // 1.0 - epsilon }; const FPCR fpcr; @@ -49,12 +49,12 @@ TEST_CASE("FPUnpack Tests", "[fp]") { } TEST_CASE("FPRound Tests", "[fp]") { - const static std::vector, u32>> test_cases { + const static std::vector, u32>> test_cases{ {0x7F800000, {FPType::Infinity, false, ToNormalized(false, 1000000, 1)}, 0x14}, {0xFF800000, {FPType::Infinity, true, ToNormalized(true, 1000000, 1)}, 0x14}, - {0x00000001, {FPType::Nonzero, false, ToNormalized(false, -149, 1)}, 0}, // Smallest single precision denormal is 2^-149. - {0x3F7FFFFF, {FPType::Nonzero, false, ToNormalized(false, -24, 0xFFFFFF)}, 0}, // 1.0 - epsilon - {0x3F800000, {FPType::Nonzero, false, ToNormalized(false, -28, 0xFFFFFFF)}, 0x10}, // rounds to 1.0 + {0x00000001, {FPType::Nonzero, false, ToNormalized(false, -149, 1)}, 0}, // Smallest single precision denormal is 2^-149. + {0x3F7FFFFF, {FPType::Nonzero, false, ToNormalized(false, -24, 0xFFFFFF)}, 0}, // 1.0 - epsilon + {0x3F800000, {FPType::Nonzero, false, ToNormalized(false, -28, 0xFFFFFFF)}, 0x10}, // rounds to 1.0 }; const FPCR fpcr; diff --git a/tests/fuzz_util.cpp b/tests/fuzz_util.cpp index 5a2afaba..1de6c29f 100644 --- a/tests/fuzz_util.cpp +++ b/tests/fuzz_util.cpp @@ -3,12 +3,13 @@ * SPDX-License-Identifier: 0BSD */ +#include "./fuzz_util.h" + #include #include #include -#include "./fuzz_util.h" #include "./rand_int.h" #include "dynarmic/common/assert.h" #include "dynarmic/common/fp/fpcr.h" @@ -34,7 +35,7 @@ u32 RandomFpcr() { return fpcr.Value(); } -InstructionGenerator::InstructionGenerator(const char* format){ +InstructionGenerator::InstructionGenerator(const char* format) { const size_t format_len = std::strlen(format); ASSERT(format_len == 16 || format_len == 32); diff --git a/tests/print_info.cpp b/tests/print_info.cpp index febc18f8..ac108b5e 100644 --- a/tests/print_info.cpp +++ b/tests/print_info.cpp @@ -12,6 +12,9 @@ #include #include +#include +#include + #include "dynarmic/common/bit_util.h" #include "dynarmic/common/common_types.h" #include "dynarmic/common/llvm_disassemble.h" @@ -30,9 +33,6 @@ #include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/opt/passes.h" -#include -#include - using namespace Dynarmic; const char* GetNameOfA32Instruction(u32 instruction) { @@ -97,7 +97,8 @@ void PrintA64Instruction(u32 instruction) { void PrintThumbInstruction(u32 instruction) { const size_t inst_size = (instruction >> 16) == 0 ? 2 : 4; - if (inst_size == 4) instruction = Common::SwapHalves32(instruction); + if (inst_size == 4) + instruction = Common::SwapHalves32(instruction); fmt::print("{:08x} {}\n", instruction, Common::DisassembleAArch32(true, 0, (u8*)&instruction, inst_size)); @@ -187,7 +188,7 @@ void ExecuteA32Instruction(u32 instruction) { u32 cpsr = 0; u32 fpscr = 0; - const std::map name_map = [®s, &ext_regs, &cpsr, &fpscr]{ + const std::map name_map = [®s, &ext_regs, &cpsr, &fpscr] { std::map name_map; for (size_t i = 0; i < regs.size(); i++) { name_map[fmt::format("r{}", i)] = ®s[i]; @@ -203,7 +204,7 @@ void ExecuteA32Instruction(u32 instruction) { return name_map; }(); - const auto get_line = [](){ + const auto get_line = []() { std::string line; std::getline(std::cin, line); std::transform(line.begin(), line.end(), line.begin(), [](unsigned char c) { return static_cast(std::tolower(c)); }); @@ -212,12 +213,15 @@ void ExecuteA32Instruction(u32 instruction) { const auto get_value = [&get_line]() -> std::optional { std::string line = get_line(); - if (line.length() > 2 && line[0] == '0' && line[1] == 'x') line = line.substr(2); - if (line.length() > 8) return std::nullopt; + if (line.length() > 2 && line[0] == '0' && line[1] == 'x') + line = line.substr(2); + if (line.length() > 8) + return std::nullopt; char* endptr; const u32 value = strtol(line.c_str(), &endptr, 16); - if (line.c_str() + line.length() != endptr) return std::nullopt; + if (line.c_str() + line.length() != endptr) + return std::nullopt; return value; }; @@ -253,7 +257,7 @@ void ExecuteA32Instruction(u32 instruction) { const u32 initial_pc = regs[15]; env.MemoryWrite32(initial_pc + 0, instruction); - env.MemoryWrite32(initial_pc + 4, 0xEAFFFFFE); // B +0 + env.MemoryWrite32(initial_pc + 4, 0xEAFFFFFE); // B +0 cpu.Run(); @@ -286,7 +290,7 @@ int main(int argc, char** argv) { return 1; } - const char* const hex_instruction = [argv]{ + const char* const hex_instruction = [argv] { if (strlen(argv[2]) > 2 && argv[2][0] == '0' && argv[2][1] == 'x') { return argv[2] + 2; } diff --git a/tests/rand_int.h b/tests/rand_int.h index ea99e937..9b4dddb8 100644 --- a/tests/rand_int.h +++ b/tests/rand_int.h @@ -8,7 +8,7 @@ #include #include -template +template T RandInt(T min, T max) { static_assert(std::is_integral_v, "T must be an integral type."); static_assert(!std::is_same_v && !std::is_same_v, diff --git a/tests/unicorn_emu/a32_unicorn.cpp b/tests/unicorn_emu/a32_unicorn.cpp index d3061afe..58a8f402 100644 --- a/tests/unicorn_emu/a32_unicorn.cpp +++ b/tests/unicorn_emu/a32_unicorn.cpp @@ -3,26 +3,28 @@ * SPDX-License-Identifier: 0BSD */ +#include "./a32_unicorn.h" + #include #include "../A32/testenv.h" -#include "./a32_unicorn.h" #include "dynarmic/common/assert.h" #include "dynarmic/common/bit_util.h" -#define CHECKED(expr) \ - do { \ - if (auto cerr_ = (expr)) { \ - ASSERT_MSG(false, "Call " #expr " failed with error: {} ({})\n", cerr_, \ - uc_strerror(cerr_)); \ - } \ +#define CHECKED(expr) \ + do { \ + if (auto cerr_ = (expr)) { \ + ASSERT_MSG(false, "Call " #expr " failed with error: {} ({})\n", cerr_, \ + uc_strerror(cerr_)); \ + } \ } while (0) constexpr u32 BEGIN_ADDRESS = 0; constexpr u32 END_ADDRESS = ~u32(0); -template -A32Unicorn::A32Unicorn(TestEnvironment& testenv) : testenv{testenv} { +template +A32Unicorn::A32Unicorn(TestEnvironment& testenv) + : testenv{testenv} { constexpr uc_mode open_mode = std::is_same_v ? UC_MODE_ARM : UC_MODE_THUMB; CHECKED(uc_open(UC_ARCH_ARM, open_mode, &uc)); @@ -31,7 +33,7 @@ A32Unicorn::A32Unicorn(TestEnvironment& testenv) : testenv{test CHECKED(uc_hook_add(uc, &mem_write_prot_hook, UC_HOOK_MEM_WRITE, (void*)MemoryWriteHook, this, BEGIN_ADDRESS, END_ADDRESS)); } -template +template A32Unicorn::~A32Unicorn() { ClearPageCache(); CHECKED(uc_hook_del(uc, intr_hook)); @@ -39,7 +41,7 @@ A32Unicorn::~A32Unicorn() { CHECKED(uc_close(uc)); } -template +template void A32Unicorn::Run() { // Thumb execution mode requires the LSB to be set to 1. constexpr u64 pc_mask = std::is_same_v ? 0 : 1; @@ -62,36 +64,50 @@ void A32Unicorn::Run() { SetPC(new_pc); } -template +template u32 A32Unicorn::GetPC() const { u32 pc; CHECKED(uc_reg_read(uc, UC_ARM_REG_PC, &pc)); return pc; } -template +template void A32Unicorn::SetPC(u32 value) { CHECKED(uc_reg_write(uc, UC_ARM_REG_PC, &value)); } -template +template u32 A32Unicorn::GetSP() const { u32 sp; CHECKED(uc_reg_read(uc, UC_ARM_REG_SP, &sp)); return sp; } -template +template void A32Unicorn::SetSP(u32 value) { CHECKED(uc_reg_write(uc, UC_ARM_REG_SP, &value)); } constexpr std::array gpr_ids{ - UC_ARM_REG_R0, UC_ARM_REG_R1, UC_ARM_REG_R2, UC_ARM_REG_R3, UC_ARM_REG_R4, UC_ARM_REG_R5, UC_ARM_REG_R6, UC_ARM_REG_R7, - UC_ARM_REG_R8, UC_ARM_REG_R9, UC_ARM_REG_R10, UC_ARM_REG_R11, UC_ARM_REG_R12, UC_ARM_REG_R13, UC_ARM_REG_R14, UC_ARM_REG_R15, + UC_ARM_REG_R0, + UC_ARM_REG_R1, + UC_ARM_REG_R2, + UC_ARM_REG_R3, + UC_ARM_REG_R4, + UC_ARM_REG_R5, + UC_ARM_REG_R6, + UC_ARM_REG_R7, + UC_ARM_REG_R8, + UC_ARM_REG_R9, + UC_ARM_REG_R10, + UC_ARM_REG_R11, + UC_ARM_REG_R12, + UC_ARM_REG_R13, + UC_ARM_REG_R14, + UC_ARM_REG_R15, }; -template +template Unicorn::A32::RegisterArray A32Unicorn::GetRegisters() const { Unicorn::A32::RegisterArray regs{}; Unicorn::A32::RegisterPtrArray ptrs; @@ -104,7 +120,7 @@ Unicorn::A32::RegisterArray A32Unicorn::GetRegisters() const { return regs; } -template +template void A32Unicorn::SetRegisters(const RegisterArray& value) { Unicorn::A32::RegisterConstPtrArray ptrs; for (size_t i = 0; i < ptrs.size(); ++i) { @@ -115,22 +131,50 @@ void A32Unicorn::SetRegisters(const RegisterArray& value) { reinterpret_cast(const_cast(ptrs.data())), static_cast(ptrs.size()))); } -using DoubleExtRegPtrArray = std::array; -using DoubleExtRegConstPtrArray = std::array; +using DoubleExtRegPtrArray = std::array; +using DoubleExtRegConstPtrArray = std::array; -constexpr std::array double_ext_reg_ids{ - UC_ARM_REG_D0, UC_ARM_REG_D1, UC_ARM_REG_D2, UC_ARM_REG_D3, UC_ARM_REG_D4, UC_ARM_REG_D5, UC_ARM_REG_D6, UC_ARM_REG_D7, - UC_ARM_REG_D8, UC_ARM_REG_D9, UC_ARM_REG_D10, UC_ARM_REG_D11, UC_ARM_REG_D12, UC_ARM_REG_D13, UC_ARM_REG_D14, UC_ARM_REG_D15, - UC_ARM_REG_D16, UC_ARM_REG_D17, UC_ARM_REG_D18, UC_ARM_REG_D19, UC_ARM_REG_D20, UC_ARM_REG_D21, UC_ARM_REG_D22, UC_ARM_REG_D23, - UC_ARM_REG_D24, UC_ARM_REG_D25, UC_ARM_REG_D26, UC_ARM_REG_D27, UC_ARM_REG_D28, UC_ARM_REG_D29, UC_ARM_REG_D30, UC_ARM_REG_D31, +constexpr std::array double_ext_reg_ids{ + UC_ARM_REG_D0, + UC_ARM_REG_D1, + UC_ARM_REG_D2, + UC_ARM_REG_D3, + UC_ARM_REG_D4, + UC_ARM_REG_D5, + UC_ARM_REG_D6, + UC_ARM_REG_D7, + UC_ARM_REG_D8, + UC_ARM_REG_D9, + UC_ARM_REG_D10, + UC_ARM_REG_D11, + UC_ARM_REG_D12, + UC_ARM_REG_D13, + UC_ARM_REG_D14, + UC_ARM_REG_D15, + UC_ARM_REG_D16, + UC_ARM_REG_D17, + UC_ARM_REG_D18, + UC_ARM_REG_D19, + UC_ARM_REG_D20, + UC_ARM_REG_D21, + UC_ARM_REG_D22, + UC_ARM_REG_D23, + UC_ARM_REG_D24, + UC_ARM_REG_D25, + UC_ARM_REG_D26, + UC_ARM_REG_D27, + UC_ARM_REG_D28, + UC_ARM_REG_D29, + UC_ARM_REG_D30, + UC_ARM_REG_D31, }; -template +template Unicorn::A32::ExtRegArray A32Unicorn::GetExtRegs() const { Unicorn::A32::ExtRegArray ext_regs{}; DoubleExtRegPtrArray ptrs; for (size_t i = 0; i < ptrs.size(); ++i) - ptrs[i] = &ext_regs[i*2]; + ptrs[i] = &ext_regs[i * 2]; CHECKED(uc_reg_read_batch(uc, const_cast(double_ext_reg_ids.data()), reinterpret_cast(ptrs.data()), static_cast(ptrs.size()))); @@ -138,60 +182,60 @@ Unicorn::A32::ExtRegArray A32Unicorn::GetExtRegs() const { return ext_regs; } -template +template void A32Unicorn::SetExtRegs(const ExtRegArray& value) { DoubleExtRegConstPtrArray ptrs; for (size_t i = 0; i < ptrs.size(); ++i) { - ptrs[i] = &value[i*2]; + ptrs[i] = &value[i * 2]; } CHECKED(uc_reg_write_batch(uc, const_cast(double_ext_reg_ids.data()), - reinterpret_cast(const_cast(ptrs.data())), static_cast(ptrs.size()))); + reinterpret_cast(const_cast(ptrs.data())), static_cast(ptrs.size()))); } -template +template u32 A32Unicorn::GetFpscr() const { u32 fpsr; CHECKED(uc_reg_read(uc, UC_ARM_REG_FPSCR, &fpsr)); return fpsr; } -template +template void A32Unicorn::SetFpscr(u32 value) { CHECKED(uc_reg_write(uc, UC_ARM_REG_FPSCR, &value)); } -template +template u32 A32Unicorn::GetFpexc() const { u32 value = 0; CHECKED(uc_reg_read(uc, UC_ARM_REG_FPEXC, &value)); return value; } -template +template void A32Unicorn::SetFpexc(u32 value) { CHECKED(uc_reg_write(uc, UC_ARM_REG_FPEXC, &value)); } -template +template u32 A32Unicorn::GetCpsr() const { u32 pstate; CHECKED(uc_reg_read(uc, UC_ARM_REG_CPSR, &pstate)); return pstate; } -template +template void A32Unicorn::SetCpsr(u32 value) { CHECKED(uc_reg_write(uc, UC_ARM_REG_CPSR, &value)); } -template +template void A32Unicorn::EnableFloatingPointAccess() { const u32 new_fpexc = GetFpexc() | (1U << 30); SetFpexc(new_fpexc); } -template +template void A32Unicorn::ClearPageCache() { for (const auto& page : pages) { CHECKED(uc_mem_unmap(uc, page->address, 4096)); @@ -199,7 +243,7 @@ void A32Unicorn::ClearPageCache() { pages.clear(); } -template +template void A32Unicorn::DumpMemoryInformation() { uc_mem_region* regions; u32 count; @@ -212,7 +256,7 @@ void A32Unicorn::DumpMemoryInformation() { CHECKED(uc_free(regions)); } -template +template void A32Unicorn::InterruptHook(uc_engine* /*uc*/, u32 int_number, void* user_data) { auto* this_ = static_cast(user_data); @@ -223,7 +267,7 @@ void A32Unicorn::InterruptHook(uc_engine* /*uc*/, u32 int_numbe auto iss = esr & 0xFFFFFF; switch (ec) { - case 0x15: // SVC + case 0x15: // SVC this_->testenv.CallSVC(iss); break; default: @@ -232,7 +276,7 @@ void A32Unicorn::InterruptHook(uc_engine* /*uc*/, u32 int_numbe } } -template +template bool A32Unicorn::UnmappedMemoryHook(uc_engine* uc, uc_mem_type /*type*/, u32 start_address, int size, u64 /*value*/, void* user_data) { auto* this_ = static_cast(user_data); @@ -253,7 +297,7 @@ bool A32Unicorn::UnmappedMemoryHook(uc_engine* uc, uc_mem_type uc_err err = uc_mem_map_ptr(uc, base_address, page->data.size(), permissions, page->data.data()); if (err == UC_ERR_MAP) - return; // page already exists + return; // page already exists CHECKED(err); this_->pages.emplace_back(std::move(page)); @@ -261,8 +305,8 @@ bool A32Unicorn::UnmappedMemoryHook(uc_engine* uc, uc_mem_type const auto is_in_range = [](u32 addr, u32 start, u32 end) { if (start <= end) - return addr >= start && addr <= end; // fffff[tttttt]fffff - return addr >= start || addr <= end; // ttttt]ffffff[ttttt + return addr >= start && addr <= end; // fffff[tttttt]fffff + return addr >= start || addr <= end; // ttttt]ffffff[ttttt }; const u32 start_address_page = start_address & ~u32(0xFFF); @@ -277,7 +321,7 @@ bool A32Unicorn::UnmappedMemoryHook(uc_engine* uc, uc_mem_type return true; } -template +template bool A32Unicorn::MemoryWriteHook(uc_engine* /*uc*/, uc_mem_type /*type*/, u32 start_address, int size, u64 value, void* user_data) { auto* this_ = static_cast(user_data); diff --git a/tests/unicorn_emu/a32_unicorn.h b/tests/unicorn_emu/a32_unicorn.h index 2b97ddd5..1cf06a02 100644 --- a/tests/unicorn_emu/a32_unicorn.h +++ b/tests/unicorn_emu/a32_unicorn.h @@ -9,11 +9,11 @@ #include #ifdef _MSC_VER -#pragma warning(push, 0) -#include -#pragma warning(pop) +# pragma warning(push, 0) +# include +# pragma warning(pop) #else -#include +# include #endif #include "../A32/testenv.h" @@ -27,9 +27,9 @@ using ExtRegArray = std::array; using RegisterArray = std::array; using RegisterPtrArray = std::array; using RegisterConstPtrArray = std::array; -} // namespace Unicorn::A32 +} // namespace Unicorn::A32 -template +template class A32Unicorn final { public: using ExtRegArray = Unicorn::A32::ExtRegArray; diff --git a/tests/unicorn_emu/a64_unicorn.cpp b/tests/unicorn_emu/a64_unicorn.cpp index e4b97615..583e04d9 100644 --- a/tests/unicorn_emu/a64_unicorn.cpp +++ b/tests/unicorn_emu/a64_unicorn.cpp @@ -4,20 +4,22 @@ */ #include "./a64_unicorn.h" + #include "dynarmic/common/assert.h" -#define CHECKED(expr) \ - do { \ - if (auto cerr_ = (expr)) { \ - ASSERT_MSG(false, "Call " #expr " failed with error: {} ({})\n", cerr_, \ - uc_strerror(cerr_)); \ - } \ +#define CHECKED(expr) \ + do { \ + if (auto cerr_ = (expr)) { \ + ASSERT_MSG(false, "Call " #expr " failed with error: {} ({})\n", cerr_, \ + uc_strerror(cerr_)); \ + } \ } while (0) constexpr u64 BEGIN_ADDRESS = 0; constexpr u64 END_ADDRESS = ~u64(0); -A64Unicorn::A64Unicorn(A64TestEnv& testenv) : testenv(testenv) { +A64Unicorn::A64Unicorn(A64TestEnv& testenv) + : testenv(testenv) { CHECKED(uc_open(UC_ARCH_ARM64, UC_MODE_ARM, &uc)); u64 fpv = 3 << 20; CHECKED(uc_reg_write(uc, UC_ARM64_REG_CPACR_EL1, &fpv)); @@ -66,8 +68,7 @@ constexpr std::array gpr_ids{ UC_ARM64_REG_X0, UC_ARM64_REG_X1, UC_ARM64_REG_X2, UC_ARM64_REG_X3, UC_ARM64_REG_X4, UC_ARM64_REG_X5, UC_ARM64_REG_X6, UC_ARM64_REG_X7, UC_ARM64_REG_X8, UC_ARM64_REG_X9, UC_ARM64_REG_X10, UC_ARM64_REG_X11, UC_ARM64_REG_X12, UC_ARM64_REG_X13, UC_ARM64_REG_X14, UC_ARM64_REG_X15, UC_ARM64_REG_X16, UC_ARM64_REG_X17, UC_ARM64_REG_X18, UC_ARM64_REG_X19, UC_ARM64_REG_X20, UC_ARM64_REG_X21, UC_ARM64_REG_X22, UC_ARM64_REG_X23, - UC_ARM64_REG_X24, UC_ARM64_REG_X25, UC_ARM64_REG_X26, UC_ARM64_REG_X27, UC_ARM64_REG_X28, UC_ARM64_REG_X29, UC_ARM64_REG_X30 -}; + UC_ARM64_REG_X24, UC_ARM64_REG_X25, UC_ARM64_REG_X26, UC_ARM64_REG_X27, UC_ARM64_REG_X28, UC_ARM64_REG_X29, UC_ARM64_REG_X30}; A64Unicorn::RegisterArray A64Unicorn::GetRegisters() const { RegisterArray regs{}; @@ -93,8 +94,7 @@ constexpr std::array vec_ids{ UC_ARM64_REG_Q0, UC_ARM64_REG_Q1, UC_ARM64_REG_Q2, UC_ARM64_REG_Q3, UC_ARM64_REG_Q4, UC_ARM64_REG_Q5, UC_ARM64_REG_Q6, UC_ARM64_REG_Q7, UC_ARM64_REG_Q8, UC_ARM64_REG_Q9, UC_ARM64_REG_Q10, UC_ARM64_REG_Q11, UC_ARM64_REG_Q12, UC_ARM64_REG_Q13, UC_ARM64_REG_Q14, UC_ARM64_REG_Q15, UC_ARM64_REG_Q16, UC_ARM64_REG_Q17, UC_ARM64_REG_Q18, UC_ARM64_REG_Q19, UC_ARM64_REG_Q20, UC_ARM64_REG_Q21, UC_ARM64_REG_Q22, UC_ARM64_REG_Q23, - UC_ARM64_REG_Q24, UC_ARM64_REG_Q25, UC_ARM64_REG_Q26, UC_ARM64_REG_Q27, UC_ARM64_REG_Q28, UC_ARM64_REG_Q29, UC_ARM64_REG_Q30, UC_ARM64_REG_Q31 -}; + UC_ARM64_REG_Q24, UC_ARM64_REG_Q25, UC_ARM64_REG_Q26, UC_ARM64_REG_Q27, UC_ARM64_REG_Q28, UC_ARM64_REG_Q29, UC_ARM64_REG_Q30, UC_ARM64_REG_Q31}; A64Unicorn::VectorArray A64Unicorn::GetVectors() const { VectorArray vecs{}; @@ -114,7 +114,7 @@ void A64Unicorn::SetVectors(const VectorArray& value) { ptrs[i] = &value[i]; CHECKED(uc_reg_write_batch(uc, const_cast(vec_ids.data()), - reinterpret_cast(const_cast(ptrs.data())), static_cast(num_vecs))); + reinterpret_cast(const_cast(ptrs.data())), static_cast(num_vecs))); } u32 A64Unicorn::GetFpcr() const { @@ -176,7 +176,7 @@ void A64Unicorn::InterruptHook(uc_engine* uc, u32 int_number, void* user_data) { auto iss = esr & 0xFFFFFF; switch (ec) { - case 0x15: // SVC + case 0x15: // SVC this_->testenv.CallSVC(iss); break; default: @@ -204,7 +204,7 @@ bool A64Unicorn::UnmappedMemoryHook(uc_engine* uc, uc_mem_type /*type*/, u64 sta uc_err err = uc_mem_map_ptr(uc, base_address, page->data.size(), permissions, page->data.data()); if (err == UC_ERR_MAP) - return; // page already exists + return; // page already exists CHECKED(err); this_->pages.emplace_back(std::move(page)); @@ -212,8 +212,8 @@ bool A64Unicorn::UnmappedMemoryHook(uc_engine* uc, uc_mem_type /*type*/, u64 sta const auto is_in_range = [](u64 addr, u64 start, u64 end) { if (start <= end) - return addr >= start && addr <= end; // fffff[tttttt]fffff - return addr >= start || addr <= end; // ttttt]ffffff[ttttt + return addr >= start && addr <= end; // fffff[tttttt]fffff + return addr >= start || addr <= end; // ttttt]ffffff[ttttt }; const u64 start_address_page = start_address & ~u64(0xFFF); diff --git a/tests/unicorn_emu/a64_unicorn.h b/tests/unicorn_emu/a64_unicorn.h index 362cc1d9..580c88a0 100644 --- a/tests/unicorn_emu/a64_unicorn.h +++ b/tests/unicorn_emu/a64_unicorn.h @@ -9,11 +9,11 @@ #include #ifdef _MSC_VER -#pragma warning(push, 0) -#include -#pragma warning(pop) +# pragma warning(push, 0) +# include +# pragma warning(pop) #else -#include +# include #endif #include "../A64/testenv.h"