diff --git a/src/frontend/translate/translate_arm/exception_generating.cpp b/src/frontend/translate/translate_arm/exception_generating.cpp
index a1ce2a82..8e1d3275 100644
--- a/src/frontend/translate/translate_arm/exception_generating.cpp
+++ b/src/frontend/translate/translate_arm/exception_generating.cpp
@@ -10,6 +10,7 @@ namespace Dynarmic {
 namespace Arm {
 
 bool ArmTranslatorVisitor::arm_BKPT(Cond cond, Imm12 imm12, Imm4 imm4) {
+    (void)(cond, imm12, imm4); // Unused
     return InterpretThisInstruction();
 }
 
diff --git a/src/frontend/translate/translate_arm/extension.cpp b/src/frontend/translate/translate_arm/extension.cpp
index 7a08acf8..1635075e 100644
--- a/src/frontend/translate/translate_arm/extension.cpp
+++ b/src/frontend/translate/translate_arm/extension.cpp
@@ -40,6 +40,7 @@ bool ArmTranslatorVisitor::arm_SXTAB(Cond cond, Reg n, Reg d, SignExtendRotation
 }
 
 bool ArmTranslatorVisitor::arm_SXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
+    (void)(cond, n, d, rotate, m); // Unused
     return InterpretThisInstruction();
 }
 
@@ -67,6 +68,7 @@ bool ArmTranslatorVisitor::arm_SXTB(Cond cond, Reg d, SignExtendRotation rotate,
 }
 
 bool ArmTranslatorVisitor::arm_SXTB16(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
+    (void)(cond, d, rotate, m); // Unused
     return InterpretThisInstruction();
 }
 
@@ -94,6 +96,7 @@ bool ArmTranslatorVisitor::arm_UXTAB(Cond cond, Reg n, Reg d, SignExtendRotation
 }
 
 bool ArmTranslatorVisitor::arm_UXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
+    (void)(cond, n, d, rotate, m); // Unused
     return InterpretThisInstruction();
 }
 
diff --git a/src/frontend/translate/translate_arm/load_store.cpp b/src/frontend/translate/translate_arm/load_store.cpp
index 7eaf8b2a..8ecbfcbc 100644
--- a/src/frontend/translate/translate_arm/load_store.cpp
+++ b/src/frontend/translate/translate_arm/load_store.cpp
@@ -586,7 +586,7 @@ bool ArmTranslatorVisitor::arm_STRB_imm(Cond cond, bool P, bool U, bool W, Reg n
 
     if (ConditionPassed(cond)) {
         const auto address = GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm12));
-        const auto value = (t == Reg::PC) ? ir.Imm8(ir.PC() - 8) : ir.GetRegister(t);
+        const auto value = (t == Reg::PC) ? ir.Imm8(static_cast<u8>(ir.PC() - 8)) : ir.GetRegister(t);
         ir.WriteMemory8(address, ir.LeastSignificantByte(value));
     }
 
@@ -603,7 +603,7 @@ bool ArmTranslatorVisitor::arm_STRB_reg(Cond cond, bool P, bool U, bool W, Reg n
     if (ConditionPassed(cond)) {
         const auto shifted = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag());
         const auto address = GetAddressingMode(ir, P, U, W, n, shifted.result);
-        const auto value = (t == Reg::PC) ? ir.Imm8(ir.PC() - 8) : ir.GetRegister(t);
+        const auto value = (t == Reg::PC) ? ir.Imm8(static_cast<u8>(ir.PC() - 8)) : ir.GetRegister(t);
         ir.WriteMemory8(address, ir.LeastSignificantByte(value));
     }
 
diff --git a/src/frontend/translate/translate_arm/parallel.cpp b/src/frontend/translate/translate_arm/parallel.cpp
index 6813c8e2..394eedd4 100644
--- a/src/frontend/translate/translate_arm/parallel.cpp
+++ b/src/frontend/translate/translate_arm/parallel.cpp
@@ -11,26 +11,32 @@ namespace Arm {
 
 // Parallel Add/Subtract (Modulo arithmetic) instructions
 bool ArmTranslatorVisitor::arm_SADD8(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_SADD16(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_SASX(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_SSAX(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_SSUB8(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_SSUB16(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
@@ -46,14 +52,17 @@ bool ArmTranslatorVisitor::arm_UADD8(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_UADD16(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_UASX(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_USAX(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
@@ -69,6 +78,7 @@ bool ArmTranslatorVisitor::arm_USUB8(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_USUB16(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
@@ -95,10 +105,12 @@ bool ArmTranslatorVisitor::arm_QADD16(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_QASX(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_QSAX(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
@@ -139,10 +151,12 @@ bool ArmTranslatorVisitor::arm_UQADD16(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_UQASX(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_UQSAX(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
@@ -189,18 +203,22 @@ bool ArmTranslatorVisitor::arm_SHADD16(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_SHASX(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_SHSAX(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_SHSUB8(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_SHSUB16(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
@@ -225,10 +243,12 @@ bool ArmTranslatorVisitor::arm_UHADD16(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_UHASX(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_UHSAX(Cond cond, Reg n, Reg d, Reg m) {
+    (void)(cond, n, d, m); // Unused
     return InterpretThisInstruction();
 }
 
diff --git a/src/frontend/translate/translate_arm/translate_arm.h b/src/frontend/translate/translate_arm/translate_arm.h
index 7687faa2..6413d8f2 100644
--- a/src/frontend/translate/translate_arm/translate_arm.h
+++ b/src/frontend/translate/translate_arm/translate_arm.h
@@ -214,8 +214,14 @@ struct ArmTranslatorVisitor final {
     bool arm_SEL(Cond cond, Reg n, Reg d, Reg m);
 
     // Unsigned sum of absolute difference functions
-    bool arm_USAD8(Cond cond, Reg d, Reg m, Reg n) { return InterpretThisInstruction(); }
-    bool arm_USADA8(Cond cond, Reg d, Reg a, Reg m, Reg n) { return InterpretThisInstruction(); }
+    bool arm_USAD8(Cond cond, Reg d, Reg m, Reg n) {
+        (void)(cond, d, m, n); // Unused
+        return InterpretThisInstruction();
+    }
+    bool arm_USADA8(Cond cond, Reg d, Reg a, Reg m, Reg n) {
+        (void)(cond, d, a, m, n); // Unused
+        return InterpretThisInstruction();
+    }
 
     // Packing instructions
     bool arm_PKHBT(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m);
@@ -227,10 +233,22 @@ struct ArmTranslatorVisitor final {
     bool arm_REVSH(Cond cond, Reg d, Reg m);
 
     // Saturation instructions
-    bool arm_SSAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) { return InterpretThisInstruction(); }
-    bool arm_SSAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n) { return InterpretThisInstruction(); }
-    bool arm_USAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) { return InterpretThisInstruction(); }
-    bool arm_USAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n) { return InterpretThisInstruction(); }
+    bool arm_SSAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) {
+        (void)(cond, sat_imm, d, imm5, sh, n); // Unused
+        return InterpretThisInstruction();
+    }
+    bool arm_SSAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n) {
+        (void)(cond, sat_imm, d, n); // Unused
+        return InterpretThisInstruction();
+    }
+    bool arm_USAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) {
+        (void)(cond, sat_imm, d, imm5, sh, n); // Unused
+        return InterpretThisInstruction();
+    }
+    bool arm_USAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n) {
+        (void)(cond, sat_imm, d, n); // Unused
+        return InterpretThisInstruction();
+    }
 
     // Multiply (Normal) instructions
     bool arm_MLA(Cond cond, bool S, Reg d, Reg a, Reg m, Reg n);
@@ -308,10 +326,22 @@ struct ArmTranslatorVisitor final {
     bool arm_UHSUB16(Cond cond, Reg n, Reg d, Reg m);
 
     // Saturated Add/Subtract instructions
-    bool arm_QADD(Cond cond, Reg n, Reg d, Reg m) { return InterpretThisInstruction(); }
-    bool arm_QSUB(Cond cond, Reg n, Reg d, Reg m) { return InterpretThisInstruction(); }
-    bool arm_QDADD(Cond cond, Reg n, Reg d, Reg m) { return InterpretThisInstruction(); }
-    bool arm_QDSUB(Cond cond, Reg n, Reg d, Reg m) { return InterpretThisInstruction(); }
+    bool arm_QADD(Cond cond, Reg n, Reg d, Reg m) {
+        (void)(cond, d, m, n); // Unused
+        return InterpretThisInstruction();
+    }
+    bool arm_QSUB(Cond cond, Reg n, Reg d, Reg m) {
+        (void)(cond, d, m, n); // Unused
+        return InterpretThisInstruction();
+    }
+    bool arm_QDADD(Cond cond, Reg n, Reg d, Reg m) {
+        (void)(cond, d, m, n); // Unused
+        return InterpretThisInstruction();
+    }
+    bool arm_QDSUB(Cond cond, Reg n, Reg d, Reg m) {
+        (void)(cond, d, m, n); // Unused
+        return InterpretThisInstruction();
+    }
 
     // Synchronization Primitive instructions
     bool arm_CLREX();