From 5f77ab28ee439320734429d408843b7c53033a27 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sun, 11 Feb 2018 16:24:55 +0000 Subject: [PATCH] A64: Implement SSHLL, SSHLL2 --- src/frontend/A64/decoder/a64.inc | 2 +- src/frontend/A64/translate/impl/impl.h | 2 +- .../impl/simd_shift_by_immediate.cpp | 21 +++++++++++++++++++ 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 1a6fc7ff..bcfcb212 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -788,7 +788,7 @@ INST(SHL_2, "SHL", "0Q001 //INST(RSHRN, "RSHRN, RSHRN2", "0Q0011110IIIIiii100011nnnnnddddd") //INST(SQSHRN_2, "SQSHRN, SQSHRN2", "0Q0011110IIIIiii100101nnnnnddddd") //INST(SQRSHRN_2, "SQRSHRN, SQRSHRN2", "0Q0011110IIIIiii100111nnnnnddddd") -//INST(SSHLL, "SSHLL, SSHLL2", "0Q0011110IIIIiii101001nnnnnddddd") +INST(SSHLL, "SSHLL, SSHLL2", "0Q0011110IIIIiii101001nnnnnddddd") //INST(SCVTF_fix_2, "SCVTF (vector, fixed-point)", "0Q0011110IIIIiii111001nnnnnddddd") //INST(FCVTZS_fix_2, "FCVTZS (vector, fixed-point)", "0Q0011110IIIIiii111111nnnnnddddd") INST(USHR_2, "USHR", "0Q1011110IIIIiii000001nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/impl.h b/src/frontend/A64/translate/impl/impl.h index 3dfbbe81..d2f824e5 100644 --- a/src/frontend/A64/translate/impl/impl.h +++ b/src/frontend/A64/translate/impl/impl.h @@ -865,7 +865,7 @@ struct TranslatorVisitor final { bool RSHRN(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); bool SQSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); bool SQRSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Reg Rd); - bool SSHLL(bool Q, Imm<4> immh, Imm<3> immb, Reg Rn, Vec Vd); + bool SSHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); bool SCVTF_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); bool FCVTZS_fix_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); bool USHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd); diff --git a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp index a06c4c74..d91d1767 100644 --- a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp +++ b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp @@ -68,6 +68,27 @@ bool TranslatorVisitor::SHL_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) return true; } +bool TranslatorVisitor::SSHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { + if (immh == 0b0000) { + return DecodeError(); + } + if (immh.Bit<3>()) { + return ReservedValue(); + } + const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend()); + const size_t datasize = 64; + const size_t part = Q ? 1 : 0; + + const u8 shift_amount = concatenate(immh, immb).ZeroExtend() - static_cast(esize); + + const IR::U128 operand = Vpart(datasize, Vn, part); + const IR::U128 expanded_operand = ir.VectorSignExtend(esize, operand); + const IR::U128 result = ir.VectorLogicalShiftLeft(2 * esize, expanded_operand, shift_amount); + + V(2 * datasize, Vd, result); + return true; +} + bool TranslatorVisitor::USHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { if (immh == 0b0000) { return DecodeError();