commit 621367dce8abf82e3924679d72f4da0913cc1520 Author: Merry Date: Sun Jul 10 09:35:44 2022 +0100 Squashed 'externals/oaknut/' content from commit 86f2ca872 git-subtree-dir: externals/oaknut git-subtree-split: 86f2ca87222e59fb0b89b2f2a6b422a58a2e0892 diff --git a/.clang-format b/.clang-format new file mode 100644 index 00000000..28884fb5 --- /dev/null +++ b/.clang-format @@ -0,0 +1,218 @@ +--- +Language: Cpp +AccessModifierOffset: -4 +AlignAfterOpenBracket: Align +AlignConsecutiveMacros: None +AlignConsecutiveAssignments: None +AlignConsecutiveBitFields: None +AlignConsecutiveDeclarations: None +AlignConsecutiveMacros: None +AlignEscapedNewlines: Right +AlignOperands: AlignAfterOperator +AlignTrailingComments: true +AllowAllArgumentsOnNextLine: true +AllowAllConstructorInitializersOnNextLine: true +AllowAllParametersOfDeclarationOnNextLine: true +AllowShortEnumsOnASingleLine: true +AllowShortBlocksOnASingleLine: Empty +AllowShortCaseLabelsOnASingleLine: false +AllowShortFunctionsOnASingleLine: Inline +AllowShortLambdasOnASingleLine: All +AllowShortIfStatementsOnASingleLine: Never +AllowShortLoopsOnASingleLine: false +AlwaysBreakAfterDefinitionReturnType: None +AlwaysBreakAfterReturnType: None +AlwaysBreakBeforeMultilineStrings: true +AlwaysBreakTemplateDeclarations: Yes +AttributeMacros: + - __capability +BinPackArguments: true +BinPackParameters: false +BitFieldColonSpacing: Both +BraceWrapping: + AfterCaseLabel: false + AfterClass: false + AfterControlStatement: Never + AfterEnum: false + AfterFunction: true + AfterNamespace: false + AfterObjCDeclaration: false + AfterStruct: false + AfterUnion: false + AfterExternBlock: false + BeforeCatch: false + BeforeElse: false + BeforeLambdaBody: false + BeforeWhile: false + IndentBraces: false + SplitEmptyFunction: false + SplitEmptyRecord: false + SplitEmptyNamespace: false +BreakBeforeBinaryOperators: All +BreakBeforeBraces: Custom +BreakBeforeConceptDeclarations: true +BreakBeforeTernaryOperators: true +BreakBeforeInheritanceComma: false +BreakConstructorInitializersBeforeComma: true +BreakConstructorInitializers: BeforeComma +BreakInheritanceList: BeforeComma +BreakAfterJavaFieldAnnotations: false +BreakStringLiterals: true +ColumnLimit: 0 +CommentPragmas: '^ IWYU pragma:' +CompactNamespaces: false +ConstructorInitializerAllOnOneLineOrOnePerLine: true +ConstructorInitializerIndentWidth: 4 +ContinuationIndentWidth: 4 +Cpp11BracedListStyle: true +DeriveLineEnding: true +DerivePointerAlignment: false +DisableFormat: false +# EmptyLineAfterAccessModifier: Leave +EmptyLineBeforeAccessModifier: Always +ExperimentalAutoDetectBinPacking: false +FixNamespaceComments: true +ForEachMacros: + - foreach + - Q_FOREACH + - BOOST_FOREACH +IncludeBlocks: Regroup +IncludeCategories: + - Regex: '^' + Priority: 1 + SortPriority: 0 + CaseSensitive: false + - Regex: '(^)|(^)|(^)' + Priority: 1 + SortPriority: 0 + CaseSensitive: false + - Regex: '^<([^\.])*>$' + Priority: 2 + SortPriority: 0 + CaseSensitive: false + - Regex: '^<.*\.' + Priority: 3 + SortPriority: 0 + CaseSensitive: false + - Regex: '.*' + Priority: 4 + SortPriority: 0 + CaseSensitive: false +IncludeIsMainRegex: '([-_](test|unittest))?$' +IncludeIsMainSourceRegex: '' +# IndentAccessModifiers: false +IndentCaseBlocks: false +IndentCaseLabels: false +IndentExternBlock: NoIndent +IndentGotoLabels: false +IndentPPDirectives: AfterHash +IndentRequires: false +IndentWidth: 4 +IndentWrappedFunctionNames: false +# InsertTrailingCommas: None +JavaScriptQuotes: Leave +JavaScriptWrapImports: true +KeepEmptyLinesAtTheStartOfBlocks: false +MacroBlockBegin: '' +MacroBlockEnd: '' +MaxEmptyLinesToKeep: 1 +NamespaceIndentation: None +NamespaceMacros: +ObjCBinPackProtocolList: Never +ObjCBlockIndentWidth: 2 +ObjCBreakBeforeNestedBlockParam: true +ObjCSpaceAfterProperty: false +ObjCSpaceBeforeProtocolList: true +PenaltyBreakAssignment: 2 +PenaltyBreakBeforeFirstCallParameter: 1 +PenaltyBreakComment: 300 +PenaltyBreakFirstLessLess: 120 +PenaltyBreakString: 1000 +PenaltyBreakTemplateDeclaration: 10 +PenaltyExcessCharacter: 1000000 +PenaltyReturnTypeOnItsOwnLine: 200 +PenaltyIndentedWhitespace: 0 +PointerAlignment: Left +RawStringFormats: + - Language: Cpp + Delimiters: + - cc + - CC + - cpp + - Cpp + - CPP + - 'c++' + - 'C++' + CanonicalDelimiter: '' + BasedOnStyle: google + - Language: TextProto + Delimiters: + - pb + - PB + - proto + - PROTO + EnclosingFunctions: + - EqualsProto + - EquivToProto + - PARSE_PARTIAL_TEXT_PROTO + - PARSE_TEST_PROTO + - PARSE_TEXT_PROTO + - ParseTextOrDie + - ParseTextProtoOrDie + - ParseTestProto + - ParsePartialTestProto + CanonicalDelimiter: '' + BasedOnStyle: google +ReflowComments: true +# ShortNamespaceLines: 5 +SortIncludes: true +SortJavaStaticImport: Before +SortUsingDeclarations: true +SpaceAfterCStyleCast: false +SpaceAfterLogicalNot: false +SpaceAfterTemplateKeyword: false +SpaceAroundPointerQualifiers: Default +SpaceBeforeAssignmentOperators: true +SpaceBeforeCaseColon: false +SpaceBeforeCpp11BracedList: false +SpaceBeforeCtorInitializerColon: true +SpaceBeforeInheritanceColon: true +SpaceBeforeParens: ControlStatements +SpaceAroundPointerQualifiers: Default +SpaceBeforeRangeBasedForLoopColon: true +SpaceBeforeSquareBrackets: false +SpaceInEmptyBlock: false +SpaceInEmptyParentheses: false +SpacesBeforeTrailingComments: 2 +SpacesInAngles: false +SpacesInConditionalStatement: false +SpacesInCStyleCastParentheses: false +SpacesInConditionalStatement: false +SpacesInContainerLiterals: false +# SpacesInLineCommentPrefix: -1 +SpacesInParentheses: false +SpacesInSquareBrackets: false +Standard: Latest +StatementAttributeLikeMacros: + - Q_EMIT +StatementMacros: + - Q_UNUSED + - QT_REQUIRE_VERSION +TabWidth: 4 +TypenameMacros: +UseCRLF: false +UseTab: Never +WhitespaceSensitiveMacros: + - STRINGIZE + - PP_STRINGIZE + - BOOST_PP_STRINGIZE + - NS_SWIFT_NAME + - CF_SWIFT_NAME + - FCODE + - ICODE +... + diff --git a/.github/workflows/build-and-test.yml b/.github/workflows/build-and-test.yml new file mode 100644 index 00000000..dba7b8a9 --- /dev/null +++ b/.github/workflows/build-and-test.yml @@ -0,0 +1,38 @@ +on: [push, pull_request] + +jobs: + test_on_ubuntu: + runs-on: ubuntu-latest + name: Build on ${{ matrix.distro }} ${{ matrix.arch }} + + strategy: + matrix: + include: + - arch: aarch64 + distro: ubuntu_latest + + steps: + - uses: actions/checkout@v3 + - uses: uraimo/run-on-arch-action@v2 + name: Build and Test + id: build + with: + arch: ${{ matrix.arch }} + distro: ${{ matrix.distro }} + shell: /bin/bash + + install: | + apt-get update -q -y + apt-get install -q -y make cmake g++ git + + pushd /tmp + git clone https://github.com/catchorg/Catch2.git + cd Catch2 + cmake -Bbuild -H. -DBUILD_TESTING=OFF + cmake --build build/ --target install + popd + + run: | + cmake -Bbuild -H. + cmake --build build + ./build/oaknut-tests diff --git a/.gitignore b/.gitignore new file mode 100644 index 00000000..6b86fecd --- /dev/null +++ b/.gitignore @@ -0,0 +1,4 @@ +.DS_Store +a.out +work/ +*build*/ diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 00000000..b6f139b9 --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,57 @@ +cmake_minimum_required(VERSION 3.8) +project(oaknut LANGUAGES CXX VERSION 0.0.0) + +# Determine if we're built as a subproject (using add_subdirectory) +# or if this is the master project. +set(MASTER_PROJECT OFF) +if (CMAKE_CURRENT_SOURCE_DIR STREQUAL CMAKE_SOURCE_DIR) + set(MASTER_PROJECT ON) +endif() + +# Disable in-source builds +set(CMAKE_DISABLE_SOURCE_CHANGES ON) +set(CMAKE_DISABLE_IN_SOURCE_BUILD ON) +if ("${CMAKE_SOURCE_DIR}" STREQUAL "${CMAKE_BINARY_DIR}") + message(SEND_ERROR "In-source builds are not allowed.") +endif() + +# Source project files +set(header_files + ${CMAKE_CURRENT_SOURCE_DIR}/include/oaknut/impl/arm64_encode_helpers.inc.hpp + ${CMAKE_CURRENT_SOURCE_DIR}/include/oaknut/impl/arm64_mnemonics.inc.hpp + ${CMAKE_CURRENT_SOURCE_DIR}/include/oaknut/impl/enum.hpp + ${CMAKE_CURRENT_SOURCE_DIR}/include/oaknut/impl/fpsimd_mnemonics.inc.hpp + ${CMAKE_CURRENT_SOURCE_DIR}/include/oaknut/impl/imm.hpp + ${CMAKE_CURRENT_SOURCE_DIR}/include/oaknut/impl/list.hpp + ${CMAKE_CURRENT_SOURCE_DIR}/include/oaknut/impl/multi_typed_name.hpp + ${CMAKE_CURRENT_SOURCE_DIR}/include/oaknut/impl/offset.hpp + ${CMAKE_CURRENT_SOURCE_DIR}/include/oaknut/impl/reg.hpp + ${CMAKE_CURRENT_SOURCE_DIR}/include/oaknut/impl/string_literal.hpp + ${CMAKE_CURRENT_SOURCE_DIR}/include/oaknut/oaknut.hpp +) + +# Library definition +add_library(oaknut INTERFACE) +add_library(merry::oaknut ALIAS oaknut) +target_sources(oaknut INTERFACE "$") +target_include_directories(oaknut INTERFACE $) +target_compile_features(oaknut INTERFACE cxx_std_20) + +# Tests +if (MASTER_PROJECT) + find_package(Catch2 3 REQUIRED) + + add_executable(oaknut-tests + tests/basic.cpp + tests/fpsimd.cpp + tests/general.cpp + ) + target_include_directories(oaknut-tests PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/tests) + target_link_libraries(oaknut-tests PRIVATE Catch2::Catch2WithMain merry::oaknut) + target_compile_options(oaknut-tests PRIVATE -Wall -Wextra -Wcast-qual -pedantic -pedantic-errors -Wfatal-errors -Wno-missing-braces) + + include(CTest) + include(Catch) + catch_discover_tests(oaknut-tests) + enable_testing() +endif() diff --git a/LICENSE b/LICENSE new file mode 100644 index 00000000..19f95710 --- /dev/null +++ b/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2022 merryhime + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/README.md b/README.md new file mode 100644 index 00000000..4b3356db --- /dev/null +++ b/README.md @@ -0,0 +1,29 @@ +# Oaknut + +*A C++20 assembler for AArch64 (ARMv8.0)* + +Oaknut is a header-only library that allows one to dynamically assemble code in-memory at runtime. + +## Usage + +Simple example: + +```cpp +using EmittedFunction = int (*)(); + +EmittedFunction EmitExample(oaknut::CodeGenerator& code, int value) +{ + using namespace oaknut::util; + + EmittedFunction result = code.ptr(); + + code.MOVZ(W0, value); + code.RET(); + + return result; +} +``` + +## License + +This project is [MIT licensed](LICENSE). diff --git a/include/oaknut/code_block.hpp b/include/oaknut/code_block.hpp new file mode 100644 index 00000000..c7b06664 --- /dev/null +++ b/include/oaknut/code_block.hpp @@ -0,0 +1,124 @@ +// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime +// SPDX-License-Identifier: MIT + +#include +#include +#include + +#if defined(_WIN32) +# include +#elif defined(__APPLE__) +# include +# include +# include +# include +#else +# include +#endif + +namespace oaknut { + +class CodeBlock { +public: + explicit CodeBlock(std::size_t size) + : m_size(size) + { +#if defined(_WIN32) + m_memory = (std::uint32_t*)VirtualAlloc(nullptr, size, MEM_COMMIT, PAGE_EXECUTE_READWRITE); +#elif defined(__APPLE__) + m_memory = (std::uint32_t*)mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANON | MAP_PRIVATE | MAP_JIT, -1, 0); +#else + m_memory = (std::uint32_t*)mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANON | MAP_PRIVATE, -1, 0); +#endif + + if (m_memory == nullptr) + throw std::bad_alloc{}; + } + + ~CodeBlock() + { + if (m_memory == nullptr) + return; + +#if defined(_WIN32) + VirtualFree((void*)m_memory, 0, MEM_RELEASE); +#else + munmap(m_memory, m_size); +#endif + } + + CodeBlock(const CodeBlock&) = delete; + CodeBlock& operator=(const CodeBlock&) = delete; + CodeBlock(CodeBlock&&) = delete; + CodeBlock& operator=(CodeBlock&&) = delete; + + std::uint32_t* ptr() const + { + return m_memory; + } + + void protect() + { +#if defined(__APPLE__) + pthread_jit_write_protect_np(1); +#endif + } + + void unprotect() + { +#if defined(__APPLE__) + pthread_jit_write_protect_np(0); +#endif + } + + void invalidate(std::uint32_t* mem, std::size_t size) + { +#if defined(__APPLE__) + sys_icache_invalidate(mem, size); +#else + static std::size_t icache_line_size = 0x10000, dcache_line_size = 0x10000; + + std::uint64_t ctr; + __asm__ volatile("mrs %0, ctr_el0" + : "=r"(ctr)); + + const std::size_t isize = icache_line_size = std::min(icache_line_size, 4 << ((ctr >> 0) & 0xf)); + const std::size_t dsize = dcache_line_size = std::min(dcache_line_size, 4 << ((ctr >> 16) & 0xf)); + + const std::uintptr_t end = (std::uintptr_t)mem + size; + + for (std::uintptr_t addr = ((std::uintptr_t)mem) & ~(dsize - 1); addr < end; addr += dsize) { + __asm__ volatile("dc cvau, %0" + : + : "r"(addr) + : "memory"); + } + __asm__ volatile("dsb ish\n" + : + : + : "memory"); + + for (std::uintptr_t addr = ((std::uintptr_t)mem) & ~(isize - 1); addr < end; addr += isize) { + __asm__ volatile("ic ivau, %0" + : + : "r"(addr) + : "memory"); + } + __asm__ volatile("dsb ish\nisb\n" + : + : + : "memory"); +#endif + } + + void invalidate_all() + { + invalidate(m_memory, m_size); + } + +protected: + std::uint32_t* m_memory; + std::size_t m_size = 0; +}; + +} // namespace oaknut diff --git a/include/oaknut/impl/arm64_encode_helpers.inc.hpp b/include/oaknut/impl/arm64_encode_helpers.inc.hpp new file mode 100644 index 00000000..5886e62e --- /dev/null +++ b/include/oaknut/impl/arm64_encode_helpers.inc.hpp @@ -0,0 +1,155 @@ +// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime +// SPDX-License-Identifier: MIT + +template +static constexpr std::uint32_t pdep(std::uint32_t val) +{ + std::uint32_t mask = mask_; + std::uint32_t res = 0; + for (std::uint32_t bb = 1; mask; bb += bb) { + if (val & bb) + res |= mask & -mask; + mask &= mask - 1; + } + return res; +} + +#define OAKNUT_STD_ENCODE(TYPE, ACCESS, SIZE) \ + template \ + std::uint32_t encode(TYPE v) \ + { \ + static_assert(std::popcount(splat) == SIZE); \ + return pdep(static_cast(ACCESS)); \ + } + +OAKNUT_STD_ENCODE(RReg, v.index() & 31, 5) +OAKNUT_STD_ENCODE(VReg, v.index() & 31, 5) +OAKNUT_STD_ENCODE(VRegArranged, v.index() & 31, 5) + +OAKNUT_STD_ENCODE(AddSubImm, v.m_encoded, 13) +OAKNUT_STD_ENCODE(BitImm32, v.m_encoded, 12) +OAKNUT_STD_ENCODE(BitImm64, v.m_encoded, 13) +OAKNUT_STD_ENCODE(LslShift<32>, v.m_encoded, 12) +OAKNUT_STD_ENCODE(LslShift<64>, v.m_encoded, 12) +OAKNUT_STD_ENCODE(FImm8, v.m_encoded, 8) +OAKNUT_STD_ENCODE(RepImm, v.m_encoded, 8) + +OAKNUT_STD_ENCODE(Cond, v, 4) +OAKNUT_STD_ENCODE(AddSubExt, v, 3) +OAKNUT_STD_ENCODE(IndexExt, v, 3) +OAKNUT_STD_ENCODE(AddSubShift, v, 2) +OAKNUT_STD_ENCODE(LogShift, v, 2) +OAKNUT_STD_ENCODE(PstateField, v, 6) +OAKNUT_STD_ENCODE(SystemReg, v, 15) +OAKNUT_STD_ENCODE(AtOp, v, 7) +OAKNUT_STD_ENCODE(BarrierOp, v, 4) +OAKNUT_STD_ENCODE(DcOp, v, 10) +OAKNUT_STD_ENCODE(IcOp, v, 10) +OAKNUT_STD_ENCODE(PrfOp, v, 5) +OAKNUT_STD_ENCODE(TlbiOp, v, 10) + +template +std::uint32_t encode(MovImm16 v) +{ + static_assert(std::popcount(splat) == 17 || std::popcount(splat) == 18); + if constexpr (std::popcount(splat) == 17) { + constexpr std::uint32_t mask = (1 << std::popcount(splat)) - 1; + if ((v.m_encoded & mask) != v.m_encoded) + throw "invalid MovImm16"; + } + return pdep(v.m_encoded); +} + +template +std::uint32_t encode(Imm v) +{ + static_assert(std::popcount(splat) >= imm_size); + return pdep(v.value()); +} + +template +std::uint32_t encode(ImmChoice v) +{ + static_assert(std::popcount(splat) == 1); + return pdep(v.m_encoded); +} + +template +std::uint32_t encode(ImmChoice v) +{ + static_assert(std::popcount(splat) == 2); + return pdep(v.m_encoded); +} + +template +std::uint32_t encode(SOffset v) +{ + static_assert(std::popcount(splat) == size - align); + return pdep(v.m_encoded); +} + +template +std::uint32_t encode(POffset v) +{ + static_assert(std::popcount(splat) == size - align); + return pdep(v.m_encoded); +} + +template +std::uint32_t encode(std::uint32_t v) +{ + return pdep(v); +} + +template +std::uint32_t encode(List v) +{ + return encode(v.m_base); +} + +#undef OAKNUT_STD_ENCODE + +void addsubext_lsl_correction(AddSubExt& ext, XRegSp) +{ + if (ext == AddSubExt::LSL) + ext = AddSubExt::UXTX; +} +void addsubext_lsl_correction(AddSubExt& ext, WRegWsp) +{ + if (ext == AddSubExt::LSL) + ext = AddSubExt::UXTW; +} +void addsubext_lsl_correction(AddSubExt& ext, XReg) +{ + if (ext == AddSubExt::LSL) + ext = AddSubExt::UXTX; +} +void addsubext_lsl_correction(AddSubExt& ext, WReg) +{ + if (ext == AddSubExt::LSL) + ext = AddSubExt::UXTW; +} + +void addsubext_verify_reg_size(AddSubExt ext, RReg rm) +{ + if (rm.bitsize() == 32 && (static_cast(ext) & 0b011) != 0b011) + return; + if (rm.bitsize() == 64 && (static_cast(ext) & 0b011) == 0b011) + return; + throw "invalid AddSubExt choice for rm size"; +} + +void indexext_verify_reg_size(IndexExt ext, RReg rm) +{ + if (rm.bitsize() == 32 && (static_cast(ext) & 1) == 0) + return; + if (rm.bitsize() == 64 && (static_cast(ext) & 1) == 1) + return; + throw "invalid IndexExt choice for rm size"; +} + +void tbz_verify_reg_size(RReg rt, Imm<6> imm) +{ + if (rt.bitsize() == 32 && imm.value() >= 32) + throw "invalid imm choice for rt size"; +} diff --git a/include/oaknut/impl/arm64_mnemonics.inc.hpp b/include/oaknut/impl/arm64_mnemonics.inc.hpp new file mode 100644 index 00000000..7fd65f05 --- /dev/null +++ b/include/oaknut/impl/arm64_mnemonics.inc.hpp @@ -0,0 +1,1709 @@ +// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime +// SPDX-License-Identifier: MIT + +void ADC(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010000mmmmm000000nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void ADC(XReg xd, XReg xn, XReg xm) +{ + emit<"10011010000mmmmm000000nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void ADCS(WReg wd, WReg wn, WReg wm) +{ + emit<"00111010000mmmmm000000nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void ADCS(XReg xd, XReg xn, XReg xm) +{ + emit<"10111010000mmmmm000000nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void ADD(WRegWsp wd, WRegWsp wn, WReg wm, AddSubExt ext = AddSubExt::LSL, Imm<3> shift_amount = 0) +{ + addsubext_lsl_correction(ext, wd); + emit<"00001011001mmmmmxxxiiinnnnnddddd", "d", "n", "m", "x", "i">(wd, wn, wm, ext, shift_amount); +} +void ADD(XRegSp xd, XRegSp xn, RReg rm, AddSubExt ext = AddSubExt::LSL, Imm<3> shift_amount = 0) +{ + addsubext_lsl_correction(ext, xd); + addsubext_verify_reg_size(ext, rm); + emit<"10001011001mmmmmxxxiiinnnnnddddd", "d", "n", "m", "x", "i">(xd, xn, rm, ext, shift_amount); +} +void ADD(WRegWsp wd, WRegWsp wn, AddSubImm imm) +{ + emit<"000100010siiiiiiiiiiiinnnnnddddd", "d", "n", "si">(wd, wn, imm); +} +void ADD(WRegWsp wd, WRegWsp wn, Imm<12> imm, LslSymbol, ImmChoice<0, 12> shift_amount) +{ + ADD(wd, wn, AddSubImm{imm.value(), static_cast(shift_amount.m_encoded)}); +} +void ADD(XRegSp xd, XRegSp xn, AddSubImm imm) +{ + emit<"100100010siiiiiiiiiiiinnnnnddddd", "d", "n", "si">(xd, xn, imm); +} +void ADD(XRegSp xd, XRegSp xn, Imm<12> imm, LslSymbol, ImmChoice<0, 12> shift_amount) +{ + ADD(xd, xn, AddSubImm{imm.value(), static_cast(shift_amount.m_encoded)}); +} +void ADD(WReg wd, WReg wn, WReg wm, AddSubShift shift = AddSubShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"00001011ss0mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(wd, wn, wm, shift, shift_amount); +} +void ADD(XReg xd, XReg xn, XReg xm, AddSubShift shift = AddSubShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"10001011ss0mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(xd, xn, xm, shift, shift_amount); +} +void ADDS(WReg wd, WRegWsp wn, WReg wm, AddSubExt ext = AddSubExt::LSL, Imm<3> shift_amount = 0) +{ + addsubext_lsl_correction(ext, wd); + emit<"00101011001mmmmmxxxiiinnnnnddddd", "d", "n", "m", "x", "i">(wd, wn, wm, ext, shift_amount); +} +void ADDS(XReg xd, XRegSp xn, RReg rm, AddSubExt ext = AddSubExt::LSL, Imm<3> shift_amount = 0) +{ + addsubext_lsl_correction(ext, xd); + addsubext_verify_reg_size(ext, rm); + emit<"10101011001mmmmmxxxiiinnnnnddddd", "d", "n", "m", "x", "i">(xd, xn, rm, ext, shift_amount); +} +void ADDS(WReg wd, WRegWsp wn, AddSubImm imm) +{ + emit<"001100010siiiiiiiiiiiinnnnnddddd", "d", "n", "si">(wd, wn, imm); +} +void ADDS(WReg wd, WRegWsp wn, Imm<12> imm, LslSymbol, ImmChoice<0, 12> shift_amount) +{ + ADDS(wd, wn, AddSubImm{imm.value(), static_cast(shift_amount.m_encoded)}); +} +void ADDS(XReg xd, XRegSp xn, AddSubImm imm) +{ + emit<"101100010siiiiiiiiiiiinnnnnddddd", "d", "n", "si">(xd, xn, imm); +} +void ADDS(XReg xd, XRegSp xn, Imm<12> imm, LslSymbol, ImmChoice<0, 12> shift_amount) +{ + ADDS(xd, xn, AddSubImm{imm.value(), static_cast(shift_amount.m_encoded)}); +} +void ADDS(WReg wd, WReg wn, WReg wm, AddSubShift shift = AddSubShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"00101011ss0mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(wd, wn, wm, shift, shift_amount); +} +void ADDS(XReg xd, XReg xn, XReg xm, AddSubShift shift = AddSubShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"10101011ss0mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(xd, xn, xm, shift, shift_amount); +} +void ADR(XReg xd, AddrOffset<21, 0> label) +{ + emit<"0ii10000iiiiiiiiiiiiiiiiiiiddddd", "d", "i">(xd, label); +} +void ADRP(XReg xd, PageOffset<21> label) +{ + emit<"1ii10000iiiiiiiiiiiiiiiiiiiddddd", "d", "i">(xd, label); +} +void AND(WRegWsp wd, WReg wn, BitImm32 imm) +{ + emit<"0001001000rrrrrrssssssnnnnnddddd", "d", "n", "rs">(wd, wn, imm); +} +void AND(XRegSp xd, XReg xn, BitImm64 imm) +{ + emit<"100100100Nrrrrrrssssssnnnnnddddd", "d", "n", "Nrs">(xd, xn, imm); +} +void AND(WReg wd, WReg wn, WReg wm, LogShift shift = LogShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"00001010ss0mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(wd, wn, wm, shift, shift_amount); +} +void AND(XReg xd, XReg xn, XReg xm, LogShift shift = LogShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"10001010ss0mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(xd, xn, xm, shift, shift_amount); +} +void ANDS(WReg wd, WReg wn, BitImm32 imm) +{ + emit<"0111001000rrrrrrssssssnnnnnddddd", "d", "n", "rs">(wd, wn, imm); +} +void ANDS(XReg xd, XReg xn, BitImm64 imm) +{ + emit<"111100100Nrrrrrrssssssnnnnnddddd", "d", "n", "Nrs">(xd, xn, imm); +} +void ANDS(WReg wd, WReg wn, WReg wm, LogShift shift = LogShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"01101010ss0mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(wd, wn, wm, shift, shift_amount); +} +void ANDS(XReg xd, XReg xn, XReg xm, LogShift shift = LogShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"11101010ss0mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(xd, xn, xm, shift, shift_amount); +} +void ASR(WReg wd, WReg wn, Imm<5> shift_amount) +{ + emit<"0001001100rrrrrr011111nnnnnddddd", "d", "n", "r">(wd, wn, shift_amount); +} +void ASR(XReg xd, XReg xn, Imm<6> shift_amount) +{ + emit<"1001001101rrrrrr111111nnnnnddddd", "d", "n", "r">(xd, xn, shift_amount); +} +void ASR(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010110mmmmm001010nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void ASR(XReg xd, XReg xn, XReg xm) +{ + emit<"10011010110mmmmm001010nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void ASRV(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010110mmmmm001010nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void ASRV(XReg xd, XReg xn, XReg xm) +{ + emit<"10011010110mmmmm001010nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void AT(AtOp op, XReg xt) +{ + emit<"1101010100001ooo0111100Mooottttt", "oMo", "t">(op, xt); +} +void B(AddrOffset<28, 2> label) +{ + emit<"000101iiiiiiiiiiiiiiiiiiiiiiiiii", "i">(label); +} +void B(Cond cond, AddrOffset<21, 2> label) +{ + emit<"01010100iiiiiiiiiiiiiiiiiii0cccc", "c", "i">(cond, label); +} +void BFI(WReg wd, WReg wn, Imm<5> lsb, Imm<5> width) +{ + if (width.value() == 0 || width.value() > (32 - lsb.value())) + throw "invalid width"; + emit<"0011001100rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(wd, wn, (-lsb.value()) & 31, width.value() - 1); +} +void BFI(XReg xd, XReg xn, Imm<6> lsb, Imm<6> width) +{ + if (width.value() == 0 || width.value() > (64 - lsb.value())) + throw "invalid width"; + emit<"1011001101rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(xd, xn, (-lsb.value()) & 63, width.value() - 1); +} +void BFM(WReg wd, WReg wn, Imm<5> immr, Imm<5> imms) +{ + emit<"0011001100rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(wd, wn, immr, imms); +} +void BFM(XReg xd, XReg xn, Imm<6> immr, Imm<6> imms) +{ + emit<"1011001101rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(xd, xn, immr, imms); +} +void BFXIL(WReg wd, WReg wn, Imm<5> lsb, Imm<5> width) +{ + if (width.value() == 0 || width.value() > (32 - lsb.value())) + throw "invalid width"; + emit<"0011001100rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(wd, wn, lsb.value(), lsb.value() + width.value() - 1); +} +void BFXIL(XReg xd, XReg xn, Imm<6> lsb, Imm<6> width) +{ + if (width.value() == 0 || width.value() > (64 - lsb.value())) + throw "invalid width"; + emit<"1011001101rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(xd, xn, lsb.value(), lsb.value() + width.value() - 1); +} +void BIC(WReg wd, WReg wn, WReg wm, LogShift shift = LogShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"00001010ss1mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(wd, wn, wm, shift, shift_amount); +} +void BIC(XReg xd, XReg xn, XReg xm, LogShift shift = LogShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"10001010ss1mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(xd, xn, xm, shift, shift_amount); +} +void BICS(WReg wd, WReg wn, WReg wm, LogShift shift = LogShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"01101010ss1mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(wd, wn, wm, shift, shift_amount); +} +void BICS(XReg xd, XReg xn, XReg xm, LogShift shift = LogShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"11101010ss1mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(xd, xn, xm, shift, shift_amount); +} +void BL(AddrOffset<28, 2> label) +{ + emit<"100101iiiiiiiiiiiiiiiiiiiiiiiiii", "i">(label); +} +void BLR(XReg xn) +{ + emit<"1101011000111111000000nnnnn00000", "n">(xn); +} +void BR(XReg xn) +{ + emit<"1101011000011111000000nnnnn00000", "n">(xn); +} +void BRK(Imm<16> imm) +{ + emit<"11010100001iiiiiiiiiiiiiiii00000", "i">(imm); +} +void CBNZ(WReg wt, AddrOffset<21, 2> label) +{ + emit<"00110101iiiiiiiiiiiiiiiiiiittttt", "t", "i">(wt, label); +} +void CBNZ(XReg xt, AddrOffset<21, 2> label) +{ + emit<"10110101iiiiiiiiiiiiiiiiiiittttt", "t", "i">(xt, label); +} +void CBZ(WReg wt, AddrOffset<21, 2> label) +{ + emit<"00110100iiiiiiiiiiiiiiiiiiittttt", "t", "i">(wt, label); +} +void CBZ(XReg xt, AddrOffset<21, 2> label) +{ + emit<"10110100iiiiiiiiiiiiiiiiiiittttt", "t", "i">(xt, label); +} +void CCMN(WReg wn, Imm<5> imm, Imm<4> nzcv, Cond cond) +{ + emit<"00111010010iiiiicccc10nnnnn0ffff", "n", "i", "f", "c">(wn, imm, nzcv, cond); +} +void CCMN(XReg xn, Imm<5> imm, Imm<4> nzcv, Cond cond) +{ + emit<"10111010010iiiiicccc10nnnnn0ffff", "n", "i", "f", "c">(xn, imm, nzcv, cond); +} +void CCMN(WReg wn, WReg wm, Imm<4> nzcv, Cond cond) +{ + emit<"00111010010mmmmmcccc00nnnnn0ffff", "n", "m", "f", "c">(wn, wm, nzcv, cond); +} +void CCMN(XReg xn, XReg xm, Imm<4> nzcv, Cond cond) +{ + emit<"10111010010mmmmmcccc00nnnnn0ffff", "n", "m", "f", "c">(xn, xm, nzcv, cond); +} +void CCMP(WReg wn, Imm<5> imm, Imm<4> nzcv, Cond cond) +{ + emit<"01111010010iiiiicccc10nnnnn0ffff", "n", "i", "f", "c">(wn, imm, nzcv, cond); +} +void CCMP(XReg xn, Imm<5> imm, Imm<4> nzcv, Cond cond) +{ + emit<"11111010010iiiiicccc10nnnnn0ffff", "n", "i", "f", "c">(xn, imm, nzcv, cond); +} +void CCMP(WReg wn, WReg wm, Imm<4> nzcv, Cond cond) +{ + emit<"01111010010mmmmmcccc00nnnnn0ffff", "n", "m", "f", "c">(wn, wm, nzcv, cond); +} +void CCMP(XReg xn, XReg xm, Imm<4> nzcv, Cond cond) +{ + emit<"11111010010mmmmmcccc00nnnnn0ffff", "n", "m", "f", "c">(xn, xm, nzcv, cond); +} +void CINC(WReg wd, WReg wn, Cond cond) +{ + if (cond == Cond::AL || cond == Cond::NV) + throw "invalid Cond"; + emit<"00011010100mmmmmcccc01nnnnnddddd", "d", "n", "m", "c">(wd, wn, wn, invert(cond)); +} +void CINC(XReg xd, XReg xn, Cond cond) +{ + if (cond == Cond::AL || cond == Cond::NV) + throw "invalid Cond"; + emit<"10011010100mmmmmcccc01nnnnnddddd", "d", "n", "m", "c">(xd, xn, xn, invert(cond)); +} +void CINV(WReg wd, WReg wn, Cond cond) +{ + if (cond == Cond::AL || cond == Cond::NV) + throw "invalid Cond"; + emit<"01011010100mmmmmcccc00nnnnnddddd", "d", "n", "m", "c">(wd, wn, wn, invert(cond)); +} +void CINV(XReg xd, XReg xn, Cond cond) +{ + if (cond == Cond::AL || cond == Cond::NV) + throw "invalid Cond"; + emit<"11011010100mmmmmcccc00nnnnnddddd", "d", "n", "m", "c">(xd, xn, xn, invert(cond)); +} +void CLREX(Imm<4> imm = 15) +{ + emit<"11010101000000110011MMMM01011111", "M">(imm); +} +void CLS(WReg wd, WReg wn) +{ + emit<"0101101011000000000101nnnnnddddd", "d", "n">(wd, wn); +} +void CLS(XReg xd, XReg xn) +{ + emit<"1101101011000000000101nnnnnddddd", "d", "n">(xd, xn); +} +void CLZ(WReg wd, WReg wn) +{ + emit<"0101101011000000000100nnnnnddddd", "d", "n">(wd, wn); +} +void CLZ(XReg xd, XReg xn) +{ + emit<"1101101011000000000100nnnnnddddd", "d", "n">(xd, xn); +} +void CMN(WRegWsp wn, WReg wm, AddSubExt ext = AddSubExt::LSL, Imm<3> shift_amount = 0) +{ + addsubext_lsl_correction(ext, wn); + emit<"00101011001mmmmmxxxiiinnnnn11111", "n", "m", "x", "i">(wn, wm, ext, shift_amount); +} +void CMN(XRegSp xn, RReg rm, AddSubExt ext = AddSubExt::LSL, Imm<3> shift_amount = 0) +{ + addsubext_lsl_correction(ext, xn); + addsubext_verify_reg_size(ext, rm); + emit<"10101011001mmmmmxxxiiinnnnn11111", "n", "m", "x", "i">(xn, rm, ext, shift_amount); +} +void CMN(WRegWsp wn, AddSubImm imm) +{ + emit<"001100010siiiiiiiiiiiinnnnn11111", "n", "si">(wn, imm); +} +void CMN(WRegWsp wn, Imm<12> imm, LslSymbol, ImmChoice<0, 12> shift_amount) +{ + CMN(wn, AddSubImm{imm.value(), static_cast(shift_amount.m_encoded)}); +} +void CMN(XRegSp xn, AddSubImm imm) +{ + emit<"101100010siiiiiiiiiiiinnnnn11111", "n", "si">(xn, imm); +} +void CMN(XRegSp xn, Imm<12> imm, LslSymbol, ImmChoice<0, 12> shift_amount) +{ + CMN(xn, AddSubImm{imm.value(), static_cast(shift_amount.m_encoded)}); +} +void CMN(WReg wn, WReg wm, AddSubShift shift = AddSubShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"00101011ss0mmmmmiiiiiinnnnn11111", "n", "m", "s", "i">(wn, wm, shift, shift_amount); +} +void CMN(XReg xn, XReg xm, AddSubShift shift = AddSubShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"10101011ss0mmmmmiiiiiinnnnn11111", "n", "m", "s", "i">(xn, xm, shift, shift_amount); +} +void CMP(WRegWsp wn, WReg wm, AddSubExt ext = AddSubExt::LSL, Imm<3> shift_amount = 0) +{ + addsubext_lsl_correction(ext, wn); + emit<"01101011001mmmmmxxxiiinnnnn11111", "n", "m", "x", "i">(wn, wm, ext, shift_amount); +} +void CMP(XRegSp xn, RReg rm, AddSubExt ext = AddSubExt::LSL, Imm<3> shift_amount = 0) +{ + addsubext_lsl_correction(ext, xn); + addsubext_verify_reg_size(ext, rm); + emit<"11101011001mmmmmxxxiiinnnnn11111", "n", "m", "x", "i">(xn, rm, ext, shift_amount); +} +void CMP(WRegWsp wn, AddSubImm imm) +{ + emit<"011100010siiiiiiiiiiiinnnnn11111", "n", "si">(wn, imm); +} +void CMP(WRegWsp wn, Imm<12> imm, LslSymbol, ImmChoice<0, 12> shift_amount) +{ + CMP(wn, AddSubImm{imm.value(), static_cast(shift_amount.m_encoded)}); +} +void CMP(XRegSp xn, AddSubImm imm) +{ + emit<"111100010siiiiiiiiiiiinnnnn11111", "n", "si">(xn, imm); +} +void CMP(XRegSp xn, Imm<12> imm, LslSymbol, ImmChoice<0, 12> shift_amount) +{ + CMP(xn, AddSubImm{imm.value(), static_cast(shift_amount.m_encoded)}); +} +void CMP(WReg wn, WReg wm, AddSubShift shift = AddSubShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"01101011ss0mmmmmiiiiiinnnnn11111", "n", "m", "s", "i">(wn, wm, shift, shift_amount); +} +void CMP(XReg xn, XReg xm, AddSubShift shift = AddSubShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"11101011ss0mmmmmiiiiiinnnnn11111", "n", "m", "s", "i">(xn, xm, shift, shift_amount); +} +void CNEG(WReg wd, WReg wn, Cond cond) +{ + if (cond == Cond::AL || cond == Cond::NV) + throw "invalid Cond"; + emit<"01011010100mmmmmcccc01nnnnnddddd", "d", "n", "m", "c">(wd, wn, wn, invert(cond)); +} +void CNEG(XReg xd, XReg xn, Cond cond) +{ + if (cond == Cond::AL || cond == Cond::NV) + throw "invalid Cond"; + emit<"11011010100mmmmmcccc01nnnnnddddd", "d", "n", "m", "c">(xd, xn, xn, invert(cond)); +} +void CRC32B(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010110mmmmm010000nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void CRC32H(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010110mmmmm010001nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void CRC32W(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010110mmmmm010010nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void CRC32X(WReg wd, WReg wn, XReg xm) +{ + emit<"10011010110mmmmm010011nnnnnddddd", "d", "n", "m">(wd, wn, xm); +} +void CRC32CB(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010110mmmmm010100nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void CRC32CH(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010110mmmmm010101nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void CRC32CW(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010110mmmmm010110nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void CRC32CX(WReg wd, WReg wn, XReg xm) +{ + emit<"10011010110mmmmm010111nnnnnddddd", "d", "n", "m">(wd, wn, xm); +} +void CSDB() +{ + emit<"11010101000000110010001010011111">(); +} +void CSEL(WReg wd, WReg wn, WReg wm, Cond cond) +{ + emit<"00011010100mmmmmcccc00nnnnnddddd", "d", "n", "m", "c">(wd, wn, wm, cond); +} +void CSEL(XReg xd, XReg xn, XReg xm, Cond cond) +{ + emit<"10011010100mmmmmcccc00nnnnnddddd", "d", "n", "m", "c">(xd, xn, xm, cond); +} +void CSET(WReg wd, Cond cond) +{ + if (cond == Cond::AL || cond == Cond::NV) + throw "invalid Cond"; + emit<"0001101010011111cccc0111111ddddd", "d", "c">(wd, invert(cond)); +} +void CSET(XReg xd, Cond cond) +{ + if (cond == Cond::AL || cond == Cond::NV) + throw "invalid Cond"; + emit<"1001101010011111cccc0111111ddddd", "d", "c">(xd, invert(cond)); +} +void CSETM(WReg wd, Cond cond) +{ + if (cond == Cond::AL || cond == Cond::NV) + throw "invalid Cond"; + emit<"0101101010011111cccc0011111ddddd", "d", "c">(wd, invert(cond)); +} +void CSETM(XReg xd, Cond cond) +{ + if (cond == Cond::AL || cond == Cond::NV) + throw "invalid Cond"; + emit<"1101101010011111cccc0011111ddddd", "d", "c">(xd, invert(cond)); +} +void CSINC(WReg wd, WReg wn, WReg wm, Cond cond) +{ + emit<"00011010100mmmmmcccc01nnnnnddddd", "d", "n", "m", "c">(wd, wn, wm, cond); +} +void CSINC(XReg xd, XReg xn, XReg xm, Cond cond) +{ + emit<"10011010100mmmmmcccc01nnnnnddddd", "d", "n", "m", "c">(xd, xn, xm, cond); +} +void CSINV(WReg wd, WReg wn, WReg wm, Cond cond) +{ + emit<"01011010100mmmmmcccc00nnnnnddddd", "d", "n", "m", "c">(wd, wn, wm, cond); +} +void CSINV(XReg xd, XReg xn, XReg xm, Cond cond) +{ + emit<"11011010100mmmmmcccc00nnnnnddddd", "d", "n", "m", "c">(xd, xn, xm, cond); +} +void CSNEG(WReg wd, WReg wn, WReg wm, Cond cond) +{ + emit<"01011010100mmmmmcccc01nnnnnddddd", "d", "n", "m", "c">(wd, wn, wm, cond); +} +void CSNEG(XReg xd, XReg xn, XReg xm, Cond cond) +{ + emit<"11011010100mmmmmcccc01nnnnnddddd", "d", "n", "m", "c">(xd, xn, xm, cond); +} +void DC(DcOp op, XReg xt) +{ + emit<"1101010100001ooo0111MMMMooottttt", "oMo", "t">(op, xt); +} +void DCPS1(Imm<16> imm = 0) +{ + emit<"11010100101iiiiiiiiiiiiiiii00001", "i">(imm); +} +void DCPS2(Imm<16> imm = 0) +{ + emit<"11010100101iiiiiiiiiiiiiiii00010", "i">(imm); +} +void DMB(BarrierOp imm) +{ + emit<"11010101000000110011MMMM10111111", "M">(imm); +} +void DRPS() +{ + emit<"11010110101111110000001111100000">(); +} +void DSB(BarrierOp imm) +{ + emit<"11010101000000110011MMMM10011111", "M">(imm); +} +void EON(WReg wd, WReg wn, WReg wm, LogShift shift = LogShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"01001010ss1mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(wd, wn, wm, shift, shift_amount); +} +void EON(XReg xd, XReg xn, XReg xm, LogShift shift = LogShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"11001010ss1mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(xd, xn, xm, shift, shift_amount); +} +void EOR(WRegWsp wd, WReg wn, BitImm32 imm) +{ + emit<"0101001000rrrrrrssssssnnnnnddddd", "d", "n", "rs">(wd, wn, imm); +} +void EOR(XRegSp xd, XReg xn, BitImm64 imm) +{ + emit<"110100100Nrrrrrrssssssnnnnnddddd", "d", "n", "Nrs">(xd, xn, imm); +} +void EOR(WReg wd, WReg wn, WReg wm, LogShift shift = LogShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"01001010ss0mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(wd, wn, wm, shift, shift_amount); +} +void EOR(XReg xd, XReg xn, XReg xm, LogShift shift = LogShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"11001010ss0mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(xd, xn, xm, shift, shift_amount); +} +void ERET() +{ + emit<"11010110100111110000001111100000">(); +} +void EXTR(WReg wd, WReg wn, WReg wm, Imm<5> imms) +{ + emit<"00010011100mmmmm0sssssnnnnnddddd", "d", "n", "m", "s">(wd, wn, wm, imms); +} +void EXTR(XReg xd, XReg xn, XReg xm, Imm<6> imms) +{ + emit<"10010011110mmmmmssssssnnnnnddddd", "d", "n", "m", "s">(xd, xn, xm, imms); +} +void HINT(Imm<7> imm) +{ + emit<"11010101000000110010MMMMooo11111", "Mo">(imm); +} +void HLT(Imm<16> imm) +{ + emit<"11010100010iiiiiiiiiiiiiiii00000", "i">(imm); +} +void HVC(Imm<16> imm) +{ + emit<"11010100000iiiiiiiiiiiiiiii00010", "i">(imm); +} +void IC(IcOp op, XReg xt) +{ + emit<"1101010100001ooo0111MMMMooottttt", "oMo", "t">(op, xt); +} +void ISB(BarrierOp imm = BarrierOp::SY) +{ + emit<"11010101000000110011MMMM11011111", "M">(imm); +} +void LDAR(WReg wt, XRegSp xn) +{ + emit<"1000100011011111111111nnnnnttttt", "t", "n">(wt, xn); +} +void LDAR(XReg xt, XRegSp xn) +{ + emit<"1100100011011111111111nnnnnttttt", "t", "n">(xt, xn); +} +void LDARB(WReg wt, XRegSp xn) +{ + emit<"0000100011011111111111nnnnnttttt", "t", "n">(wt, xn); +} +void LDARH(WReg wt, XRegSp xn) +{ + emit<"0100100011011111111111nnnnnttttt", "t", "n">(wt, xn); +} +void LDAXP(WReg wt1, WReg wt2, XRegSp xn) +{ + emit<"10001000011111111uuuuunnnnnttttt", "t", "u", "n">(wt1, wt2, xn); +} +void LDAXP(XReg xt1, XReg xt2, XRegSp xn) +{ + emit<"11001000011111111uuuuunnnnnttttt", "t", "u", "n">(xt1, xt2, xn); +} +void LDAXR(WReg wt, XRegSp xn) +{ + emit<"1000100001011111111111nnnnnttttt", "t", "n">(wt, xn); +} +void LDAXR(XReg xt, XRegSp xn) +{ + emit<"1100100001011111111111nnnnnttttt", "t", "n">(xt, xn); +} +void LDAXRB(WReg wt, XRegSp xn) +{ + emit<"0000100001011111111111nnnnnttttt", "t", "n">(wt, xn); +} +void LDAXRH(WReg wt, XRegSp xn) +{ + emit<"0100100001011111111111nnnnnttttt", "t", "n">(wt, xn); +} +void LDNP(WReg wt1, WReg wt2, XRegSp xn, SOffset<9, 2> imm = 0) +{ + emit<"0010100001iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(wt1, wt2, xn, imm); +} +void LDNP(XReg xt1, XReg xt2, XRegSp xn, SOffset<10, 3> imm = 0) +{ + emit<"1010100001iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(xt1, xt2, xn, imm); +} +void LDP(WReg wt1, WReg wt2, XRegSp xn, PostIndexed, SOffset<9, 2> imm) +{ + emit<"0010100011iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(wt1, wt2, xn, imm); +} +void LDP(XReg xt1, XReg xt2, XRegSp xn, PostIndexed, SOffset<10, 3> imm) +{ + emit<"1010100011iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(xt1, xt2, xn, imm); +} +void LDP(WReg wt1, WReg wt2, XRegSp xn, PreIndexed, SOffset<9, 2> imm) +{ + emit<"0010100111iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(wt1, wt2, xn, imm); +} +void LDP(XReg xt1, XReg xt2, XRegSp xn, PreIndexed, SOffset<10, 3> imm) +{ + emit<"1010100111iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(xt1, xt2, xn, imm); +} +void LDP(WReg wt1, WReg wt2, XRegSp xn, SOffset<9, 2> imm = 0) +{ + emit<"0010100101iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(wt1, wt2, xn, imm); +} +void LDP(XReg xt1, XReg xt2, XRegSp xn, SOffset<10, 3> imm = 0) +{ + emit<"1010100101iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(xt1, xt2, xn, imm); +} +void LDPSW(XReg xt1, XReg xt2, XRegSp xn, PostIndexed, SOffset<9, 2> imm) +{ + emit<"0110100011iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(xt1, xt2, xn, imm); +} +void LDPSW(XReg xt1, XReg xt2, XRegSp xn, PreIndexed, SOffset<9, 2> imm) +{ + emit<"0110100111iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(xt1, xt2, xn, imm); +} +void LDPSW(XReg xt1, XReg xt2, XRegSp xn, SOffset<9, 2> imm = 0) +{ + emit<"0110100101iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(xt1, xt2, xn, imm); +} +void LDR(WReg wt, XRegSp xn, PostIndexed, SOffset<9, 0> simm) +{ + emit<"10111000010iiiiiiiii01nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDR(XReg xt, XRegSp xn, PostIndexed, SOffset<9, 0> simm) +{ + emit<"11111000010iiiiiiiii01nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void LDR(WReg wt, XRegSp xn, PreIndexed, SOffset<9, 0> simm) +{ + emit<"10111000010iiiiiiiii11nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDR(XReg xt, XRegSp xn, PreIndexed, SOffset<9, 0> simm) +{ + emit<"11111000010iiiiiiiii11nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void LDR(WReg wt, XRegSp xn, POffset<14, 2> pimm = 0) +{ + emit<"1011100101iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(wt, xn, pimm); +} +void LDR(XReg xt, XRegSp xn, POffset<15, 3> pimm = 0) +{ + emit<"1111100101iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(xt, xn, pimm); +} +void LDR(WReg wt, AddrOffset<21, 2> label) +{ + emit<"00011000iiiiiiiiiiiiiiiiiiittttt", "t", "i">(wt, label); +} +void LDR(XReg xt, AddrOffset<21, 2> label) +{ + emit<"01011000iiiiiiiiiiiiiiiiiiittttt", "t", "i">(xt, label); +} +void LDR(WReg wt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 2> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"10111000011mmmmmxxxS10nnnnnttttt", "t", "n", "m", "x", "S">(wt, xn, rm, ext, amount); +} +void LDR(XReg xt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 3> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"11111000011mmmmmxxxS10nnnnnttttt", "t", "n", "m", "x", "S">(xt, xn, rm, ext, amount); +} +void LDRB(WReg wt, XRegSp xn, PostIndexed, SOffset<9, 0> simm) +{ + emit<"00111000010iiiiiiiii01nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDRB(WReg wt, XRegSp xn, PreIndexed, SOffset<9, 0> simm) +{ + emit<"00111000010iiiiiiiii11nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDRB(WReg wt, XRegSp xn, POffset<12, 0> pimm = 0) +{ + emit<"0011100101iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(wt, xn, pimm); +} +void LDRB(WReg wt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 0> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"00111000011mmmmmxxxS10nnnnnttttt", "t", "n", "m", "x", "S">(wt, xn, rm, ext, amount); +} +void LDRH(WReg wt, XRegSp xn, PostIndexed, SOffset<9, 0> simm) +{ + emit<"01111000010iiiiiiiii01nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDRH(WReg wt, XRegSp xn, PreIndexed, SOffset<9, 0> simm) +{ + emit<"01111000010iiiiiiiii11nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDRH(WReg wt, XRegSp xn, POffset<13, 1> pimm = 0) +{ + emit<"0111100101iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(wt, xn, pimm); +} +void LDRH(WReg wt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 1> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"01111000011mmmmmxxxS10nnnnnttttt", "t", "n", "m", "x", "S">(wt, xn, rm, ext, amount); +} +void LDRSB(WReg wt, XRegSp xn, PostIndexed, SOffset<9, 0> simm) +{ + emit<"00111000110iiiiiiiii01nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDRSB(XReg xt, XRegSp xn, PostIndexed, SOffset<9, 0> simm) +{ + emit<"00111000100iiiiiiiii01nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void LDRSB(WReg wt, XRegSp xn, PreIndexed, SOffset<9, 0> simm) +{ + emit<"00111000110iiiiiiiii11nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDRSB(XReg xt, XRegSp xn, PreIndexed, SOffset<9, 0> simm) +{ + emit<"00111000100iiiiiiiii11nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void LDRSB(WReg wt, XRegSp xn, POffset<12, 0> pimm = 0) +{ + emit<"0011100111iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(wt, xn, pimm); +} +void LDRSB(XReg xt, XRegSp xn, POffset<12, 0> pimm = 0) +{ + emit<"0011100110iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(xt, xn, pimm); +} +void LDRSB(WReg wt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 0> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"00111000111mmmmmxxxS10nnnnnttttt", "t", "n", "m", "x", "S">(wt, xn, rm, ext, amount); +} +void LDRSB(WReg wt, XRegSp xn, XReg xm, ImmChoice<0, 0> amount = 0) +{ + emit<"00111000111mmmmm011S10nnnnnttttt", "t", "n", "m", "S">(wt, xn, xm, amount); +} +void LDRSB(XReg xt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 0> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"00111000101mmmmmxxxS10nnnnnttttt", "t", "n", "m", "x", "S">(xt, xn, rm, ext, amount); +} +void LDRSB(XReg xt, XRegSp xn, XReg xm, ImmChoice<0, 0> amount = 0) +{ + emit<"00111000101mmmmm011S10nnnnnttttt", "t", "n", "m", "S">(xt, xn, xm, amount); +} +void LDRSH(WReg wt, XRegSp xn, PostIndexed, SOffset<9, 0> simm) +{ + emit<"01111000110iiiiiiiii01nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDRSH(XReg xt, XRegSp xn, PostIndexed, SOffset<9, 0> simm) +{ + emit<"01111000100iiiiiiiii01nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void LDRSH(WReg wt, XRegSp xn, PreIndexed, SOffset<9, 0> simm) +{ + emit<"01111000110iiiiiiiii11nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDRSH(XReg xt, XRegSp xn, PreIndexed, SOffset<9, 0> simm) +{ + emit<"01111000100iiiiiiiii11nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void LDRSH(WReg wt, XRegSp xn, POffset<13, 1> pimm = 0) +{ + emit<"0111100111iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(wt, xn, pimm); +} +void LDRSH(XReg xt, XRegSp xn, POffset<13, 1> pimm = 0) +{ + emit<"0111100110iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(xt, xn, pimm); +} +void LDRSH(WReg wt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 1> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"01111000111mmmmmxxxS10nnnnnttttt", "t", "n", "m", "x", "S">(wt, xn, rm, ext, amount); +} +void LDRSH(XReg xt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 1> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"01111000101mmmmmxxxS10nnnnnttttt", "t", "n", "m", "x", "S">(xt, xn, rm, ext, amount); +} +void LDRSW(XReg xt, XRegSp xn, PostIndexed, SOffset<9, 0> simm) +{ + emit<"10111000100iiiiiiiii01nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void LDRSW(XReg xt, XRegSp xn, PreIndexed, SOffset<9, 0> simm) +{ + emit<"10111000100iiiiiiiii11nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void LDRSW(XReg xt, XRegSp xn, POffset<14, 2> pimm = 0) +{ + emit<"1011100110iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(xt, xn, pimm); +} +void LDRSW(XReg xt, AddrOffset<21, 2> label) +{ + emit<"10011000iiiiiiiiiiiiiiiiiiittttt", "t", "i">(xt, label); +} +void LDRSW(XReg xt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 2> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"10111000101mmmmmxxxS10nnnnnttttt", "t", "n", "m", "x", "S">(xt, xn, rm, ext, amount); +} +void LDTR(WReg wt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"10111000010iiiiiiiii10nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDTR(XReg xt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"11111000010iiiiiiiii10nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void LDTRB(WReg wt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"00111000010iiiiiiiii10nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDTRH(WReg wt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"01111000010iiiiiiiii10nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDTRSB(WReg wt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"00111000110iiiiiiiii10nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDTRSB(XReg xt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"00111000100iiiiiiiii10nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void LDTRSH(WReg wt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"01111000110iiiiiiiii10nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDTRSH(XReg xt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"01111000100iiiiiiiii10nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void LDTRSW(XReg xt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"10111000100iiiiiiiii10nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void LDUR(WReg wt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"10111000010iiiiiiiii00nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDUR(XReg xt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"11111000010iiiiiiiii00nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void LDURB(WReg wt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"00111000010iiiiiiiii00nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDURH(WReg wt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"01111000010iiiiiiiii00nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDURSB(WReg wt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"00111000110iiiiiiiii00nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDURSB(XReg xt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"00111000100iiiiiiiii00nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void LDURSH(WReg wt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"01111000110iiiiiiiii00nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void LDURSH(XReg xt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"01111000100iiiiiiiii00nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void LDURSW(XReg xt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"10111000100iiiiiiiii00nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void LDXP(WReg wt1, WReg wt2, XRegSp xn) +{ + emit<"10001000011111110uuuuunnnnnttttt", "t", "u", "n">(wt1, wt2, xn); +} +void LDXP(XReg xt1, XReg xt2, XRegSp xn) +{ + emit<"11001000011111110uuuuunnnnnttttt", "t", "u", "n">(xt1, xt2, xn); +} +void LDXR(WReg wt, XRegSp xn) +{ + emit<"1000100001011111011111nnnnnttttt", "t", "n">(wt, xn); +} +void LDXR(XReg xt, XRegSp xn) +{ + emit<"1100100001011111011111nnnnnttttt", "t", "n">(xt, xn); +} +void LDXRB(WReg wt, XRegSp xn) +{ + emit<"0000100001011111011111nnnnnttttt", "t", "n">(wt, xn); +} +void LDXRH(WReg wt, XRegSp xn) +{ + emit<"0100100001011111011111nnnnnttttt", "t", "n">(wt, xn); +} +void LSL(WReg wd, WReg wn, LslShift<32> shift_amount) +{ + emit<"0101001100rrrrrrssssssnnnnnddddd", "d", "n", "rs">(wd, wn, shift_amount); +} +void LSL(XReg xd, XReg xn, LslShift<64> shift_amount) +{ + emit<"1101001101rrrrrrssssssnnnnnddddd", "d", "n", "rs">(xd, xn, shift_amount); +} +void LSL(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010110mmmmm001000nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void LSL(XReg xd, XReg xn, XReg xm) +{ + emit<"10011010110mmmmm001000nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void LSLV(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010110mmmmm001000nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void LSLV(XReg xd, XReg xn, XReg xm) +{ + emit<"10011010110mmmmm001000nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void LSR(WReg wd, WReg wn, Imm<5> shift_amount) +{ + emit<"0101001100rrrrrr011111nnnnnddddd", "d", "n", "r">(wd, wn, shift_amount); +} +void LSR(XReg xd, XReg xn, Imm<6> shift_amount) +{ + emit<"1101001101rrrrrr111111nnnnnddddd", "d", "n", "r">(xd, xn, shift_amount); +} +void LSR(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010110mmmmm001001nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void LSR(XReg xd, XReg xn, XReg xm) +{ + emit<"10011010110mmmmm001001nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void LSRV(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010110mmmmm001001nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void LSRV(XReg xd, XReg xn, XReg xm) +{ + emit<"10011010110mmmmm001001nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void MADD(WReg wd, WReg wn, WReg wm, WReg wa) +{ + emit<"00011011000mmmmm0aaaaannnnnddddd", "d", "n", "m", "a">(wd, wn, wm, wa); +} +void MADD(XReg xd, XReg xn, XReg xm, XReg xa) +{ + emit<"10011011000mmmmm0aaaaannnnnddddd", "d", "n", "m", "a">(xd, xn, xm, xa); +} +void MNEG(WReg wd, WReg wn, WReg wm) +{ + emit<"00011011000mmmmm111111nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void MNEG(XReg xd, XReg xn, XReg xm) +{ + emit<"10011011000mmmmm111111nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void MOV(WReg wd, WReg wm) +{ + emit<"00101010000mmmmm00000011111ddddd", "d", "m">(wd, wm); +} +void MOV(XReg xd, XReg xm) +{ + emit<"10101010000mmmmm00000011111ddddd", "d", "m">(xd, xm); +} +void MOV(WRegWsp wd, WRegWsp wn) +{ + emit<"0001000100000000000000nnnnnddddd", "d", "n">(wd, wn); +} +void MOV(XRegSp xd, XRegSp xn) +{ + emit<"1001000100000000000000nnnnnddddd", "d", "n">(xd, xn); +} +void MOVK(WReg wd, MovImm16 imm) +{ + emit<"0111001010hiiiiiiiiiiiiiiiiddddd", "d", "hi">(wd, imm); +} +void MOVK(XReg xd, MovImm16 imm) +{ + emit<"111100101hhiiiiiiiiiiiiiiiiddddd", "d", "hi">(xd, imm); +} +void MOVN(WReg wd, MovImm16 imm) +{ + emit<"0001001010hiiiiiiiiiiiiiiiiddddd", "d", "hi">(wd, imm); +} +void MOVN(XReg xd, MovImm16 imm) +{ + emit<"100100101hhiiiiiiiiiiiiiiiiddddd", "d", "hi">(xd, imm); +} +void MOVZ(WReg wd, MovImm16 imm) +{ + emit<"0101001010hiiiiiiiiiiiiiiiiddddd", "d", "hi">(wd, imm); +} +void MOVZ(XReg xd, MovImm16 imm) +{ + emit<"110100101hhiiiiiiiiiiiiiiiiddddd", "d", "hi">(xd, imm); +} +void MRS(XReg xt, SystemReg systemreg) +{ + emit<"110101010011ooooNNNNMMMMooottttt", "t", "oNMo">(xt, systemreg); +} +void MSR(PstateField pstatefield, Imm<4> imm) +{ + emit<"1101010100000ooo0100MMMMooo11111", "o", "M">(pstatefield, imm); +} +void MSR(SystemReg systemreg, XReg xt) +{ + emit<"110101010001ooooNNNNMMMMooottttt", "oNMo", "t">(systemreg, xt); +} +void MSUB(WReg wd, WReg wn, WReg wm, WReg wa) +{ + emit<"00011011000mmmmm1aaaaannnnnddddd", "d", "n", "m", "a">(wd, wn, wm, wa); +} +void MSUB(XReg xd, XReg xn, XReg xm, XReg xa) +{ + emit<"10011011000mmmmm1aaaaannnnnddddd", "d", "n", "m", "a">(xd, xn, xm, xa); +} +void MUL(WReg wd, WReg wn, WReg wm) +{ + emit<"00011011000mmmmm011111nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void MUL(XReg xd, XReg xn, XReg xm) +{ + emit<"10011011000mmmmm011111nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void MVN(WReg wd, WReg wm, LogShift shift = LogShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"00101010ss1mmmmmiiiiii11111ddddd", "d", "m", "s", "i">(wd, wm, shift, shift_amount); +} +void MVN(XReg xd, XReg xm, LogShift shift = LogShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"10101010ss1mmmmmiiiiii11111ddddd", "d", "m", "s", "i">(xd, xm, shift, shift_amount); +} +void NEG(WReg wd, WReg wm, AddSubShift shift = AddSubShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"01001011ss0mmmmmiiiiii11111ddddd", "d", "m", "s", "i">(wd, wm, shift, shift_amount); +} +void NEG(XReg xd, XReg xm, AddSubShift shift = AddSubShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"11001011ss0mmmmmiiiiii11111ddddd", "d", "m", "s", "i">(xd, xm, shift, shift_amount); +} +void NEGS(WReg wd, WReg wm, AddSubShift shift = AddSubShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"01101011ss0mmmmmiiiiii11111ddddd", "d", "m", "s", "i">(wd, wm, shift, shift_amount); +} +void NEGS(XReg xd, XReg xm, AddSubShift shift = AddSubShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"11101011ss0mmmmmiiiiii11111ddddd", "d", "m", "s", "i">(xd, xm, shift, shift_amount); +} +void NGC(WReg wd, WReg wm) +{ + emit<"01011010000mmmmm00000011111ddddd", "d", "m">(wd, wm); +} +void NGC(XReg xd, XReg xm) +{ + emit<"11011010000mmmmm00000011111ddddd", "d", "m">(xd, xm); +} +void NGCS(WReg wd, WReg wm) +{ + emit<"01111010000mmmmm00000011111ddddd", "d", "m">(wd, wm); +} +void NGCS(XReg xd, XReg xm) +{ + emit<"11111010000mmmmm00000011111ddddd", "d", "m">(xd, xm); +} +void NOP() +{ + emit<"11010101000000110010000000011111">(); +} +void ORN(WReg wd, WReg wn, WReg wm, LogShift shift = LogShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"00101010ss1mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(wd, wn, wm, shift, shift_amount); +} +void ORN(XReg xd, XReg xn, XReg xm, LogShift shift = LogShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"10101010ss1mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(xd, xn, xm, shift, shift_amount); +} +void ORR(WRegWsp wd, WReg wn, BitImm32 imm) +{ + emit<"0011001000rrrrrrssssssnnnnnddddd", "d", "n", "rs">(wd, wn, imm); +} +void ORR(XRegSp xd, XReg xn, BitImm64 imm) +{ + emit<"101100100Nrrrrrrssssssnnnnnddddd", "d", "n", "Nrs">(xd, xn, imm); +} +void ORR(WReg wd, WReg wn, WReg wm, LogShift shift = LogShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"00101010ss0mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(wd, wn, wm, shift, shift_amount); +} +void ORR(XReg xd, XReg xn, XReg xm, LogShift shift = LogShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"10101010ss0mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(xd, xn, xm, shift, shift_amount); +} +void PRFM(PrfOp prfop, XRegSp xn, POffset<15, 3> pimm = 0) +{ + emit<"1111100110iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(prfop, xn, pimm); +} +void PRFM(PrfOp prfop, AddrOffset<21, 2> label) +{ + emit<"11011000iiiiiiiiiiiiiiiiiiittttt", "t", "i">(prfop, label); +} +void PRFM(PrfOp prfop, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 3> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"11111000101mmmmmxxxS10nnnnnttttt", "t", "n", "m", "x", "S">(prfop, xn, rm, ext, amount); +} +void PRFUM(PrfOp prfop, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"11111000100iiiiiiiii00nnnnnttttt", "t", "n", "i">(prfop, xn, simm); +} +void PSSBB() +{ + emit<"11010101000000110011010010011111">(); +} +void RBIT(WReg wd, WReg wn) +{ + emit<"0101101011000000000000nnnnnddddd", "d", "n">(wd, wn); +} +void RBIT(XReg xd, XReg xn) +{ + emit<"1101101011000000000000nnnnnddddd", "d", "n">(xd, xn); +} +void RET(XReg xn) +{ + emit<"1101011001011111000000nnnnn00000", "n">(xn); +} +void REV(WReg wd, WReg wn) +{ + emit<"0101101011000000000010nnnnnddddd", "d", "n">(wd, wn); +} +void REV(XReg xd, XReg xn) +{ + emit<"1101101011000000000011nnnnnddddd", "d", "n">(xd, xn); +} +void REV16(WReg wd, WReg wn) +{ + emit<"0101101011000000000001nnnnnddddd", "d", "n">(wd, wn); +} +void REV16(XReg xd, XReg xn) +{ + emit<"1101101011000000000001nnnnnddddd", "d", "n">(xd, xn); +} +void REV32(XReg xd, XReg xn) +{ + emit<"1101101011000000000010nnnnnddddd", "d", "n">(xd, xn); +} +void REV64(XReg xd, XReg xn) +{ + emit<"1101101011000000000011nnnnnddddd", "d", "n">(xd, xn); +} +void ROR(WReg wd, WReg ws, Imm<5> shift_amount) +{ + emit<"00010011100mmmmm0sssssnnnnnddddd", "d", "n", "m", "s">(wd, ws, ws, shift_amount); +} +void ROR(XReg xd, XReg xs, Imm<6> shift_amount) +{ + emit<"10010011110mmmmmssssssnnnnnddddd", "d", "n", "m", "s">(xd, xs, xs, shift_amount); +} +void ROR(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010110mmmmm001011nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void ROR(XReg xd, XReg xn, XReg xm) +{ + emit<"10011010110mmmmm001011nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void RORV(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010110mmmmm001011nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void RORV(XReg xd, XReg xn, XReg xm) +{ + emit<"10011010110mmmmm001011nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void SB() +{ + emit<"11010101000000110011000011111111">(); +} +void SBC(WReg wd, WReg wn, WReg wm) +{ + emit<"01011010000mmmmm000000nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void SBC(XReg xd, XReg xn, XReg xm) +{ + emit<"11011010000mmmmm000000nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void SBCS(WReg wd, WReg wn, WReg wm) +{ + emit<"01111010000mmmmm000000nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void SBCS(XReg xd, XReg xn, XReg xm) +{ + emit<"11111010000mmmmm000000nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void SBFIZ(WReg wd, WReg wn, Imm<5> lsb, Imm<5> width) +{ + if (width.value() == 0 || width.value() > (32 - lsb.value())) + throw "invalid width"; + emit<"0001001100rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(wd, wn, (-lsb.value()) & 31, width.value() - 1); +} +void SBFIZ(XReg xd, XReg xn, Imm<6> lsb, Imm<6> width) +{ + if (width.value() == 0 || width.value() > (64 - lsb.value())) + throw "invalid width"; + emit<"1001001101rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(xd, xn, (-lsb.value()) & 63, width.value() - 1); +} +void SBFM(WReg wd, WReg wn, Imm<5> immr, Imm<5> imms) +{ + emit<"0001001100rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(wd, wn, immr, imms); +} +void SBFM(XReg xd, XReg xn, Imm<6> immr, Imm<6> imms) +{ + emit<"1001001101rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(xd, xn, immr, imms); +} +void SBFX(WReg wd, WReg wn, Imm<5> lsb, Imm<5> width) +{ + if (width.value() == 0 || width.value() > (32 - lsb.value())) + throw "invalid width"; + emit<"0001001100rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(wd, wn, lsb.value(), lsb.value() + width.value() - 1); +} +void SBFX(XReg xd, XReg xn, Imm<6> lsb, Imm<6> width) +{ + if (width.value() == 0 || width.value() > (64 - lsb.value())) + throw "invalid width"; + emit<"1001001101rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(xd, xn, lsb.value(), lsb.value() + width.value() - 1); +} +void SDIV(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010110mmmmm000011nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void SDIV(XReg xd, XReg xn, XReg xm) +{ + emit<"10011010110mmmmm000011nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void SEV() +{ + emit<"11010101000000110010000010011111">(); +} +void SEVL() +{ + emit<"11010101000000110010000010111111">(); +} +void SMADDL(XReg xd, WReg wn, WReg wm, XReg xa) +{ + emit<"10011011001mmmmm0aaaaannnnnddddd", "d", "n", "m", "a">(xd, wn, wm, xa); +} +void SMNEGL(XReg xd, WReg wn, WReg wm) +{ + emit<"10011011001mmmmm111111nnnnnddddd", "d", "n", "m">(xd, wn, wm); +} +void SMSUBL(XReg xd, WReg wn, WReg wm, XReg xa) +{ + emit<"10011011001mmmmm1aaaaannnnnddddd", "d", "n", "m", "a">(xd, wn, wm, xa); +} +void SMULH(XReg xd, XReg xn, XReg xm) +{ + emit<"10011011010mmmmm011111nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void SMULL(XReg xd, WReg wn, WReg wm) +{ + emit<"10011011001mmmmm011111nnnnnddddd", "d", "n", "m">(xd, wn, wm); +} +void SSBB() +{ + emit<"11010101000000110011000010011111">(); +} +void STLR(WReg wt, XRegSp xn) +{ + emit<"1000100010011111111111nnnnnttttt", "t", "n">(wt, xn); +} +void STLR(XReg xt, XRegSp xn) +{ + emit<"1100100010011111111111nnnnnttttt", "t", "n">(xt, xn); +} +void STLRB(WReg wt, XRegSp xn) +{ + emit<"0000100010011111111111nnnnnttttt", "t", "n">(wt, xn); +} +void STLRH(WReg wt, XRegSp xn) +{ + emit<"0100100010011111111111nnnnnttttt", "t", "n">(wt, xn); +} +void STLXP(WReg ws, WReg wt1, WReg wt2, XRegSp xn) +{ + emit<"10001000001sssss1uuuuunnnnnttttt", "s", "t", "u", "n">(ws, wt1, wt2, xn); +} +void STLXP(WReg ws, XReg xt1, XReg xt2, XRegSp xn) +{ + emit<"11001000001sssss1uuuuunnnnnttttt", "s", "t", "u", "n">(ws, xt1, xt2, xn); +} +void STLXR(WReg ws, WReg wt, XRegSp xn) +{ + emit<"10001000000sssss111111nnnnnttttt", "s", "t", "n">(ws, wt, xn); +} +void STLXR(WReg ws, XReg xt, XRegSp xn) +{ + emit<"11001000000sssss111111nnnnnttttt", "s", "t", "n">(ws, xt, xn); +} +void STLXRB(WReg ws, WReg wt, XRegSp xn) +{ + emit<"00001000000sssss111111nnnnnttttt", "s", "t", "n">(ws, wt, xn); +} +void STLXRH(WReg ws, WReg wt, XRegSp xn) +{ + emit<"01001000000sssss111111nnnnnttttt", "s", "t", "n">(ws, wt, xn); +} +void STNP(WReg wt1, WReg wt2, XRegSp xn, SOffset<9, 2> imm = 0) +{ + emit<"0010100000iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(wt1, wt2, xn, imm); +} +void STNP(XReg xt1, XReg xt2, XRegSp xn, SOffset<10, 3> imm = 0) +{ + emit<"1010100000iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(xt1, xt2, xn, imm); +} +void STP(WReg wt1, WReg wt2, XRegSp xn, PostIndexed, SOffset<9, 2> imm) +{ + emit<"0010100010iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(wt1, wt2, xn, imm); +} +void STP(XReg xt1, XReg xt2, XRegSp xn, PostIndexed, SOffset<10, 3> imm) +{ + emit<"1010100010iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(xt1, xt2, xn, imm); +} +void STP(WReg wt1, WReg wt2, XRegSp xn, PreIndexed, SOffset<9, 2> imm) +{ + emit<"0010100110iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(wt1, wt2, xn, imm); +} +void STP(XReg xt1, XReg xt2, XRegSp xn, PreIndexed, SOffset<10, 3> imm) +{ + emit<"1010100110iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(xt1, xt2, xn, imm); +} +void STP(WReg wt1, WReg wt2, XRegSp xn, SOffset<9, 2> imm = 0) +{ + emit<"0010100100iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(wt1, wt2, xn, imm); +} +void STP(XReg xt1, XReg xt2, XRegSp xn, SOffset<10, 3> imm = 0) +{ + emit<"1010100100iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(xt1, xt2, xn, imm); +} +void STR(WReg wt, XRegSp xn, PostIndexed, SOffset<9, 0> simm) +{ + emit<"10111000000iiiiiiiii01nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void STR(XReg xt, XRegSp xn, PostIndexed, SOffset<9, 0> simm) +{ + emit<"11111000000iiiiiiiii01nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void STR(WReg wt, XRegSp xn, PreIndexed, SOffset<9, 0> simm) +{ + emit<"10111000000iiiiiiiii11nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void STR(XReg xt, XRegSp xn, PreIndexed, SOffset<9, 0> simm) +{ + emit<"11111000000iiiiiiiii11nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void STR(WReg wt, XRegSp xn, POffset<14, 2> pimm = 0) +{ + emit<"1011100100iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(wt, xn, pimm); +} +void STR(XReg xt, XRegSp xn, POffset<15, 3> pimm = 0) +{ + emit<"1111100100iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(xt, xn, pimm); +} +void STR(WReg wt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 2> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"10111000001mmmmmxxxS10nnnnnttttt", "t", "n", "m", "x", "S">(wt, xn, rm, ext, amount); +} +void STR(XReg xt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 3> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"11111000001mmmmmxxxS10nnnnnttttt", "t", "n", "m", "x", "S">(xt, xn, rm, ext, amount); +} +void STRB(WReg wt, XRegSp xn, PostIndexed, SOffset<9, 0> simm) +{ + emit<"00111000000iiiiiiiii01nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void STRB(WReg wt, XRegSp xn, PreIndexed, SOffset<9, 0> simm) +{ + emit<"00111000000iiiiiiiii11nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void STRB(WReg wt, XRegSp xn, POffset<12, 0> pimm = 0) +{ + emit<"0011100100iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(wt, xn, pimm); +} +void STRB(WReg wt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 0> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"00111000001mmmmmxxxS10nnnnnttttt", "t", "n", "m", "x", "S">(wt, xn, rm, ext, amount); +} +void STRB(WReg wt, XRegSp xn, XReg xm, ImmChoice<0, 0> amount = 0) +{ + emit<"00111000001mmmmm011S10nnnnnttttt", "t", "n", "m", "S">(wt, xn, xm, amount); +} +void STRH(WReg wt, XRegSp xn, PostIndexed, SOffset<9, 0> simm) +{ + emit<"01111000000iiiiiiiii01nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void STRH(WReg wt, XRegSp xn, PreIndexed, SOffset<9, 0> simm) +{ + emit<"01111000000iiiiiiiii11nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void STRH(WReg wt, XRegSp xn, POffset<13, 1> pimm = 0) +{ + emit<"0111100100iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(wt, xn, pimm); +} +void STRH(WReg wt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 1> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"01111000001mmmmmxxxS10nnnnnttttt", "t", "n", "m", "x", "S">(wt, xn, rm, ext, amount); +} +void STTR(WReg wt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"10111000000iiiiiiiii10nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void STTR(XReg xt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"11111000000iiiiiiiii10nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void STTRB(WReg wt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"00111000000iiiiiiiii10nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void STTRH(WReg wt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"01111000000iiiiiiiii10nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void STUR(WReg wt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"10111000000iiiiiiiii00nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void STUR(XReg xt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"11111000000iiiiiiiii00nnnnnttttt", "t", "n", "i">(xt, xn, simm); +} +void STURB(WReg wt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"00111000000iiiiiiiii00nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void STURH(WReg wt, XRegSp xn, SOffset<9, 0> simm = 0) +{ + emit<"01111000000iiiiiiiii00nnnnnttttt", "t", "n", "i">(wt, xn, simm); +} +void STXP(WReg ws, WReg wt1, WReg wt2, XRegSp xn) +{ + emit<"10001000001sssss0uuuuunnnnnttttt", "s", "t", "u", "n">(ws, wt1, wt2, xn); +} +void STXP(WReg ws, XReg xt1, XReg xt2, XRegSp xn) +{ + emit<"11001000001sssss0uuuuunnnnnttttt", "s", "t", "u", "n">(ws, xt1, xt2, xn); +} +void STXR(WReg ws, WReg wt, XRegSp xn) +{ + emit<"10001000000sssss011111nnnnnttttt", "s", "t", "n">(ws, wt, xn); +} +void STXR(WReg ws, XReg xt, XRegSp xn) +{ + emit<"11001000000sssss011111nnnnnttttt", "s", "t", "n">(ws, xt, xn); +} +void STXRB(WReg ws, WReg wt, XRegSp xn) +{ + emit<"00001000000sssss011111nnnnnttttt", "s", "t", "n">(ws, wt, xn); +} +void STXRH(WReg ws, WReg wt, XRegSp xn) +{ + emit<"01001000000sssss011111nnnnnttttt", "s", "t", "n">(ws, wt, xn); +} +void SUB(WRegWsp wd, WRegWsp wn, WReg wm, AddSubExt ext = AddSubExt::LSL, Imm<3> shift_amount = 0) +{ + addsubext_lsl_correction(ext, wd); + emit<"01001011001mmmmmxxxiiinnnnnddddd", "d", "n", "m", "x", "i">(wd, wn, wm, ext, shift_amount); +} +void SUB(XRegSp xd, XRegSp xn, RReg rm, AddSubExt ext = AddSubExt::LSL, Imm<3> shift_amount = 0) +{ + addsubext_lsl_correction(ext, xd); + addsubext_verify_reg_size(ext, rm); + emit<"11001011001mmmmmxxxiiinnnnnddddd", "d", "n", "m", "x", "i">(xd, xn, rm, ext, shift_amount); +} +void SUB(WRegWsp wd, WRegWsp wn, AddSubImm imm) +{ + emit<"010100010siiiiiiiiiiiinnnnnddddd", "d", "n", "si">(wd, wn, imm); +} +void SUB(WRegWsp wd, WRegWsp wn, Imm<12> imm, LslSymbol, ImmChoice<0, 12> shift_amount) +{ + SUB(wd, wn, AddSubImm{imm.value(), static_cast(shift_amount.m_encoded)}); +} +void SUB(XRegSp xd, XRegSp xn, AddSubImm imm) +{ + emit<"110100010siiiiiiiiiiiinnnnnddddd", "d", "n", "si">(xd, xn, imm); +} +void SUB(XRegSp xd, XRegSp xn, Imm<12> imm, LslSymbol, ImmChoice<0, 12> shift_amount) +{ + SUB(xd, xn, AddSubImm{imm.value(), static_cast(shift_amount.m_encoded)}); +} +void SUB(WReg wd, WReg wn, WReg wm, AddSubShift shift = AddSubShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"01001011ss0mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(wd, wn, wm, shift, shift_amount); +} +void SUB(XReg xd, XReg xn, XReg xm, AddSubShift shift = AddSubShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"11001011ss0mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(xd, xn, xm, shift, shift_amount); +} +void SUBS(WReg wd, WRegWsp wn, WReg wm, AddSubExt ext = AddSubExt::LSL, Imm<3> shift_amount = 0) +{ + addsubext_lsl_correction(ext, wd); + emit<"01101011001mmmmmxxxiiinnnnnddddd", "d", "n", "m", "x", "i">(wd, wn, wm, ext, shift_amount); +} +void SUBS(XReg xd, XRegSp xn, RReg rm, AddSubExt ext = AddSubExt::LSL, Imm<3> shift_amount = 0) +{ + addsubext_lsl_correction(ext, xd); + addsubext_verify_reg_size(ext, rm); + emit<"11101011001mmmmmxxxiiinnnnnddddd", "d", "n", "m", "x", "i">(xd, xn, rm, ext, shift_amount); +} +void SUBS(WReg wd, WRegWsp wn, AddSubImm imm) +{ + emit<"011100010siiiiiiiiiiiinnnnnddddd", "d", "n", "si">(wd, wn, imm); +} +void SUBS(WReg wd, WRegWsp wn, Imm<12> imm, LslSymbol, ImmChoice<0, 12> shift_amount) +{ + SUBS(wd, wn, AddSubImm{imm.value(), static_cast(shift_amount.m_encoded)}); +} +void SUBS(XReg xd, XRegSp xn, AddSubImm imm) +{ + emit<"111100010siiiiiiiiiiiinnnnnddddd", "d", "n", "si">(xd, xn, imm); +} +void SUBS(XReg xd, XRegSp xn, Imm<12> imm, LslSymbol, ImmChoice<0, 12> shift_amount) +{ + SUBS(xd, xn, AddSubImm{imm.value(), static_cast(shift_amount.m_encoded)}); +} +void SUBS(WReg wd, WReg wn, WReg wm, AddSubShift shift = AddSubShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"01101011ss0mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(wd, wn, wm, shift, shift_amount); +} +void SUBS(XReg xd, XReg xn, XReg xm, AddSubShift shift = AddSubShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"11101011ss0mmmmmiiiiiinnnnnddddd", "d", "n", "m", "s", "i">(xd, xn, xm, shift, shift_amount); +} +void SVC(Imm<16> imm) +{ + emit<"11010100000iiiiiiiiiiiiiiii00001", "i">(imm); +} +void SXTB(WReg wd, WReg wn) +{ + emit<"0001001100000000000111nnnnnddddd", "d", "n">(wd, wn); +} +void SXTB(XReg xd, WReg wn) +{ + emit<"1001001101000000000111nnnnnddddd", "d", "n">(xd, wn); +} +void SXTH(WReg wd, WReg wn) +{ + emit<"0001001100000000001111nnnnnddddd", "d", "n">(wd, wn); +} +void SXTH(XReg xd, WReg wn) +{ + emit<"1001001101000000001111nnnnnddddd", "d", "n">(xd, wn); +} +void SXTW(XReg xd, WReg wn) +{ + emit<"1001001101000000011111nnnnnddddd", "d", "n">(xd, wn); +} +void TBNZ(RReg rt, Imm<6> imm, AddrOffset<16, 2> label) +{ + tbz_verify_reg_size(rt, imm); + emit<"b0110111bbbbbiiiiiiiiiiiiiittttt", "t", "b", "i">(rt, imm, label); +} +void TBZ(RReg rt, Imm<6> imm, AddrOffset<16, 2> label) +{ + tbz_verify_reg_size(rt, imm); + emit<"b0110110bbbbbiiiiiiiiiiiiiittttt", "t", "b", "i">(rt, imm, label); +} +void TLBI(TlbiOp op, XReg xt) +{ + emit<"1101010100001ooo1000MMMMooottttt", "oMo", "t">(op, xt); +} +void TST(WReg wn, BitImm32 imm) +{ + emit<"0111001000rrrrrrssssssnnnnn11111", "n", "rs">(wn, imm); +} +void TST(XReg xn, BitImm64 imm) +{ + emit<"111100100Nrrrrrrssssssnnnnn11111", "n", "Nrs">(xn, imm); +} +void TST(WReg wn, WReg wm, LogShift shift = LogShift::LSL, Imm<5> shift_amount = 0) +{ + emit<"01101010ss0mmmmmiiiiiinnnnn11111", "n", "m", "s", "i">(wn, wm, shift, shift_amount); +} +void TST(XReg xn, XReg xm, LogShift shift = LogShift::LSL, Imm<6> shift_amount = 0) +{ + emit<"11101010ss0mmmmmiiiiiinnnnn11111", "n", "m", "s", "i">(xn, xm, shift, shift_amount); +} +void UBFIZ(WReg wd, WReg wn, Imm<5> lsb, Imm<5> width) +{ + if (width.value() == 0 || width.value() > (32 - lsb.value())) + throw "invalid width"; + emit<"0101001100rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(wd, wn, (-lsb.value()) & 31, width.value() - 1); +} +void UBFIZ(XReg xd, XReg xn, Imm<6> lsb, Imm<6> width) +{ + if (width.value() == 0 || width.value() > (64 - lsb.value())) + throw "invalid width"; + emit<"1101001101rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(xd, xn, (-lsb.value()) & 63, width.value() - 1); +} +void UBFM(WReg wd, WReg wn, Imm<5> immr, Imm<5> imms) +{ + emit<"0101001100rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(wd, wn, immr, imms); +} +void UBFM(XReg xd, XReg xn, Imm<6> immr, Imm<6> imms) +{ + emit<"1101001101rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(xd, xn, immr, imms); +} +void UBFX(WReg wd, WReg wn, Imm<5> lsb, Imm<5> width) +{ + if (width.value() == 0 || width.value() > (32 - lsb.value())) + throw "invalid width"; + emit<"0101001100rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(wd, wn, lsb.value(), lsb.value() + width.value() - 1); +} +void UBFX(XReg xd, XReg xn, Imm<6> lsb, Imm<6> width) +{ + if (width.value() == 0 || width.value() > (64 - lsb.value())) + throw "invalid width"; + emit<"1101001101rrrrrrssssssnnnnnddddd", "d", "n", "r", "s">(xd, xn, lsb.value(), lsb.value() + width.value() - 1); +} +void UDF(Imm<16> imm) +{ + emit<"0000000000000000iiiiiiiiiiiiiiii", "i">(imm); +} +void UDIV(WReg wd, WReg wn, WReg wm) +{ + emit<"00011010110mmmmm000010nnnnnddddd", "d", "n", "m">(wd, wn, wm); +} +void UDIV(XReg xd, XReg xn, XReg xm) +{ + emit<"10011010110mmmmm000010nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void UMADDL(XReg xd, WReg wn, WReg wm, XReg xa) +{ + emit<"10011011101mmmmm0aaaaannnnnddddd", "d", "n", "m", "a">(xd, wn, wm, xa); +} +void UMNEGL(XReg xd, WReg wn, WReg wm) +{ + emit<"10011011101mmmmm111111nnnnnddddd", "d", "n", "m">(xd, wn, wm); +} +void UMSUBL(XReg xd, WReg wn, WReg wm, XReg xa) +{ + emit<"10011011101mmmmm1aaaaannnnnddddd", "d", "n", "m", "a">(xd, wn, wm, xa); +} +void UMULH(XReg xd, XReg xn, XReg xm) +{ + emit<"10011011110mmmmm011111nnnnnddddd", "d", "n", "m">(xd, xn, xm); +} +void UMULL(XReg xd, WReg wn, WReg wm) +{ + emit<"10011011101mmmmm011111nnnnnddddd", "d", "n", "m">(xd, wn, wm); +} +void UXTB(WReg wd, WReg wn) +{ + emit<"0101001100000000000111nnnnnddddd", "d", "n">(wd, wn); +} +void UXTH(WReg wd, WReg wn) +{ + emit<"0101001100000000001111nnnnnddddd", "d", "n">(wd, wn); +} +void WFE() +{ + emit<"11010101000000110010000001011111">(); +} +void WFI() +{ + emit<"11010101000000110010000001111111">(); +} +void YIELD() +{ + emit<"11010101000000110010000000111111">(); +} diff --git a/include/oaknut/impl/enum.hpp b/include/oaknut/impl/enum.hpp new file mode 100644 index 00000000..95a55dfc --- /dev/null +++ b/include/oaknut/impl/enum.hpp @@ -0,0 +1,242 @@ +// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime +// SPDX-License-Identifier: MIT + +#pragma once + +namespace oaknut { + +struct PostIndexed {}; + +struct PreIndexed {}; + +enum class LslSymbol { + LSL, +}; + +enum class MslSymbol { + MSL, +}; + +enum class Cond { + EQ, + NE, + CS, + CC, + MI, + PL, + VS, + VC, + HI, + LS, + GE, + LT, + GT, + LE, + AL, + NV, + HS = CS, + LO = CC, +}; + +constexpr Cond invert(Cond c) +{ + return static_cast(static_cast(c) ^ 1); +} + +enum class AddSubExt { + UXTB, + UXTH, + UXTW, + UXTX, + SXTB, + SXTH, + SXTW, + SXTX, + LSL, // UXTW (32-bit) or UXTX (64-bit) +}; + +enum class IndexExt { + UXTW = 0b010, + LSL = 0b011, + SXTW = 0b110, + SXTX = 0b111, +}; + +enum class AddSubShift { + LSL, + LSR, + ASR, +}; + +enum class LogShift { + LSL, + LSR, + ASR, + ROR, +}; + +enum class PstateField { + UAO = 0b000'011, // ARMv8.2-UAO + PAN = 0b000'100, // ARMv8.1-PAN + SPSel = 0b000'101, + DIT = 0b011'010, // ARMv8.4-DIT + DAIFSet = 0b011'110, + DAIFClr = 0b011'111, +}; + +enum class SystemReg { +}; + +enum class AtOp { + S1E1R = 0b000'0'000, + S1E1W = 0b000'0'001, + S1E0R = 0b000'0'010, + S1E0W = 0b000'0'011, + S1E1RP = 0b000'1'000, // ARMv8.2-ATS1E1 + S1E1WP = 0b000'1'001, // ARMv8.2-ATS1E1 + S1E2R = 0b100'0'000, + S1E2W = 0b100'0'001, + S12E1R = 0b100'0'100, + S12E1W = 0b100'0'101, + S12E0R = 0b100'0'110, + S12E0W = 0b100'0'111, + S1E3R = 0b110'0'000, + S1E3W = 0b110'0'001, +}; + +enum class BarrierOp { + SY = 0b1111, + ST = 0b1110, + LD = 0b1101, + ISH = 0b1011, + ISHST = 0b1010, + ISHLD = 0b1001, + NSH = 0b0111, + NSHST = 0b0110, + NSHLD = 0b0101, + OSH = 0b0011, + OSHST = 0b0010, + OSHLD = 0b0001, +}; + +enum class DcOp { + IVAC = 0b000'0110'001, + ISW = 0b000'0110'010, + CSW = 0b000'1010'010, + CISW = 0b000'1110'010, + ZVA = 0b011'0100'001, + CVAC = 0b011'1010'001, + CVAU = 0b011'1011'001, + CVAP = 0b011'1100'001, // ARMv8.2-DCPoP + CIVAC = 0b011'1110'001, +}; + +enum class IcOp { + IALLUIS = 0b000'0001'000, + IALLU = 0b000'0101'000, + IVAU = 0b011'0101'001, +}; + +enum class PrfOp { + PLDL1KEEP = 0b00'00'0, + PLDL1STRM = 0b00'00'1, + PLDL2KEEP = 0b00'01'0, + PLDL2STRM = 0b00'01'1, + PLDL3KEEP = 0b00'10'0, + PLDL3STRM = 0b00'10'1, + PLIL1KEEP = 0b01'00'0, + PLIL1STRM = 0b01'00'1, + PLIL2KEEP = 0b01'01'0, + PLIL2STRM = 0b01'01'1, + PLIL3KEEP = 0b01'10'0, + PLIL3STRM = 0b01'10'1, + PSTL1KEEP = 0b10'00'0, + PSTL1STRM = 0b10'00'1, + PSTL2KEEP = 0b10'01'0, + PSTL2STRM = 0b10'01'1, + PSTL3KEEP = 0b10'10'0, + PSTL3STRM = 0b10'10'1, +}; + +enum class TlbiOp { + VMALLE1OS = 0b000'0001'000, // ARMv8.4-TLBI + VAE1OS = 0b000'0001'001, // ARMv8.4-TLBI + ASIDE1OS = 0b000'0001'010, // ARMv8.4-TLBI + VAAE1OS = 0b000'0001'011, // ARMv8.4-TLBI + VALE1OS = 0b000'0001'101, // ARMv8.4-TLBI + VAALE1OS = 0b000'0001'111, // ARMv8.4-TLBI + RVAE1IS = 0b000'0010'001, // ARMv8.4-TLBI + RVAAE1IS = 0b000'0010'011, // ARMv8.4-TLBI + RVALE1IS = 0b000'0010'101, // ARMv8.4-TLBI + RVAALE1IS = 0b000'0010'111, // ARMv8.4-TLBI + VMALLE1IS = 0b000'0011'000, + VAE1IS = 0b000'0011'001, + ASIDE1IS = 0b000'0011'010, + VAAE1IS = 0b000'0011'011, + VALE1IS = 0b000'0011'101, + VAALE1IS = 0b000'0011'111, + RVAE1OS = 0b000'0101'001, // ARMv8.4-TLBI + RVAAE1OS = 0b000'0101'011, // ARMv8.4-TLBI + RVALE1OS = 0b000'0101'101, // ARMv8.4-TLBI + RVAALE1OS = 0b000'0101'111, // ARMv8.4-TLBI + RVAE1 = 0b000'0110'001, // ARMv8.4-TLBI + RVAAE1 = 0b000'0110'011, // ARMv8.4-TLBI + RVALE1 = 0b000'0110'101, // ARMv8.4-TLBI + RVAALE1 = 0b000'0110'111, // ARMv8.4-TLBI + VMALLE1 = 0b000'0111'000, + VAE1 = 0b000'0111'001, + ASIDE1 = 0b000'0111'010, + VAAE1 = 0b000'0111'011, + VALE1 = 0b000'0111'101, + VAALE1 = 0b000'0111'111, + IPAS2E1IS = 0b100'0000'001, + RIPAS2E1IS = 0b100'0000'010, // ARMv8.4-TLBI + IPAS2LE1IS = 0b100'0000'101, + RIPAS2LE1IS = 0b100'0000'110, // ARMv8.4-TLBI + ALLE2OS = 0b100'0001'000, // ARMv8.4-TLBI + VAE2OS = 0b100'0001'001, // ARMv8.4-TLBI + ALLE1OS = 0b100'0001'100, // ARMv8.4-TLBI + VALE2OS = 0b100'0001'101, // ARMv8.4-TLBI + VMALLS12E1OS = 0b100'0001'110, // ARMv8.4-TLBI + RVAE2IS = 0b100'0010'001, // ARMv8.4-TLBI + RVALE2IS = 0b100'0010'101, // ARMv8.4-TLBI + ALLE2IS = 0b100'0011'000, + VAE2IS = 0b100'0011'001, + ALLE1IS = 0b100'0011'100, + VALE2IS = 0b100'0011'101, + VMALLS12E1IS = 0b100'0011'110, + IPAS2E1OS = 0b100'0100'000, // ARMv8.4-TLBI + IPAS2E1 = 0b100'0100'001, + RIPAS2E1 = 0b100'0100'010, // ARMv8.4-TLBI + RIPAS2E1OS = 0b100'0100'011, // ARMv8.4-TLBI + IPAS2LE1OS = 0b100'0100'100, // ARMv8.4-TLBI + IPAS2LE1 = 0b100'0100'101, + RIPAS2LE1 = 0b100'0100'110, // ARMv8.4-TLBI + RIPAS2LE1OS = 0b100'0100'111, // ARMv8.4-TLBI + RVAE2OS = 0b100'0101'001, // ARMv8.4-TLBI + RVALE2OS = 0b100'0101'101, // ARMv8.4-TLBI + RVAE2 = 0b100'0110'001, // ARMv8.4-TLBI + RVALE2 = 0b100'0110'101, // ARMv8.4-TLBI + ALLE2 = 0b100'0111'000, + VAE2 = 0b100'0111'001, + ALLE1 = 0b100'0111'100, + VALE2 = 0b100'0111'101, + VMALLS12E1 = 0b100'0111'110, + ALLE3OS = 0b110'0001'000, // ARMv8.4-TLBI + VAE3OS = 0b110'0001'001, // ARMv8.4-TLBI + VALE3OS = 0b110'0001'101, // ARMv8.4-TLBI + RVAE3IS = 0b110'0010'001, // ARMv8.4-TLBI + RVALE3IS = 0b110'0010'101, // ARMv8.4-TLBI + ALLE3IS = 0b110'0011'000, + VAE3IS = 0b110'0011'001, + VALE3IS = 0b110'0011'101, + RVAE3OS = 0b110'0101'001, // ARMv8.4-TLBI + RVALE3OS = 0b110'0101'101, // ARMv8.4-TLBI + RVAE3 = 0b110'0110'001, // ARMv8.4-TLBI + RVALE3 = 0b110'0110'101, // ARMv8.4-TLBI + ALLE3 = 0b110'0111'000, + VAE3 = 0b110'0111'001, + VALE3 = 0b110'0111'101, +}; + +} // namespace oaknut diff --git a/include/oaknut/impl/fpsimd_mnemonics.inc.hpp b/include/oaknut/impl/fpsimd_mnemonics.inc.hpp new file mode 100644 index 00000000..8867fddd --- /dev/null +++ b/include/oaknut/impl/fpsimd_mnemonics.inc.hpp @@ -0,0 +1,9163 @@ +// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime +// SPDX-License-Identifier: MIT + +void ABS(DReg rd, DReg rn) +{ + emit<"0101111011100000101110nnnnnddddd", "d", "n">(rd, rn); +} +void ABS(VReg_8B rd, VReg_8B rn) +{ + emit<"0000111000100000101110nnnnnddddd", "d", "n">(rd, rn); +} +void ABS(VReg_16B rd, VReg_16B rn) +{ + emit<"0100111000100000101110nnnnnddddd", "d", "n">(rd, rn); +} +void ABS(VReg_4H rd, VReg_4H rn) +{ + emit<"0000111001100000101110nnnnnddddd", "d", "n">(rd, rn); +} +void ABS(VReg_8H rd, VReg_8H rn) +{ + emit<"0100111001100000101110nnnnnddddd", "d", "n">(rd, rn); +} +void ABS(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111010100000101110nnnnnddddd", "d", "n">(rd, rn); +} +void ABS(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111010100000101110nnnnnddddd", "d", "n">(rd, rn); +} +void ABS(VReg_2D rd, VReg_2D rn) +{ + emit<"0100111011100000101110nnnnnddddd", "d", "n">(rd, rn); +} +void ADD(DReg rd, DReg rn, DReg rm) +{ + emit<"01011110111mmmmm100001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADD(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm100001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADD(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm100001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADD(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm100001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADD(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm100001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADD(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm100001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADD(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm100001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADD(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm100001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADDHN(VReg_8B rd, VReg_8H rn, VReg_8H rm) +{ + emit<"00001110001mmmmm010000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADDHN2(VReg_16B rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110001mmmmm010000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADDHN(VReg_4H rd, VReg_4S rn, VReg_4S rm) +{ + emit<"00001110011mmmmm010000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADDHN2(VReg_8H rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110011mmmmm010000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADDHN(VReg_2S rd, VReg_2D rn, VReg_2D rm) +{ + emit<"00001110101mmmmm010000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADDHN2(VReg_4S rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110101mmmmm010000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADDP(DReg rd, VReg_2D rn) +{ + emit<"0101111011110001101110nnnnnddddd", "d", "n">(rd, rn); +} +void ADDP(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm101111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADDP(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm101111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADDP(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm101111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADDP(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm101111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADDP(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm101111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADDP(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm101111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADDP(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm101111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ADDV(BReg rd, VReg_8B rn) +{ + emit<"0000111000110001101110nnnnnddddd", "d", "n">(rd, rn); +} +void ADDV(BReg rd, VReg_16B rn) +{ + emit<"0100111000110001101110nnnnnddddd", "d", "n">(rd, rn); +} +void ADDV(HReg rd, VReg_4H rn) +{ + emit<"0000111001110001101110nnnnnddddd", "d", "n">(rd, rn); +} +void ADDV(HReg rd, VReg_8H rn) +{ + emit<"0100111001110001101110nnnnnddddd", "d", "n">(rd, rn); +} +void ADDV(SReg rd, VReg_4S rn) +{ + emit<"0100111010110001101110nnnnnddddd", "d", "n">(rd, rn); +} +void AESD(VReg_16B rd, VReg_16B rn) +{ + emit<"0100111000101000010110nnnnnddddd", "d", "n">(rd, rn); +} +void AESE(VReg_16B rd, VReg_16B rn) +{ + emit<"0100111000101000010010nnnnnddddd", "d", "n">(rd, rn); +} +void AESIMC(VReg_16B rd, VReg_16B rn) +{ + emit<"0100111000101000011110nnnnnddddd", "d", "n">(rd, rn); +} +void AESMC(VReg_16B rd, VReg_16B rn) +{ + emit<"0100111000101000011010nnnnnddddd", "d", "n">(rd, rn); +} +void AND(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm000111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void AND(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm000111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void BIC(VReg_4H rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmChoice<0, 8> amount = 0) +{ + emit<"0010111100000vvv10c101vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void BIC(VReg_8H rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmChoice<0, 8> amount = 0) +{ + emit<"0110111100000vvv10c101vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void BIC(VReg_2S rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmChoice<0, 8, 16, 24> amount = 0) +{ + emit<"0010111100000vvv0cc101vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void BIC(VReg_4S rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmChoice<0, 8, 16, 24> amount = 0) +{ + emit<"0110111100000vvv0cc101vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void BIC(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110011mmmmm000111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void BIC(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110011mmmmm000111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void BIF(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110111mmmmm000111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void BIF(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110111mmmmm000111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void BIT(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110101mmmmm000111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void BIT(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110101mmmmm000111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void BSL(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110011mmmmm000111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void BSL(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110011mmmmm000111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CLS(VReg_8B rd, VReg_8B rn) +{ + emit<"0000111000100000010010nnnnnddddd", "d", "n">(rd, rn); +} +void CLS(VReg_16B rd, VReg_16B rn) +{ + emit<"0100111000100000010010nnnnnddddd", "d", "n">(rd, rn); +} +void CLS(VReg_4H rd, VReg_4H rn) +{ + emit<"0000111001100000010010nnnnnddddd", "d", "n">(rd, rn); +} +void CLS(VReg_8H rd, VReg_8H rn) +{ + emit<"0100111001100000010010nnnnnddddd", "d", "n">(rd, rn); +} +void CLS(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111010100000010010nnnnnddddd", "d", "n">(rd, rn); +} +void CLS(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111010100000010010nnnnnddddd", "d", "n">(rd, rn); +} +void CLZ(VReg_8B rd, VReg_8B rn) +{ + emit<"0010111000100000010010nnnnnddddd", "d", "n">(rd, rn); +} +void CLZ(VReg_16B rd, VReg_16B rn) +{ + emit<"0110111000100000010010nnnnnddddd", "d", "n">(rd, rn); +} +void CLZ(VReg_4H rd, VReg_4H rn) +{ + emit<"0010111001100000010010nnnnnddddd", "d", "n">(rd, rn); +} +void CLZ(VReg_8H rd, VReg_8H rn) +{ + emit<"0110111001100000010010nnnnnddddd", "d", "n">(rd, rn); +} +void CLZ(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111010100000010010nnnnnddddd", "d", "n">(rd, rn); +} +void CLZ(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111010100000010010nnnnnddddd", "d", "n">(rd, rn); +} +void CMEQ(DReg rd, DReg rn, DReg rm) +{ + emit<"01111110111mmmmm100011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMEQ(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm100011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMEQ(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm100011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMEQ(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm100011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMEQ(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm100011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMEQ(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm100011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMEQ(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm100011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMEQ(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110111mmmmm100011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMEQ(DReg rd, DReg rn, ImmConst<0>) +{ + emit<"0101111011100000100110nnnnnddddd", "d", "n">(rd, rn); +} +void CMEQ(VReg_8B rd, VReg_8B rn, ImmConst<0>) +{ + emit<"0000111000100000100110nnnnnddddd", "d", "n">(rd, rn); +} +void CMEQ(VReg_16B rd, VReg_16B rn, ImmConst<0>) +{ + emit<"0100111000100000100110nnnnnddddd", "d", "n">(rd, rn); +} +void CMEQ(VReg_4H rd, VReg_4H rn, ImmConst<0>) +{ + emit<"0000111001100000100110nnnnnddddd", "d", "n">(rd, rn); +} +void CMEQ(VReg_8H rd, VReg_8H rn, ImmConst<0>) +{ + emit<"0100111001100000100110nnnnnddddd", "d", "n">(rd, rn); +} +void CMEQ(VReg_2S rd, VReg_2S rn, ImmConst<0>) +{ + emit<"0000111010100000100110nnnnnddddd", "d", "n">(rd, rn); +} +void CMEQ(VReg_4S rd, VReg_4S rn, ImmConst<0>) +{ + emit<"0100111010100000100110nnnnnddddd", "d", "n">(rd, rn); +} +void CMEQ(VReg_2D rd, VReg_2D rn, ImmConst<0>) +{ + emit<"0100111011100000100110nnnnnddddd", "d", "n">(rd, rn); +} +void CMGE(DReg rd, DReg rn, DReg rm) +{ + emit<"01011110111mmmmm001111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMGE(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm001111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMGE(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm001111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMGE(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm001111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMGE(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm001111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMGE(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm001111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMGE(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm001111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMGE(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm001111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMGE(DReg rd, DReg rn, ImmConst<0>) +{ + emit<"0111111011100000100010nnnnnddddd", "d", "n">(rd, rn); +} +void CMGE(VReg_8B rd, VReg_8B rn, ImmConst<0>) +{ + emit<"0010111000100000100010nnnnnddddd", "d", "n">(rd, rn); +} +void CMGE(VReg_16B rd, VReg_16B rn, ImmConst<0>) +{ + emit<"0110111000100000100010nnnnnddddd", "d", "n">(rd, rn); +} +void CMGE(VReg_4H rd, VReg_4H rn, ImmConst<0>) +{ + emit<"0010111001100000100010nnnnnddddd", "d", "n">(rd, rn); +} +void CMGE(VReg_8H rd, VReg_8H rn, ImmConst<0>) +{ + emit<"0110111001100000100010nnnnnddddd", "d", "n">(rd, rn); +} +void CMGE(VReg_2S rd, VReg_2S rn, ImmConst<0>) +{ + emit<"0010111010100000100010nnnnnddddd", "d", "n">(rd, rn); +} +void CMGE(VReg_4S rd, VReg_4S rn, ImmConst<0>) +{ + emit<"0110111010100000100010nnnnnddddd", "d", "n">(rd, rn); +} +void CMGE(VReg_2D rd, VReg_2D rn, ImmConst<0>) +{ + emit<"0110111011100000100010nnnnnddddd", "d", "n">(rd, rn); +} +void CMGT(DReg rd, DReg rn, DReg rm) +{ + emit<"01011110111mmmmm001101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMGT(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm001101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMGT(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm001101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMGT(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm001101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMGT(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm001101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMGT(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm001101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMGT(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm001101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMGT(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm001101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMGT(DReg rd, DReg rn, ImmConst<0>) +{ + emit<"0101111011100000100010nnnnnddddd", "d", "n">(rd, rn); +} +void CMGT(VReg_8B rd, VReg_8B rn, ImmConst<0>) +{ + emit<"0000111000100000100010nnnnnddddd", "d", "n">(rd, rn); +} +void CMGT(VReg_16B rd, VReg_16B rn, ImmConst<0>) +{ + emit<"0100111000100000100010nnnnnddddd", "d", "n">(rd, rn); +} +void CMGT(VReg_4H rd, VReg_4H rn, ImmConst<0>) +{ + emit<"0000111001100000100010nnnnnddddd", "d", "n">(rd, rn); +} +void CMGT(VReg_8H rd, VReg_8H rn, ImmConst<0>) +{ + emit<"0100111001100000100010nnnnnddddd", "d", "n">(rd, rn); +} +void CMGT(VReg_2S rd, VReg_2S rn, ImmConst<0>) +{ + emit<"0000111010100000100010nnnnnddddd", "d", "n">(rd, rn); +} +void CMGT(VReg_4S rd, VReg_4S rn, ImmConst<0>) +{ + emit<"0100111010100000100010nnnnnddddd", "d", "n">(rd, rn); +} +void CMGT(VReg_2D rd, VReg_2D rn, ImmConst<0>) +{ + emit<"0100111011100000100010nnnnnddddd", "d", "n">(rd, rn); +} +void CMHI(DReg rd, DReg rn, DReg rm) +{ + emit<"01111110111mmmmm001101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMHI(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm001101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMHI(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm001101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMHI(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm001101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMHI(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm001101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMHI(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm001101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMHI(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm001101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMHI(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110111mmmmm001101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMHS(DReg rd, DReg rn, DReg rm) +{ + emit<"01111110111mmmmm001111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMHS(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm001111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMHS(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm001111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMHS(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm001111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMHS(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm001111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMHS(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm001111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMHS(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm001111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMHS(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110111mmmmm001111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMLE(DReg rd, DReg rn, ImmConst<0>) +{ + emit<"0111111011100000100110nnnnnddddd", "d", "n">(rd, rn); +} +void CMLE(VReg_8B rd, VReg_8B rn, ImmConst<0>) +{ + emit<"0010111000100000100110nnnnnddddd", "d", "n">(rd, rn); +} +void CMLE(VReg_16B rd, VReg_16B rn, ImmConst<0>) +{ + emit<"0110111000100000100110nnnnnddddd", "d", "n">(rd, rn); +} +void CMLE(VReg_4H rd, VReg_4H rn, ImmConst<0>) +{ + emit<"0010111001100000100110nnnnnddddd", "d", "n">(rd, rn); +} +void CMLE(VReg_8H rd, VReg_8H rn, ImmConst<0>) +{ + emit<"0110111001100000100110nnnnnddddd", "d", "n">(rd, rn); +} +void CMLE(VReg_2S rd, VReg_2S rn, ImmConst<0>) +{ + emit<"0010111010100000100110nnnnnddddd", "d", "n">(rd, rn); +} +void CMLE(VReg_4S rd, VReg_4S rn, ImmConst<0>) +{ + emit<"0110111010100000100110nnnnnddddd", "d", "n">(rd, rn); +} +void CMLE(VReg_2D rd, VReg_2D rn, ImmConst<0>) +{ + emit<"0110111011100000100110nnnnnddddd", "d", "n">(rd, rn); +} +void CMLT(DReg rd, DReg rn, ImmConst<0>) +{ + emit<"0101111011100000101010nnnnnddddd", "d", "n">(rd, rn); +} +void CMLT(VReg_8B rd, VReg_8B rn, ImmConst<0>) +{ + emit<"0000111000100000101010nnnnnddddd", "d", "n">(rd, rn); +} +void CMLT(VReg_16B rd, VReg_16B rn, ImmConst<0>) +{ + emit<"0100111000100000101010nnnnnddddd", "d", "n">(rd, rn); +} +void CMLT(VReg_4H rd, VReg_4H rn, ImmConst<0>) +{ + emit<"0000111001100000101010nnnnnddddd", "d", "n">(rd, rn); +} +void CMLT(VReg_8H rd, VReg_8H rn, ImmConst<0>) +{ + emit<"0100111001100000101010nnnnnddddd", "d", "n">(rd, rn); +} +void CMLT(VReg_2S rd, VReg_2S rn, ImmConst<0>) +{ + emit<"0000111010100000101010nnnnnddddd", "d", "n">(rd, rn); +} +void CMLT(VReg_4S rd, VReg_4S rn, ImmConst<0>) +{ + emit<"0100111010100000101010nnnnnddddd", "d", "n">(rd, rn); +} +void CMLT(VReg_2D rd, VReg_2D rn, ImmConst<0>) +{ + emit<"0100111011100000101010nnnnnddddd", "d", "n">(rd, rn); +} +void CMTST(DReg rd, DReg rn, DReg rm) +{ + emit<"01011110111mmmmm100011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMTST(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm100011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMTST(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm100011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMTST(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm100011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMTST(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm100011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMTST(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm100011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMTST(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm100011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CMTST(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm100011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void CNT(VReg_8B rd, VReg_8B rn) +{ + emit<"0000111000100000010110nnnnnddddd", "d", "n">(rd, rn); +} +void CNT(VReg_16B rd, VReg_16B rn) +{ + emit<"0100111000100000010110nnnnnddddd", "d", "n">(rd, rn); +} +void DUP(BReg rd, BElem en) +{ + emit<"01011110000xxxx1000001nnnnnddddd", "d", "n", "x">(rd, en.reg_index(), en.elem_index()); +} +void DUP(HReg rd, HElem en) +{ + emit<"01011110000xxx10000001nnnnnddddd", "d", "n", "x">(rd, en.reg_index(), en.elem_index()); +} +void DUP(SReg rd, SElem en) +{ + emit<"01011110000xx100000001nnnnnddddd", "d", "n", "x">(rd, en.reg_index(), en.elem_index()); +} +void DUP(DReg rd, DElem en) +{ + emit<"01011110000x1000000001nnnnnddddd", "d", "n", "x">(rd, en.reg_index(), en.elem_index()); +} +void DUP(VReg_8B rd, BElem en) +{ + emit<"00001110000xxxx1000001nnnnnddddd", "d", "n", "x">(rd, en.reg_index(), en.elem_index()); +} +void DUP(VReg_16B rd, BElem en) +{ + emit<"01001110000xxxx1000001nnnnnddddd", "d", "n", "x">(rd, en.reg_index(), en.elem_index()); +} +void DUP(VReg_4H rd, HElem en) +{ + emit<"00001110000xxx10000001nnnnnddddd", "d", "n", "x">(rd, en.reg_index(), en.elem_index()); +} +void DUP(VReg_8H rd, HElem en) +{ + emit<"01001110000xxx10000001nnnnnddddd", "d", "n", "x">(rd, en.reg_index(), en.elem_index()); +} +void DUP(VReg_2S rd, SElem en) +{ + emit<"00001110000xx100000001nnnnnddddd", "d", "n", "x">(rd, en.reg_index(), en.elem_index()); +} +void DUP(VReg_4S rd, SElem en) +{ + emit<"01001110000xx100000001nnnnnddddd", "d", "n", "x">(rd, en.reg_index(), en.elem_index()); +} +void DUP(VReg_2D rd, DElem en) +{ + emit<"01001110000x1000000001nnnnnddddd", "d", "n", "x">(rd, en.reg_index(), en.elem_index()); +} +void DUP(VReg_8B rd, WReg rn) +{ + emit<"00001110000xxxx1000011nnnnnddddd", "d", "n">(rd, rn); +} +void DUP(VReg_16B rd, WReg rn) +{ + emit<"01001110000xxxx1000011nnnnnddddd", "d", "n">(rd, rn); +} +void DUP(VReg_4H rd, WReg rn) +{ + emit<"00001110000xxx10000011nnnnnddddd", "d", "n">(rd, rn); +} +void DUP(VReg_8H rd, WReg rn) +{ + emit<"01001110000xxx10000011nnnnnddddd", "d", "n">(rd, rn); +} +void DUP(VReg_2S rd, WReg rn) +{ + emit<"00001110000xx100000011nnnnnddddd", "d", "n">(rd, rn); +} +void DUP(VReg_4S rd, WReg rn) +{ + emit<"01001110000xx100000011nnnnnddddd", "d", "n">(rd, rn); +} +void DUP(VReg_2D rd, XReg rn) +{ + emit<"01001110000x1000000011nnnnnddddd", "d", "n">(rd, rn); +} +void EOR(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm000111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void EOR(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm000111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void EXT(VReg_8B rd, VReg_8B rn, VReg_8B rm, Imm<3> index) +{ + emit<"00101110000mmmmm0jjjj0nnnnnddddd", "d", "n", "m", "j">(rd, rn, rm, index); +} +void EXT(VReg_16B rd, VReg_16B rn, VReg_16B rm, Imm<4> index) +{ + emit<"01101110000mmmmm0jjjj0nnnnnddddd", "d", "n", "m", "j">(rd, rn, rm, index); +} +void FABD(SReg rd, SReg rn, SReg rm) +{ + emit<"01111110101mmmmm110101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FABD(DReg rd, DReg rn, DReg rm) +{ + emit<"01111110111mmmmm110101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FABD(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm110101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FABD(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm110101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FABD(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110111mmmmm110101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FABS(SReg rd, SReg rn) +{ + emit<"0001111000100000110000nnnnnddddd", "d", "n">(rd, rn); +} +void FABS(DReg rd, DReg rn) +{ + emit<"0001111001100000110000nnnnnddddd", "d", "n">(rd, rn); +} +void FABS(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111010100000111110nnnnnddddd", "d", "n">(rd, rn); +} +void FABS(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111010100000111110nnnnnddddd", "d", "n">(rd, rn); +} +void FABS(VReg_2D rd, VReg_2D rn) +{ + emit<"0100111011100000111110nnnnnddddd", "d", "n">(rd, rn); +} +void FACGE(SReg rd, SReg rn, SReg rm) +{ + emit<"01111110001mmmmm111011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FACGE(DReg rd, DReg rn, DReg rm) +{ + emit<"01111110011mmmmm111011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FACGE(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110001mmmmm111011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FACGE(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110001mmmmm111011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FACGE(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110011mmmmm111011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FACGT(SReg rd, SReg rn, SReg rm) +{ + emit<"01111110101mmmmm111011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FACGT(DReg rd, DReg rn, DReg rm) +{ + emit<"01111110111mmmmm111011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FACGT(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm111011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FACGT(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm111011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FACGT(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110111mmmmm111011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FADD(SReg rd, SReg rn, SReg rm) +{ + emit<"00011110001mmmmm001010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FADD(DReg rd, DReg rn, DReg rm) +{ + emit<"00011110011mmmmm001010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FADD(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110001mmmmm110101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FADD(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110001mmmmm110101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FADD(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110011mmmmm110101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FADDP(SReg rd, VReg_2S rn) +{ + emit<"0111111000110000110110nnnnnddddd", "d", "n">(rd, rn); +} +void FADDP(DReg rd, VReg_2D rn) +{ + emit<"0111111001110000110110nnnnnddddd", "d", "n">(rd, rn); +} +void FADDP(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110001mmmmm110101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FADDP(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110001mmmmm110101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FADDP(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110011mmmmm110101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FCCMP(SReg rn, SReg rm, Imm<4> nzcv, Cond cond) +{ + emit<"00011110001mmmmmcccc01nnnnn0ffff", "n", "m", "f", "c">(rn, rm, nzcv, cond); +} +void FCCMP(DReg rn, DReg rm, Imm<4> nzcv, Cond cond) +{ + emit<"00011110011mmmmmcccc01nnnnn0ffff", "n", "m", "f", "c">(rn, rm, nzcv, cond); +} +void FCCMPE(SReg rn, SReg rm, Imm<4> nzcv, Cond cond) +{ + emit<"00011110001mmmmmcccc01nnnnn1ffff", "n", "m", "f", "c">(rn, rm, nzcv, cond); +} +void FCCMPE(DReg rn, DReg rm, Imm<4> nzcv, Cond cond) +{ + emit<"00011110011mmmmmcccc01nnnnn1ffff", "n", "m", "f", "c">(rn, rm, nzcv, cond); +} +void FCMEQ(SReg rd, SReg rn, SReg rm) +{ + emit<"01011110001mmmmm111001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FCMEQ(DReg rd, DReg rn, DReg rm) +{ + emit<"01011110011mmmmm111001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FCMEQ(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110001mmmmm111001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FCMEQ(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110001mmmmm111001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FCMEQ(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110011mmmmm111001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FCMEQ(SReg rd, SReg rn, ImmConstFZero) +{ + emit<"0101111010100000110110nnnnnddddd", "d", "n">(rd, rn); +} +void FCMEQ(DReg rd, DReg rn, ImmConstFZero) +{ + emit<"0101111011100000110110nnnnnddddd", "d", "n">(rd, rn); +} +void FCMEQ(VReg_2S rd, VReg_2S rn, ImmConstFZero) +{ + emit<"0000111010100000110110nnnnnddddd", "d", "n">(rd, rn); +} +void FCMEQ(VReg_4S rd, VReg_4S rn, ImmConstFZero) +{ + emit<"0100111010100000110110nnnnnddddd", "d", "n">(rd, rn); +} +void FCMEQ(VReg_2D rd, VReg_2D rn, ImmConstFZero) +{ + emit<"0100111011100000110110nnnnnddddd", "d", "n">(rd, rn); +} +void FCMGE(SReg rd, SReg rn, SReg rm) +{ + emit<"01111110001mmmmm111001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FCMGE(DReg rd, DReg rn, DReg rm) +{ + emit<"01111110011mmmmm111001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FCMGE(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110001mmmmm111001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FCMGE(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110001mmmmm111001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FCMGE(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110011mmmmm111001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FCMGE(SReg rd, SReg rn, ImmConstFZero) +{ + emit<"0111111010100000110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCMGE(DReg rd, DReg rn, ImmConstFZero) +{ + emit<"0111111011100000110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCMGE(VReg_2S rd, VReg_2S rn, ImmConstFZero) +{ + emit<"0010111010100000110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCMGE(VReg_4S rd, VReg_4S rn, ImmConstFZero) +{ + emit<"0110111010100000110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCMGE(VReg_2D rd, VReg_2D rn, ImmConstFZero) +{ + emit<"0110111011100000110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCMGT(SReg rd, SReg rn, SReg rm) +{ + emit<"01111110101mmmmm111001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FCMGT(DReg rd, DReg rn, DReg rm) +{ + emit<"01111110111mmmmm111001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FCMGT(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm111001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FCMGT(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm111001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FCMGT(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110111mmmmm111001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FCMGT(SReg rd, SReg rn, ImmConstFZero) +{ + emit<"0101111010100000110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCMGT(DReg rd, DReg rn, ImmConstFZero) +{ + emit<"0101111011100000110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCMGT(VReg_2S rd, VReg_2S rn, ImmConstFZero) +{ + emit<"0000111010100000110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCMGT(VReg_4S rd, VReg_4S rn, ImmConstFZero) +{ + emit<"0100111010100000110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCMGT(VReg_2D rd, VReg_2D rn, ImmConstFZero) +{ + emit<"0100111011100000110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCMLE(SReg rd, SReg rn, ImmConstFZero) +{ + emit<"0111111010100000110110nnnnnddddd", "d", "n">(rd, rn); +} +void FCMLE(DReg rd, DReg rn, ImmConstFZero) +{ + emit<"0111111011100000110110nnnnnddddd", "d", "n">(rd, rn); +} +void FCMLE(VReg_2S rd, VReg_2S rn, ImmConstFZero) +{ + emit<"0010111010100000110110nnnnnddddd", "d", "n">(rd, rn); +} +void FCMLE(VReg_4S rd, VReg_4S rn, ImmConstFZero) +{ + emit<"0110111010100000110110nnnnnddddd", "d", "n">(rd, rn); +} +void FCMLE(VReg_2D rd, VReg_2D rn, ImmConstFZero) +{ + emit<"0110111011100000110110nnnnnddddd", "d", "n">(rd, rn); +} +void FCMLT(SReg rd, SReg rn, ImmConstFZero) +{ + emit<"0101111010100000111010nnnnnddddd", "d", "n">(rd, rn); +} +void FCMLT(DReg rd, DReg rn, ImmConstFZero) +{ + emit<"0101111011100000111010nnnnnddddd", "d", "n">(rd, rn); +} +void FCMLT(VReg_2S rd, VReg_2S rn, ImmConstFZero) +{ + emit<"0000111010100000111010nnnnnddddd", "d", "n">(rd, rn); +} +void FCMLT(VReg_4S rd, VReg_4S rn, ImmConstFZero) +{ + emit<"0100111010100000111010nnnnnddddd", "d", "n">(rd, rn); +} +void FCMLT(VReg_2D rd, VReg_2D rn, ImmConstFZero) +{ + emit<"0100111011100000111010nnnnnddddd", "d", "n">(rd, rn); +} +void FCMP(SReg rn, SReg rm) +{ + emit<"00011110001mmmmm001000nnnnn00000", "n", "m">(rn, rm); +} +void FCMP(SReg rn, ImmConstFZero) +{ + emit<"0001111000100000001000nnnnn01000", "n">(rn); +} +void FCMP(DReg rn, DReg rm) +{ + emit<"00011110011mmmmm001000nnnnn00000", "n", "m">(rn, rm); +} +void FCMP(DReg rn, ImmConstFZero) +{ + emit<"0001111001100000001000nnnnn01000", "n">(rn); +} +void FCMPE(SReg rn, SReg rm) +{ + emit<"00011110001mmmmm001000nnnnn10000", "n", "m">(rn, rm); +} +void FCMPE(SReg rn, ImmConstFZero) +{ + emit<"0001111000100000001000nnnnn11000", "n">(rn); +} +void FCMPE(DReg rn, DReg rm) +{ + emit<"00011110011mmmmm001000nnnnn10000", "n", "m">(rn, rm); +} +void FCMPE(DReg rn, ImmConstFZero) +{ + emit<"0001111001100000001000nnnnn11000", "n">(rn); +} +void FCSEL(SReg rd, SReg rn, SReg rm, Cond cond) +{ + emit<"00011110001mmmmmcccc11nnnnnddddd", "d", "n", "m", "c">(rd, rn, rm, cond); +} +void FCSEL(DReg rd, DReg rn, DReg rm, Cond cond) +{ + emit<"00011110011mmmmmcccc11nnnnnddddd", "d", "n", "m", "c">(rd, rn, rm, cond); +} +void FCVT(SReg rd, HReg rn) +{ + emit<"0001111011100010010000nnnnnddddd", "d", "n">(rd, rn); +} +void FCVT(DReg rd, HReg rn) +{ + emit<"0001111011100010110000nnnnnddddd", "d", "n">(rd, rn); +} +void FCVT(HReg rd, SReg rn) +{ + emit<"0001111000100011110000nnnnnddddd", "d", "n">(rd, rn); +} +void FCVT(DReg rd, SReg rn) +{ + emit<"0001111000100010110000nnnnnddddd", "d", "n">(rd, rn); +} +void FCVT(HReg rd, DReg rn) +{ + emit<"0001111001100011110000nnnnnddddd", "d", "n">(rd, rn); +} +void FCVT(SReg rd, DReg rn) +{ + emit<"0001111001100010010000nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTAS(WReg wd, SReg rn) +{ + emit<"0001111000100100000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTAS(XReg xd, SReg rn) +{ + emit<"1001111000100100000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTAS(WReg wd, DReg rn) +{ + emit<"0001111001100100000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTAS(XReg xd, DReg rn) +{ + emit<"1001111001100100000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTAS(SReg rd, SReg rn) +{ + emit<"0101111000100001110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTAS(DReg rd, DReg rn) +{ + emit<"0101111001100001110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTAS(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111000100001110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTAS(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111000100001110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTAS(VReg_2D rd, VReg_2D rn) +{ + emit<"0100111001100001110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTAU(WReg wd, SReg rn) +{ + emit<"0001111000100101000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTAU(XReg xd, SReg rn) +{ + emit<"1001111000100101000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTAU(WReg wd, DReg rn) +{ + emit<"0001111001100101000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTAU(XReg xd, DReg rn) +{ + emit<"1001111001100101000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTAU(SReg rd, SReg rn) +{ + emit<"0111111000100001110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTAU(DReg rd, DReg rn) +{ + emit<"0111111001100001110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTAU(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111000100001110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTAU(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111000100001110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTAU(VReg_2D rd, VReg_2D rn) +{ + emit<"0110111001100001110010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTL(VReg_4S rd, VReg_4H rn) +{ + emit<"0000111000100001011110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTL2(VReg_4S rd, VReg_8H rn) +{ + emit<"0100111000100001011110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTL(VReg_2D rd, VReg_2S rn) +{ + emit<"0000111001100001011110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTL2(VReg_2D rd, VReg_4S rn) +{ + emit<"0100111001100001011110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTMS(WReg wd, SReg rn) +{ + emit<"0001111000110000000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTMS(XReg xd, SReg rn) +{ + emit<"1001111000110000000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTMS(WReg wd, DReg rn) +{ + emit<"0001111001110000000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTMS(XReg xd, DReg rn) +{ + emit<"1001111001110000000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTMS(SReg rd, SReg rn) +{ + emit<"0101111000100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTMS(DReg rd, DReg rn) +{ + emit<"0101111001100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTMS(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111000100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTMS(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111000100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTMS(VReg_2D rd, VReg_2D rn) +{ + emit<"0100111001100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTMU(WReg wd, SReg rn) +{ + emit<"0001111000110001000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTMU(XReg xd, SReg rn) +{ + emit<"1001111000110001000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTMU(WReg wd, DReg rn) +{ + emit<"0001111001110001000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTMU(XReg xd, DReg rn) +{ + emit<"1001111001110001000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTMU(SReg rd, SReg rn) +{ + emit<"0111111000100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTMU(DReg rd, DReg rn) +{ + emit<"0111111001100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTMU(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111000100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTMU(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111000100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTMU(VReg_2D rd, VReg_2D rn) +{ + emit<"0110111001100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTN(VReg_4H rd, VReg_4S rn) +{ + emit<"0000111000100001011010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTN2(VReg_8H rd, VReg_4S rn) +{ + emit<"0100111000100001011010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTN(VReg_2S rd, VReg_2D rn) +{ + emit<"0000111001100001011010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTN2(VReg_4S rd, VReg_2D rn) +{ + emit<"0100111001100001011010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTNS(WReg wd, SReg rn) +{ + emit<"0001111000100000000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTNS(XReg xd, SReg rn) +{ + emit<"1001111000100000000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTNS(WReg wd, DReg rn) +{ + emit<"0001111001100000000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTNS(XReg xd, DReg rn) +{ + emit<"1001111001100000000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTNS(SReg rd, SReg rn) +{ + emit<"0101111000100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTNS(DReg rd, DReg rn) +{ + emit<"0101111001100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTNS(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111000100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTNS(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111000100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTNS(VReg_2D rd, VReg_2D rn) +{ + emit<"0100111001100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTNU(WReg wd, SReg rn) +{ + emit<"0001111000100001000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTNU(XReg xd, SReg rn) +{ + emit<"1001111000100001000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTNU(WReg wd, DReg rn) +{ + emit<"0001111001100001000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTNU(XReg xd, DReg rn) +{ + emit<"1001111001100001000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTNU(SReg rd, SReg rn) +{ + emit<"0111111000100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTNU(DReg rd, DReg rn) +{ + emit<"0111111001100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTNU(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111000100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTNU(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111000100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTNU(VReg_2D rd, VReg_2D rn) +{ + emit<"0110111001100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTPS(WReg wd, SReg rn) +{ + emit<"0001111000101000000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTPS(XReg xd, SReg rn) +{ + emit<"1001111000101000000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTPS(WReg wd, DReg rn) +{ + emit<"0001111001101000000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTPS(XReg xd, DReg rn) +{ + emit<"1001111001101000000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTPS(SReg rd, SReg rn) +{ + emit<"0101111010100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTPS(DReg rd, DReg rn) +{ + emit<"0101111011100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTPS(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111010100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTPS(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111010100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTPS(VReg_2D rd, VReg_2D rn) +{ + emit<"0100111011100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTPU(WReg wd, SReg rn) +{ + emit<"0001111000101001000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTPU(XReg xd, SReg rn) +{ + emit<"1001111000101001000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTPU(WReg wd, DReg rn) +{ + emit<"0001111001101001000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTPU(XReg xd, DReg rn) +{ + emit<"1001111001101001000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTPU(SReg rd, SReg rn) +{ + emit<"0111111010100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTPU(DReg rd, DReg rn) +{ + emit<"0111111011100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTPU(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111010100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTPU(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111010100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTPU(VReg_2D rd, VReg_2D rn) +{ + emit<"0110111011100001101010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTXN(SReg rd, DReg rn) +{ + emit<"0111111001100001011010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTXN(VReg_2S rd, VReg_2D rn) +{ + emit<"0010111001100001011010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTXN2(VReg_4S rd, VReg_2D rn) +{ + emit<"0110111001100001011010nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTZS(WReg wd, SReg rn, ImmRange<1, 32> fbits) +{ + emit<"0001111000011000SSSSSSnnnnnddddd", "d", "n", "S">(wd, rn, 64 - fbits.value()); +} +void FCVTZS(XReg xd, SReg rn, ImmRange<1, 64> fbits) +{ + emit<"1001111000011000SSSSSSnnnnnddddd", "d", "n", "S">(xd, rn, 64 - fbits.value()); +} +void FCVTZS(WReg wd, DReg rn, ImmRange<1, 32> fbits) +{ + emit<"0001111001011000SSSSSSnnnnnddddd", "d", "n", "S">(wd, rn, 64 - fbits.value()); +} +void FCVTZS(XReg xd, DReg rn, ImmRange<1, 64> fbits) +{ + emit<"1001111001011000SSSSSSnnnnnddddd", "d", "n", "S">(xd, rn, 64 - fbits.value()); +} +void FCVTZS(WReg wd, SReg rn) +{ + emit<"0001111000111000000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTZS(XReg xd, SReg rn) +{ + emit<"1001111000111000000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTZS(WReg wd, DReg rn) +{ + emit<"0001111001111000000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTZS(XReg xd, DReg rn) +{ + emit<"1001111001111000000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTZS(HReg rd, HReg rn, ImmRange<1, 16> fbits) +{ + emit<"010111110001hbbb111111nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - fbits.value()); +} +void FCVTZS(SReg rd, SReg rn, ImmRange<1, 32> fbits) +{ + emit<"01011111001hhbbb111111nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - fbits.value()); +} +void FCVTZS(DReg rd, DReg rn, ImmRange<1, 64> fbits) +{ + emit<"0101111101hhhbbb111111nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - fbits.value()); +} +void FCVTZS(VReg_4H rd, VReg_4H rn, ImmRange<1, 16> fbits) +{ + emit<"000011110001hbbb111111nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - fbits.value()); +} +void FCVTZS(VReg_8H rd, VReg_8H rn, ImmRange<1, 16> fbits) +{ + emit<"010011110001hbbb111111nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - fbits.value()); +} +void FCVTZS(VReg_2S rd, VReg_2S rn, ImmRange<1, 32> fbits) +{ + emit<"00001111001hhbbb111111nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - fbits.value()); +} +void FCVTZS(VReg_4S rd, VReg_4S rn, ImmRange<1, 32> fbits) +{ + emit<"01001111001hhbbb111111nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - fbits.value()); +} +void FCVTZS(VReg_2D rd, VReg_2D rn, ImmRange<1, 64> fbits) +{ + emit<"0100111101hhhbbb111111nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - fbits.value()); +} +void FCVTZS(SReg rd, SReg rn) +{ + emit<"0101111010100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTZS(DReg rd, DReg rn) +{ + emit<"0101111011100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTZS(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111010100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTZS(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111010100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTZS(VReg_2D rd, VReg_2D rn) +{ + emit<"0100111011100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTZU(WReg wd, SReg rn, ImmRange<1, 32> fbits) +{ + emit<"0001111000011001SSSSSSnnnnnddddd", "d", "n", "S">(wd, rn, 64 - fbits.value()); +} +void FCVTZU(XReg xd, SReg rn, ImmRange<1, 64> fbits) +{ + emit<"1001111000011001SSSSSSnnnnnddddd", "d", "n", "S">(xd, rn, 64 - fbits.value()); +} +void FCVTZU(WReg wd, DReg rn, ImmRange<1, 32> fbits) +{ + emit<"0001111001011001SSSSSSnnnnnddddd", "d", "n", "S">(wd, rn, 64 - fbits.value()); +} +void FCVTZU(XReg xd, DReg rn, ImmRange<1, 64> fbits) +{ + emit<"1001111001011001SSSSSSnnnnnddddd", "d", "n", "S">(xd, rn, 64 - fbits.value()); +} +void FCVTZU(WReg wd, SReg rn) +{ + emit<"0001111000111001000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTZU(XReg xd, SReg rn) +{ + emit<"1001111000111001000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTZU(WReg wd, DReg rn) +{ + emit<"0001111001111001000000nnnnnddddd", "d", "n">(wd, rn); +} +void FCVTZU(XReg xd, DReg rn) +{ + emit<"1001111001111001000000nnnnnddddd", "d", "n">(xd, rn); +} +void FCVTZU(HReg rd, HReg rn, ImmRange<1, 16> fbits) +{ + emit<"011111110001hbbb111111nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - fbits.value()); +} +void FCVTZU(SReg rd, SReg rn, ImmRange<1, 32> fbits) +{ + emit<"01111111001hhbbb111111nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - fbits.value()); +} +void FCVTZU(DReg rd, DReg rn, ImmRange<1, 64> fbits) +{ + emit<"0111111101hhhbbb111111nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - fbits.value()); +} +void FCVTZU(VReg_4H rd, VReg_4H rn, ImmRange<1, 16> fbits) +{ + emit<"001011110001hbbb111111nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - fbits.value()); +} +void FCVTZU(VReg_8H rd, VReg_8H rn, ImmRange<1, 16> fbits) +{ + emit<"011011110001hbbb111111nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - fbits.value()); +} +void FCVTZU(VReg_2S rd, VReg_2S rn, ImmRange<1, 32> fbits) +{ + emit<"00101111001hhbbb111111nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - fbits.value()); +} +void FCVTZU(VReg_4S rd, VReg_4S rn, ImmRange<1, 32> fbits) +{ + emit<"01101111001hhbbb111111nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - fbits.value()); +} +void FCVTZU(VReg_2D rd, VReg_2D rn, ImmRange<1, 64> fbits) +{ + emit<"0110111101hhhbbb111111nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - fbits.value()); +} +void FCVTZU(SReg rd, SReg rn) +{ + emit<"0111111010100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTZU(DReg rd, DReg rn) +{ + emit<"0111111011100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTZU(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111010100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTZU(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111010100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FCVTZU(VReg_2D rd, VReg_2D rn) +{ + emit<"0110111011100001101110nnnnnddddd", "d", "n">(rd, rn); +} +void FDIV(SReg rd, SReg rn, SReg rm) +{ + emit<"00011110001mmmmm000110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FDIV(DReg rd, DReg rn, DReg rm) +{ + emit<"00011110011mmmmm000110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FDIV(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110001mmmmm111111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FDIV(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110001mmmmm111111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FDIV(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110011mmmmm111111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMADD(SReg rd, SReg rn, SReg rm, SReg ra) +{ + emit<"00011111000mmmmm0aaaaannnnnddddd", "d", "n", "m", "a">(rd, rn, rm, ra); +} +void FMADD(DReg rd, DReg rn, DReg rm, DReg ra) +{ + emit<"00011111010mmmmm0aaaaannnnnddddd", "d", "n", "m", "a">(rd, rn, rm, ra); +} +void FMAX(SReg rd, SReg rn, SReg rm) +{ + emit<"00011110001mmmmm010010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMAX(DReg rd, DReg rn, DReg rm) +{ + emit<"00011110011mmmmm010010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMAX(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110001mmmmm111101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMAX(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110001mmmmm111101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMAX(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110011mmmmm111101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMAXNM(SReg rd, SReg rn, SReg rm) +{ + emit<"00011110001mmmmm011010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMAXNM(DReg rd, DReg rn, DReg rm) +{ + emit<"00011110011mmmmm011010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMAXNM(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110001mmmmm110001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMAXNM(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110001mmmmm110001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMAXNM(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110011mmmmm110001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMAXNMP(SReg rd, VReg_2S rn) +{ + emit<"0111111000110000110010nnnnnddddd", "d", "n">(rd, rn); +} +void FMAXNMP(DReg rd, VReg_2D rn) +{ + emit<"0111111001110000110010nnnnnddddd", "d", "n">(rd, rn); +} +void FMAXNMP(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110001mmmmm110001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMAXNMP(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110001mmmmm110001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMAXNMP(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110011mmmmm110001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMAXNMV(SReg rd, VReg_4S rn) +{ + emit<"0110111000110000110010nnnnnddddd", "d", "n">(rd, rn); +} +void FMAXP(SReg rd, VReg_2S rn) +{ + emit<"0111111000110000111110nnnnnddddd", "d", "n">(rd, rn); +} +void FMAXP(DReg rd, VReg_2D rn) +{ + emit<"0111111001110000111110nnnnnddddd", "d", "n">(rd, rn); +} +void FMAXP(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110001mmmmm111101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMAXP(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110001mmmmm111101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMAXP(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110011mmmmm111101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMAXV(SReg rd, VReg_4S rn) +{ + emit<"0110111000110000111110nnnnnddddd", "d", "n">(rd, rn); +} +void FMIN(SReg rd, SReg rn, SReg rm) +{ + emit<"00011110001mmmmm010110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMIN(DReg rd, DReg rn, DReg rm) +{ + emit<"00011110011mmmmm010110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMIN(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm111101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMIN(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm111101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMIN(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm111101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMINNM(SReg rd, SReg rn, SReg rm) +{ + emit<"00011110001mmmmm011110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMINNM(DReg rd, DReg rn, DReg rm) +{ + emit<"00011110011mmmmm011110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMINNM(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm110001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMINNM(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm110001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMINNM(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm110001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMINNMP(SReg rd, VReg_2S rn) +{ + emit<"0111111010110000110010nnnnnddddd", "d", "n">(rd, rn); +} +void FMINNMP(DReg rd, VReg_2D rn) +{ + emit<"0111111011110000110010nnnnnddddd", "d", "n">(rd, rn); +} +void FMINNMP(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm110001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMINNMP(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm110001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMINNMP(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110111mmmmm110001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMINNMV(SReg rd, VReg_4S rn) +{ + emit<"0110111010110000110010nnnnnddddd", "d", "n">(rd, rn); +} +void FMINP(SReg rd, VReg_2S rn) +{ + emit<"0111111010110000111110nnnnnddddd", "d", "n">(rd, rn); +} +void FMINP(DReg rd, VReg_2D rn) +{ + emit<"0111111011110000111110nnnnnddddd", "d", "n">(rd, rn); +} +void FMINP(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm111101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMINP(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm111101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMINP(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110111mmmmm111101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMINV(SReg rd, VReg_4S rn) +{ + emit<"0110111010110000111110nnnnnddddd", "d", "n">(rd, rn); +} +void FMLA(SReg rd, SReg rn, SElem em) +{ + emit<"0101111110LMmmmm0001H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), em.elem_index() & 1, em.elem_index() >> 1); +} +void FMLA(DReg rd, DReg rn, DElem em) +{ + emit<"0101111111LMmmmm0001H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), 0, em.elem_index()); +} +void FMLA(VReg_2S rd, VReg_2S rn, SElem em) +{ + emit<"0000111110LMmmmm0001H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), em.elem_index() & 1, em.elem_index() >> 1); +} +void FMLA(VReg_4S rd, VReg_4S rn, SElem em) +{ + emit<"0100111110LMmmmm0001H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), em.elem_index() & 1, em.elem_index() >> 1); +} +void FMLA(VReg_2D rd, VReg_2D rn, DElem em) +{ + emit<"0100111111LMmmmm0001H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), 0, em.elem_index()); +} +void FMLA(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110001mmmmm110011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMLA(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110001mmmmm110011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMLA(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110011mmmmm110011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMLS(SReg rd, SReg rn, SElem em) +{ + emit<"0101111110LMmmmm0101H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), em.elem_index() & 1, em.elem_index() >> 1); +} +void FMLS(DReg rd, DReg rn, DElem em) +{ + emit<"0101111111LMmmmm0101H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), 0, em.elem_index()); +} +void FMLS(VReg_2S rd, VReg_2S rn, SElem em) +{ + emit<"0000111110LMmmmm0101H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), em.elem_index() & 1, em.elem_index() >> 1); +} +void FMLS(VReg_4S rd, VReg_4S rn, SElem em) +{ + emit<"0100111110LMmmmm0101H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), em.elem_index() & 1, em.elem_index() >> 1); +} +void FMLS(VReg_2D rd, VReg_2D rn, DElem em) +{ + emit<"0100111111LMmmmm0101H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), 0, em.elem_index()); +} +void FMLS(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm110011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMLS(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm110011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMLS(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm110011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMOV(SReg rd, WReg wn) +{ + emit<"0001111000100111000000nnnnnddddd", "d", "n">(rd, wn); +} +void FMOV(WReg wd, SReg rn) +{ + emit<"0001111000100110000000nnnnnddddd", "d", "n">(wd, rn); +} +void FMOV(DReg rd, XReg xn) +{ + emit<"1001111001100111000000nnnnnddddd", "d", "n">(rd, xn); +} +void FMOV(DElem_1 ed, XReg xn) +{ + emit<"1001111010101111000000nnnnnddddd", "d", "n">(ed.reg_index(), xn); +} +void FMOV(XReg xd, DReg rn) +{ + emit<"1001111001100110000000nnnnnddddd", "d", "n">(xd, rn); +} +void FMOV(XReg xd, DElem_1 en) +{ + emit<"1001111010101110000000nnnnnddddd", "d", "n">(xd, en.reg_index()); +} +void FMOV(SReg rd, SReg rn) +{ + emit<"0001111000100000010000nnnnnddddd", "d", "n">(rd, rn); +} +void FMOV(DReg rd, DReg rn) +{ + emit<"0001111001100000010000nnnnnddddd", "d", "n">(rd, rn); +} +void FMOV(SReg rd, FImm8 imm) +{ + emit<"00011110001iiiiiiii10000000ddddd", "d", "i">(rd, imm); +} +void FMOV(DReg rd, FImm8 imm) +{ + emit<"00011110011iiiiiiii10000000ddddd", "d", "i">(rd, imm); +} +void FMOV(VReg_2S rd, FImm8 imm) +{ + emit<"0000111100000vvv111101vvvvvddddd", "d", "v">(rd, imm); +} +void FMOV(VReg_4S rd, FImm8 imm) +{ + emit<"0100111100000vvv111101vvvvvddddd", "d", "v">(rd, imm); +} +void FMOV(VReg_2D rd, FImm8 imm) +{ + emit<"0110111100000vvv111101vvvvvddddd", "d", "v">(rd, imm); +} +void FMSUB(SReg rd, SReg rn, SReg rm, SReg ra) +{ + emit<"00011111000mmmmm1aaaaannnnnddddd", "d", "n", "m", "a">(rd, rn, rm, ra); +} +void FMSUB(DReg rd, DReg rn, DReg rm, DReg ra) +{ + emit<"00011111010mmmmm1aaaaannnnnddddd", "d", "n", "m", "a">(rd, rn, rm, ra); +} +void FMUL(SReg rd, SReg rn, SElem em) +{ + emit<"0101111110LMmmmm1001H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), em.elem_index() & 1, em.elem_index() >> 1); +} +void FMUL(DReg rd, DReg rn, DElem em) +{ + emit<"0101111111LMmmmm1001H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), 0, em.elem_index()); +} +void FMUL(VReg_2S rd, VReg_2S rn, SElem em) +{ + emit<"0000111110LMmmmm1001H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), em.elem_index() & 1, em.elem_index() >> 1); +} +void FMUL(VReg_4S rd, VReg_4S rn, SElem em) +{ + emit<"0100111110LMmmmm1001H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), em.elem_index() & 1, em.elem_index() >> 1); +} +void FMUL(VReg_2D rd, VReg_2D rn, DElem em) +{ + emit<"0100111111LMmmmm1001H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), 0, em.elem_index()); +} +void FMUL(SReg rd, SReg rn, SReg rm) +{ + emit<"00011110001mmmmm000010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMUL(DReg rd, DReg rn, DReg rm) +{ + emit<"00011110011mmmmm000010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMUL(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110001mmmmm110111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMUL(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110001mmmmm110111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMUL(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110011mmmmm110111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMULX(SReg rd, SReg rn, SReg rm) +{ + emit<"01011110001mmmmm110111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMULX(DReg rd, DReg rn, DReg rm) +{ + emit<"01011110011mmmmm110111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMULX(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110001mmmmm110111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMULX(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110001mmmmm110111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMULX(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110011mmmmm110111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FMULX(SReg rd, SReg rn, SElem em) +{ + emit<"0111111110LMmmmm1001H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), em.elem_index() & 1, em.elem_index() >> 1); +} +void FMULX(DReg rd, DReg rn, DElem em) +{ + emit<"0111111111LMmmmm1001H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), 0, em.elem_index()); +} +void FMULX(VReg_2S rd, VReg_2S rn, SElem em) +{ + emit<"0010111110LMmmmm1001H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), em.elem_index() & 1, em.elem_index() >> 1); +} +void FMULX(VReg_4S rd, VReg_4S rn, SElem em) +{ + emit<"0110111110LMmmmm1001H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), em.elem_index() & 1, em.elem_index() >> 1); +} +void FMULX(VReg_2D rd, VReg_2D rn, DElem em) +{ + emit<"0110111111LMmmmm1001H0nnnnnddddd", "d", "n", "Mm", "L", "H">(rd, rn, em.reg_index(), 0, em.elem_index()); +} +void FNEG(SReg rd, SReg rn) +{ + emit<"0001111000100001010000nnnnnddddd", "d", "n">(rd, rn); +} +void FNEG(DReg rd, DReg rn) +{ + emit<"0001111001100001010000nnnnnddddd", "d", "n">(rd, rn); +} +void FNEG(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111010100000111110nnnnnddddd", "d", "n">(rd, rn); +} +void FNEG(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111010100000111110nnnnnddddd", "d", "n">(rd, rn); +} +void FNEG(VReg_2D rd, VReg_2D rn) +{ + emit<"0110111011100000111110nnnnnddddd", "d", "n">(rd, rn); +} +void FNMADD(SReg rd, SReg rn, SReg rm, SReg ra) +{ + emit<"00011111001mmmmm0aaaaannnnnddddd", "d", "n", "m", "a">(rd, rn, rm, ra); +} +void FNMADD(DReg rd, DReg rn, DReg rm, DReg ra) +{ + emit<"00011111011mmmmm0aaaaannnnnddddd", "d", "n", "m", "a">(rd, rn, rm, ra); +} +void FNMSUB(SReg rd, SReg rn, SReg rm, SReg ra) +{ + emit<"00011111001mmmmm1aaaaannnnnddddd", "d", "n", "m", "a">(rd, rn, rm, ra); +} +void FNMSUB(DReg rd, DReg rn, DReg rm, DReg ra) +{ + emit<"00011111011mmmmm1aaaaannnnnddddd", "d", "n", "m", "a">(rd, rn, rm, ra); +} +void FNMUL(SReg rd, SReg rn, SReg rm) +{ + emit<"00011110001mmmmm100010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FNMUL(DReg rd, DReg rn, DReg rm) +{ + emit<"00011110011mmmmm100010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FRECPE(SReg rd, SReg rn) +{ + emit<"0101111010100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void FRECPE(DReg rd, DReg rn) +{ + emit<"0101111011100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void FRECPE(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111010100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void FRECPE(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111010100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void FRECPE(VReg_2D rd, VReg_2D rn) +{ + emit<"0100111011100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void FRECPS(SReg rd, SReg rn, SReg rm) +{ + emit<"01011110001mmmmm111111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FRECPS(DReg rd, DReg rn, DReg rm) +{ + emit<"01011110011mmmmm111111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FRECPS(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110001mmmmm111111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FRECPS(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110001mmmmm111111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FRECPS(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110011mmmmm111111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FRECPX(SReg rd, SReg rn) +{ + emit<"0101111010100001111110nnnnnddddd", "d", "n">(rd, rn); +} +void FRECPX(DReg rd, DReg rn) +{ + emit<"0101111011100001111110nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTA(SReg rd, SReg rn) +{ + emit<"0001111000100110010000nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTA(DReg rd, DReg rn) +{ + emit<"0001111001100110010000nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTA(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111000100001100010nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTA(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111000100001100010nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTA(VReg_2D rd, VReg_2D rn) +{ + emit<"0110111001100001100010nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTI(SReg rd, SReg rn) +{ + emit<"0001111000100111110000nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTI(DReg rd, DReg rn) +{ + emit<"0001111001100111110000nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTI(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111010100001100110nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTI(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111010100001100110nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTI(VReg_2D rd, VReg_2D rn) +{ + emit<"0110111011100001100110nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTM(SReg rd, SReg rn) +{ + emit<"0001111000100101010000nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTM(DReg rd, DReg rn) +{ + emit<"0001111001100101010000nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTM(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111000100001100110nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTM(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111000100001100110nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTM(VReg_2D rd, VReg_2D rn) +{ + emit<"0100111001100001100110nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTN(SReg rd, SReg rn) +{ + emit<"0001111000100100010000nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTN(DReg rd, DReg rn) +{ + emit<"0001111001100100010000nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTN(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111000100001100010nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTN(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111000100001100010nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTN(VReg_2D rd, VReg_2D rn) +{ + emit<"0100111001100001100010nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTP(SReg rd, SReg rn) +{ + emit<"0001111000100100110000nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTP(DReg rd, DReg rn) +{ + emit<"0001111001100100110000nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTP(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111010100001100010nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTP(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111010100001100010nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTP(VReg_2D rd, VReg_2D rn) +{ + emit<"0100111011100001100010nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTX(SReg rd, SReg rn) +{ + emit<"0001111000100111010000nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTX(DReg rd, DReg rn) +{ + emit<"0001111001100111010000nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTX(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111000100001100110nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTX(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111000100001100110nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTX(VReg_2D rd, VReg_2D rn) +{ + emit<"0110111001100001100110nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTZ(SReg rd, SReg rn) +{ + emit<"0001111000100101110000nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTZ(DReg rd, DReg rn) +{ + emit<"0001111001100101110000nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTZ(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111010100001100110nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTZ(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111010100001100110nnnnnddddd", "d", "n">(rd, rn); +} +void FRINTZ(VReg_2D rd, VReg_2D rn) +{ + emit<"0100111011100001100110nnnnnddddd", "d", "n">(rd, rn); +} +void FRSQRTE(SReg rd, SReg rn) +{ + emit<"0111111010100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void FRSQRTE(DReg rd, DReg rn) +{ + emit<"0111111011100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void FRSQRTE(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111010100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void FRSQRTE(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111010100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void FRSQRTE(VReg_2D rd, VReg_2D rn) +{ + emit<"0110111011100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void FRSQRTS(SReg rd, SReg rn, SReg rm) +{ + emit<"01011110101mmmmm111111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FRSQRTS(DReg rd, DReg rn, DReg rm) +{ + emit<"01011110111mmmmm111111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FRSQRTS(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm111111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FRSQRTS(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm111111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FRSQRTS(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm111111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FSQRT(SReg rd, SReg rn) +{ + emit<"0001111000100001110000nnnnnddddd", "d", "n">(rd, rn); +} +void FSQRT(DReg rd, DReg rn) +{ + emit<"0001111001100001110000nnnnnddddd", "d", "n">(rd, rn); +} +void FSQRT(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111010100001111110nnnnnddddd", "d", "n">(rd, rn); +} +void FSQRT(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111010100001111110nnnnnddddd", "d", "n">(rd, rn); +} +void FSQRT(VReg_2D rd, VReg_2D rn) +{ + emit<"0110111011100001111110nnnnnddddd", "d", "n">(rd, rn); +} +void FSUB(SReg rd, SReg rn, SReg rm) +{ + emit<"00011110001mmmmm001110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FSUB(DReg rd, DReg rn, DReg rm) +{ + emit<"00011110011mmmmm001110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FSUB(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm110101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FSUB(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm110101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void FSUB(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm110101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void INS(BElem ed, BElem en) +{ + emit<"01101110000xxxx10yyyy1nnnnnddddd", "d", "x", "n", "y">(ed.reg_index(), ed.elem_index(), en.reg_index(), en.elem_index()); +} +void INS(HElem ed, HElem en) +{ + emit<"01101110000xxx100yyy01nnnnnddddd", "d", "x", "n", "y">(ed.reg_index(), ed.elem_index(), en.reg_index(), en.elem_index()); +} +void INS(SElem ed, SElem en) +{ + emit<"01101110000xx1000yy001nnnnnddddd", "d", "x", "n", "y">(ed.reg_index(), ed.elem_index(), en.reg_index(), en.elem_index()); +} +void INS(DElem ed, DElem en) +{ + emit<"01101110000x10000y0001nnnnnddddd", "d", "x", "n", "y">(ed.reg_index(), ed.elem_index(), en.reg_index(), en.elem_index()); +} +void INS(BElem ed, WReg rn) +{ + emit<"01001110000xxxx1000111nnnnnddddd", "d", "x", "n">(ed.reg_index(), ed.elem_index(), rn); +} +void INS(HElem ed, WReg rn) +{ + emit<"01001110000xxx10000111nnnnnddddd", "d", "x", "n">(ed.reg_index(), ed.elem_index(), rn); +} +void INS(SElem ed, WReg rn) +{ + emit<"01001110000xx100000111nnnnnddddd", "d", "x", "n">(ed.reg_index(), ed.elem_index(), rn); +} +void INS(DElem ed, XReg rn) +{ + emit<"01001110000x1000000111nnnnnddddd", "d", "x", "n">(ed.reg_index(), ed.elem_index(), rn); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000011100nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000011100nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000011101nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000011101nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000011110nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000011110nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000011111nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000011111nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000101000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000101000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000101001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000101001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000101010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000101010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000101011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000101011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000011000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000011000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000011001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000011001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000011010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000011010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000011011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000011011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000001000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000001000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000001001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000001001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000001010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000001010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000001011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000001011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0000110011011111011100nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0100110011011111011100nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0000110011011111011101nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0100110011011111011101nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0000110011011111011110nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0100110011011111011110nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0000110011011111011111nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0100110011011111011111nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm011100nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm011100nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm011101nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm011101nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm011110nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm011110nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm011111nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm011111nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0000110011011111101000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110011011111101000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0000110011011111101001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110011011111101001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0000110011011111101010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110011011111101010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0000110011011111101011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110011011111101011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm101000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm101000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm101001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm101001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm101010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm101010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm101011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm101011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0000110011011111011000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<48>) +{ + emit<"0100110011011111011000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0000110011011111011001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<48>) +{ + emit<"0100110011011111011001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0000110011011111011010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<48>) +{ + emit<"0100110011011111011010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0000110011011111011011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<48>) +{ + emit<"0100110011011111011011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm011000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm011000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm011001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm011001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm011010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm011010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm011011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm011011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0000110011011111001000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<64>) +{ + emit<"0100110011011111001000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0000110011011111001001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<64>) +{ + emit<"0100110011011111001001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0000110011011111001010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<64>) +{ + emit<"0100110011011111001010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0000110011011111001011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<64>) +{ + emit<"0100110011011111001011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm001000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm001000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm001001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm001001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm001010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm001010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm001011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm001011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0Q00110101000000000Szznnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0Q00110101000000010Sz0nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0Q00110101000000100S00nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD1(List tlist, XRegSp addr_n) +{ + emit<"0Q00110101000000100001nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<1>) +{ + emit<"0Q00110111011111000Szznnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101110mmmmm000Szznnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<2>) +{ + emit<"0Q00110111011111010Sz0nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101110mmmmm010Sz0nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<4>) +{ + emit<"0Q00110111011111100S00nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101110mmmmm100S00nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0Q00110111011111100001nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101110mmmmm100001nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void LD1R(List tlist, XRegSp addr_n) +{ + emit<"0000110101000000110000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1R(List tlist, XRegSp addr_n) +{ + emit<"0100110101000000110000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1R(List tlist, XRegSp addr_n) +{ + emit<"0000110101000000110001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1R(List tlist, XRegSp addr_n) +{ + emit<"0100110101000000110001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1R(List tlist, XRegSp addr_n) +{ + emit<"0000110101000000110010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1R(List tlist, XRegSp addr_n) +{ + emit<"0100110101000000110010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1R(List tlist, XRegSp addr_n) +{ + emit<"0000110101000000110011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1R(List tlist, XRegSp addr_n) +{ + emit<"0100110101000000110011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<1>) +{ + emit<"0000110111011111110000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<1>) +{ + emit<"0100110111011111110000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<2>) +{ + emit<"0000110111011111110001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<2>) +{ + emit<"0100110111011111110001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<4>) +{ + emit<"0000110111011111110010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<4>) +{ + emit<"0100110111011111110010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0000110111011111110011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0100110111011111110011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD1R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001101110mmmmm110000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001101110mmmmm110000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001101110mmmmm110001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001101110mmmmm110001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001101110mmmmm110010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001101110mmmmm110010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001101110mmmmm110011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD1R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001101110mmmmm110011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD2(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000100000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000100000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000100001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000100001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000100010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000100010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000100011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0000110011011111100000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110011011111100000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0000110011011111100001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110011011111100001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0000110011011111100010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110011011111100010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110011011111100011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm100000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm100000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm100001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm100001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm100010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm100010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm100011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD2(List tlist, XRegSp addr_n) +{ + emit<"0Q00110101100000000Szznnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD2(List tlist, XRegSp addr_n) +{ + emit<"0Q00110101100000010Sz0nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD2(List tlist, XRegSp addr_n) +{ + emit<"0Q00110101100000100S00nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD2(List tlist, XRegSp addr_n) +{ + emit<"0Q00110101100000100001nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<2>) +{ + emit<"0Q00110111111111000Szznnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101111mmmmm000Szznnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<4>) +{ + emit<"0Q00110111111111010Sz0nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101111mmmmm010Sz0nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0Q00110111111111100S00nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101111mmmmm100S00nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0Q00110111111111100001nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101111mmmmm100001nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void LD2R(List tlist, XRegSp addr_n) +{ + emit<"0000110101100000110000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2R(List tlist, XRegSp addr_n) +{ + emit<"0100110101100000110000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2R(List tlist, XRegSp addr_n) +{ + emit<"0000110101100000110001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2R(List tlist, XRegSp addr_n) +{ + emit<"0100110101100000110001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2R(List tlist, XRegSp addr_n) +{ + emit<"0000110101100000110010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2R(List tlist, XRegSp addr_n) +{ + emit<"0100110101100000110010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2R(List tlist, XRegSp addr_n) +{ + emit<"0000110101100000110011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2R(List tlist, XRegSp addr_n) +{ + emit<"0100110101100000110011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<2>) +{ + emit<"0000110111111111110000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<2>) +{ + emit<"0100110111111111110000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<4>) +{ + emit<"0000110111111111110001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<4>) +{ + emit<"0100110111111111110001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0000110111111111110010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0100110111111111110010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0000110111111111110011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0100110111111111110011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD2R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001101111mmmmm110000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD2R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001101111mmmmm110000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD2R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001101111mmmmm110001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD2R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001101111mmmmm110001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD2R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001101111mmmmm110010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD2R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001101111mmmmm110010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD2R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001101111mmmmm110011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD2R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001101111mmmmm110011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD3(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000010000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000010000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000010001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000010001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000010010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000010010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000010011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0000110011011111010000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<48>) +{ + emit<"0100110011011111010000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0000110011011111010001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<48>) +{ + emit<"0100110011011111010001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0000110011011111010010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<48>) +{ + emit<"0100110011011111010010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<48>) +{ + emit<"0100110011011111010011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm010000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm010000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm010001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm010001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm010010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm010010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm010011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD3(List tlist, XRegSp addr_n) +{ + emit<"0Q00110101000000001Szznnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD3(List tlist, XRegSp addr_n) +{ + emit<"0Q00110101000000011Sz0nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD3(List tlist, XRegSp addr_n) +{ + emit<"0Q00110101000000101S00nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD3(List tlist, XRegSp addr_n) +{ + emit<"0Q00110101000000101001nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<3>) +{ + emit<"0Q00110111011111001Szznnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101110mmmmm001Szznnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<6>) +{ + emit<"0Q00110111011111011Sz0nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101110mmmmm011Sz0nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<12>) +{ + emit<"0Q00110111011111101S00nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101110mmmmm101S00nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0Q00110111011111101001nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101110mmmmm101001nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void LD3R(List tlist, XRegSp addr_n) +{ + emit<"0000110101000000111000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3R(List tlist, XRegSp addr_n) +{ + emit<"0100110101000000111000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3R(List tlist, XRegSp addr_n) +{ + emit<"0000110101000000111001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3R(List tlist, XRegSp addr_n) +{ + emit<"0100110101000000111001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3R(List tlist, XRegSp addr_n) +{ + emit<"0000110101000000111010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3R(List tlist, XRegSp addr_n) +{ + emit<"0100110101000000111010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3R(List tlist, XRegSp addr_n) +{ + emit<"0000110101000000111011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3R(List tlist, XRegSp addr_n) +{ + emit<"0100110101000000111011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<3>) +{ + emit<"0000110111011111111000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<3>) +{ + emit<"0100110111011111111000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<6>) +{ + emit<"0000110111011111111001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<6>) +{ + emit<"0100110111011111111001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<12>) +{ + emit<"0000110111011111111010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<12>) +{ + emit<"0100110111011111111010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0000110111011111111011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0100110111011111111011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD3R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001101110mmmmm111000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD3R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001101110mmmmm111000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD3R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001101110mmmmm111001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD3R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001101110mmmmm111001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD3R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001101110mmmmm111010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD3R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001101110mmmmm111010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD3R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001101110mmmmm111011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD3R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001101110mmmmm111011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD4(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000000000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000000000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000000001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000000001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4(List tlist, XRegSp addr_n) +{ + emit<"0000110001000000000010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000000010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4(List tlist, XRegSp addr_n) +{ + emit<"0100110001000000000011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0000110011011111000000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<64>) +{ + emit<"0100110011011111000000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0000110011011111000001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<64>) +{ + emit<"0100110011011111000001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0000110011011111000010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<64>) +{ + emit<"0100110011011111000010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<64>) +{ + emit<"0100110011011111000011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm000000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm000000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm000001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm000001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100110mmmmm000010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm000010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100110mmmmm000011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD4(List tlist, XRegSp addr_n) +{ + emit<"0Q00110101100000001Szznnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD4(List tlist, XRegSp addr_n) +{ + emit<"0Q00110101100000011Sz0nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD4(List tlist, XRegSp addr_n) +{ + emit<"0Q00110101100000101S00nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD4(List tlist, XRegSp addr_n) +{ + emit<"0Q00110101100000101001nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<4>) +{ + emit<"0Q00110111111111001Szznnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101111mmmmm001Szznnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0Q00110111111111011Sz0nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101111mmmmm011Sz0nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0Q00110111111111101S00nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101111mmmmm101S00nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0Q00110111111111101001nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void LD4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101111mmmmm101001nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void LD4R(List tlist, XRegSp addr_n) +{ + emit<"0000110101100000111000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4R(List tlist, XRegSp addr_n) +{ + emit<"0100110101100000111000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4R(List tlist, XRegSp addr_n) +{ + emit<"0000110101100000111001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4R(List tlist, XRegSp addr_n) +{ + emit<"0100110101100000111001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4R(List tlist, XRegSp addr_n) +{ + emit<"0000110101100000111010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4R(List tlist, XRegSp addr_n) +{ + emit<"0100110101100000111010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4R(List tlist, XRegSp addr_n) +{ + emit<"0000110101100000111011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4R(List tlist, XRegSp addr_n) +{ + emit<"0100110101100000111011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<4>) +{ + emit<"0000110111111111111000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<4>) +{ + emit<"0100110111111111111000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0000110111111111111001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0100110111111111111001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0000110111111111111010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0100110111111111111010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0000110111111111111011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4R(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110111111111111011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void LD4R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001101111mmmmm111000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD4R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001101111mmmmm111000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD4R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001101111mmmmm111001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD4R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001101111mmmmm111001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD4R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001101111mmmmm111010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD4R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001101111mmmmm111010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD4R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001101111mmmmm111011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LD4R(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001101111mmmmm111011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void LDNP(SReg rt1, SReg rt2, XRegSp addr_n, SOffset<9, 2> offset = 0) +{ + emit<"0010110001iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void LDNP(DReg rt1, DReg rt2, XRegSp addr_n, SOffset<10, 3> offset = 0) +{ + emit<"0110110001iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void LDNP(QReg rt1, QReg rt2, XRegSp addr_n, SOffset<11, 4> offset = 0) +{ + emit<"1010110001iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void LDP(SReg rt1, SReg rt2, XRegSp addr_n, PostIndexed, SOffset<9, 2> offset) +{ + emit<"0010110011iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void LDP(DReg rt1, DReg rt2, XRegSp addr_n, PostIndexed, SOffset<10, 3> offset) +{ + emit<"0110110011iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void LDP(QReg rt1, QReg rt2, XRegSp addr_n, PostIndexed, SOffset<11, 4> offset) +{ + emit<"1010110011iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void LDP(SReg rt1, SReg rt2, XRegSp addr_n, PreIndexed, SOffset<9, 2> offset) +{ + emit<"0010110111iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void LDP(DReg rt1, DReg rt2, XRegSp addr_n, PreIndexed, SOffset<10, 3> offset) +{ + emit<"0110110111iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void LDP(QReg rt1, QReg rt2, XRegSp addr_n, PreIndexed, SOffset<11, 4> offset) +{ + emit<"1010110111iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void LDP(SReg rt1, SReg rt2, XRegSp addr_n, SOffset<9, 2> offset = 0) +{ + emit<"0010110101iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void LDP(DReg rt1, DReg rt2, XRegSp addr_n, SOffset<10, 3> offset = 0) +{ + emit<"0110110101iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void LDP(QReg rt1, QReg rt2, XRegSp addr_n, SOffset<11, 4> offset = 0) +{ + emit<"1010110101iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void LDR(BReg rt, XRegSp addr_n, PostIndexed, SOffset<9, 0> offset) +{ + emit<"00111100010iiiiiiiii01nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDR(HReg rt, XRegSp addr_n, PostIndexed, SOffset<9, 0> offset) +{ + emit<"01111100010iiiiiiiii01nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDR(SReg rt, XRegSp addr_n, PostIndexed, SOffset<9, 0> offset) +{ + emit<"10111100010iiiiiiiii01nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDR(DReg rt, XRegSp addr_n, PostIndexed, SOffset<9, 0> offset) +{ + emit<"11111100010iiiiiiiii01nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDR(QReg rt, XRegSp addr_n, PostIndexed, SOffset<9, 0> offset) +{ + emit<"00111100110iiiiiiiii01nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDR(BReg rt, XRegSp addr_n, PreIndexed, SOffset<9, 0> offset) +{ + emit<"00111100010iiiiiiiii11nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDR(HReg rt, XRegSp addr_n, PreIndexed, SOffset<9, 0> offset) +{ + emit<"01111100010iiiiiiiii11nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDR(SReg rt, XRegSp addr_n, PreIndexed, SOffset<9, 0> offset) +{ + emit<"10111100010iiiiiiiii11nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDR(DReg rt, XRegSp addr_n, PreIndexed, SOffset<9, 0> offset) +{ + emit<"11111100010iiiiiiiii11nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDR(QReg rt, XRegSp addr_n, PreIndexed, SOffset<9, 0> offset) +{ + emit<"00111100110iiiiiiiii11nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDR(BReg rt, XRegSp addr_n, POffset<12, 0> offset = 0) +{ + emit<"0011110101iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDR(HReg rt, XRegSp addr_n, POffset<13, 1> offset = 0) +{ + emit<"0111110101iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDR(SReg rt, XRegSp addr_n, POffset<14, 2> offset = 0) +{ + emit<"1011110101iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDR(DReg rt, XRegSp addr_n, POffset<15, 3> offset = 0) +{ + emit<"1111110101iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDR(QReg rt, XRegSp addr_n, POffset<16, 4> offset = 0) +{ + emit<"0011110111iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDR(SReg rt, AddrOffset<21, 2> offset) +{ + emit<"00011100iiiiiiiiiiiiiiiiiiittttt", "t", "i">(rt, offset); +} +void LDR(DReg rt, AddrOffset<21, 2> offset) +{ + emit<"01011100iiiiiiiiiiiiiiiiiiittttt", "t", "i">(rt, offset); +} +void LDR(QReg rt, AddrOffset<21, 2> offset) +{ + emit<"10011100iiiiiiiiiiiiiiiiiiittttt", "t", "i">(rt, offset); +} +void LDR(BReg rt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 0> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"00111100011mmmmmpppS10nnnnnttttt", "t", "n", "m", "p", "S">(rt, xn, rm, ext, amount); +} +void LDR(HReg rt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 1> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"01111100011mmmmmpppS10nnnnnttttt", "t", "n", "m", "p", "S">(rt, xn, rm, ext, amount); +} +void LDR(SReg rt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 2> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"10111100011mmmmmpppS10nnnnnttttt", "t", "n", "m", "p", "S">(rt, xn, rm, ext, amount); +} +void LDR(DReg rt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 3> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"11111100011mmmmmpppS10nnnnnttttt", "t", "n", "m", "p", "S">(rt, xn, rm, ext, amount); +} +void LDR(QReg rt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 4> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"00111100111mmmmmpppS10nnnnnttttt", "t", "n", "m", "p", "S">(rt, xn, rm, ext, amount); +} +void LDUR(BReg rt, XRegSp addr_n, SOffset<9, 0> offset = 0) +{ + emit<"00111100010iiiiiiiii00nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDUR(HReg rt, XRegSp addr_n, SOffset<9, 0> offset = 0) +{ + emit<"01111100010iiiiiiiii00nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDUR(SReg rt, XRegSp addr_n, SOffset<9, 0> offset = 0) +{ + emit<"10111100010iiiiiiiii00nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDUR(DReg rt, XRegSp addr_n, SOffset<9, 0> offset = 0) +{ + emit<"11111100010iiiiiiiii00nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void LDUR(QReg rt, XRegSp addr_n, SOffset<9, 0> offset = 0) +{ + emit<"00111100110iiiiiiiii00nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void MLA(VReg_4H rd, VReg_4H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0010111101LMmmmm0000H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void MLA(VReg_8H rd, VReg_8H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0110111101LMmmmm0000H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void MLA(VReg_2S rd, VReg_2S rn, SElem em) +{ + emit<"0010111110LMmmmm0000H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void MLA(VReg_4S rd, VReg_4S rn, SElem em) +{ + emit<"0110111110LMmmmm0000H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void MLA(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm100101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MLA(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm100101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MLA(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm100101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MLA(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm100101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MLA(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm100101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MLA(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm100101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MLS(VReg_4H rd, VReg_4H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0010111101LMmmmm0100H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void MLS(VReg_8H rd, VReg_8H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0110111101LMmmmm0100H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void MLS(VReg_2S rd, VReg_2S rn, SElem em) +{ + emit<"0010111110LMmmmm0100H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void MLS(VReg_4S rd, VReg_4S rn, SElem em) +{ + emit<"0110111110LMmmmm0100H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void MLS(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm100101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MLS(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm100101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MLS(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm100101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MLS(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm100101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MLS(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm100101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MLS(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm100101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MOV(BElem ed, BElem en) +{ + emit<"01101110000xxxx10yyyy1nnnnnddddd", "d", "x", "n", "y">(ed.reg_index(), ed.elem_index(), en.reg_index(), en.elem_index()); +} +void MOV(HElem ed, HElem en) +{ + emit<"01101110000xxx100yyy01nnnnnddddd", "d", "x", "n", "y">(ed.reg_index(), ed.elem_index(), en.reg_index(), en.elem_index()); +} +void MOV(SElem ed, SElem en) +{ + emit<"01101110000xx1000yy001nnnnnddddd", "d", "x", "n", "y">(ed.reg_index(), ed.elem_index(), en.reg_index(), en.elem_index()); +} +void MOV(DElem ed, DElem en) +{ + emit<"01101110000x10000y0001nnnnnddddd", "d", "x", "n", "y">(ed.reg_index(), ed.elem_index(), en.reg_index(), en.elem_index()); +} +void MOV(BElem ed, WReg rn) +{ + emit<"01001110000xxxx1000111nnnnnddddd", "d", "x", "n">(ed.reg_index(), ed.elem_index(), rn); +} +void MOV(HElem ed, WReg rn) +{ + emit<"01001110000xxx10000111nnnnnddddd", "d", "x", "n">(ed.reg_index(), ed.elem_index(), rn); +} +void MOV(SElem ed, WReg rn) +{ + emit<"01001110000xx100000111nnnnnddddd", "d", "x", "n">(ed.reg_index(), ed.elem_index(), rn); +} +void MOV(DElem ed, XReg rn) +{ + emit<"01001110000x1000000111nnnnnddddd", "d", "x", "n">(ed.reg_index(), ed.elem_index(), rn); +} +void MOV(BReg rd, BElem en) +{ + emit<"01011110000xxxx1000001nnnnnddddd", "d", "n", "x">(rd, en.reg_index(), en.elem_index()); +} +void MOV(HReg rd, HElem en) +{ + emit<"01011110000xxx10000001nnnnnddddd", "d", "n", "x">(rd, en.reg_index(), en.elem_index()); +} +void MOV(SReg rd, SElem en) +{ + emit<"01011110000xx100000001nnnnnddddd", "d", "n", "x">(rd, en.reg_index(), en.elem_index()); +} +void MOV(DReg rd, DElem en) +{ + emit<"01011110000x1000000001nnnnnddddd", "d", "n", "x">(rd, en.reg_index(), en.elem_index()); +} +void MOV(WReg wd, SElem en) +{ + emit<"00001110000ii100001111nnnnnddddd", "d", "n", "x">(wd, en.reg_index(), en.elem_index()); +} +void MOV(XReg xd, DElem en) +{ + emit<"01001110000i1000001111nnnnnddddd", "d", "n", "x">(xd, en.reg_index(), en.elem_index()); +} +void MOV(VReg_8B rd, VReg_8B rn) +{ + emit<"00001110101mmmmm000111nnnnnddddd", "d", "n">(rd, rn); +} +void MOV(VReg_16B rd, VReg_16B rn) +{ + emit<"01001110101mmmmm000111nnnnnddddd", "d", "n">(rd, rn); +} +void MOVI(VReg_8B rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmConst<0> = 0) +{ + emit<"0000111100000vvv111001vvvvvddddd", "d", "v">(rd, imm); +} +void MOVI(VReg_16B rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmConst<0> = 0) +{ + emit<"0100111100000vvv111001vvvvvddddd", "d", "v">(rd, imm); +} +void MOVI(VReg_4H rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmChoice<0, 8> amount = 0) +{ + emit<"0000111100000vvv10c001vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void MOVI(VReg_8H rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmChoice<0, 8> amount = 0) +{ + emit<"0100111100000vvv10c001vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void MOVI(VReg_2S rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmChoice<0, 8, 16, 24> amount = 0) +{ + emit<"0000111100000vvv0cc001vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void MOVI(VReg_4S rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmChoice<0, 8, 16, 24> amount = 0) +{ + emit<"0100111100000vvv0cc001vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void MOVI(VReg_2S rd, Imm<8> imm, MslSymbol, ImmChoice<8, 16> amount) +{ + emit<"0000111100000vvv110c01vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void MOVI(VReg_4S rd, Imm<8> imm, MslSymbol, ImmChoice<8, 16> amount) +{ + emit<"0100111100000vvv110c01vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void MOVI(DReg rd, RepImm imm) +{ + emit<"0010111100000vvv111001vvvvvddddd", "d", "v">(rd, imm); +} +void MOVI(VReg_2D rd, RepImm imm) +{ + emit<"0110111100000vvv111001vvvvvddddd", "d", "v">(rd, imm); +} +void MUL(VReg_4H rd, VReg_4H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0000111101LMmmmm1000H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void MUL(VReg_8H rd, VReg_8H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0100111101LMmmmm1000H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void MUL(VReg_2S rd, VReg_2S rn, SElem em) +{ + emit<"0000111110LMmmmm1000H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void MUL(VReg_4S rd, VReg_4S rn, SElem em) +{ + emit<"0100111110LMmmmm1000H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void MUL(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm100111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MUL(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm100111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MUL(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm100111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MUL(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm100111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MUL(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm100111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MUL(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm100111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void MVN(VReg_8B rd, VReg_8B rn) +{ + emit<"0010111000100000010110nnnnnddddd", "d", "n">(rd, rn); +} +void MVN(VReg_16B rd, VReg_16B rn) +{ + emit<"0110111000100000010110nnnnnddddd", "d", "n">(rd, rn); +} +void MVNI(VReg_4H rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmChoice<0, 8> amount = 0) +{ + emit<"0010111100000vvv10c001vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void MVNI(VReg_8H rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmChoice<0, 8> amount = 0) +{ + emit<"0110111100000vvv10c001vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void MVNI(VReg_2S rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmChoice<0, 8, 16, 24> amount = 0) +{ + emit<"0010111100000vvv0cc001vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void MVNI(VReg_4S rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmChoice<0, 8, 16, 24> amount = 0) +{ + emit<"0110111100000vvv0cc001vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void MVNI(VReg_2S rd, Imm<8> imm, MslSymbol, ImmChoice<8, 16> amount) +{ + emit<"0010111100000vvv110c01vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void MVNI(VReg_4S rd, Imm<8> imm, MslSymbol, ImmChoice<8, 16> amount) +{ + emit<"0110111100000vvv110c01vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void NEG(DReg rd, DReg rn) +{ + emit<"0111111011100000101110nnnnnddddd", "d", "n">(rd, rn); +} +void NEG(VReg_8B rd, VReg_8B rn) +{ + emit<"0010111000100000101110nnnnnddddd", "d", "n">(rd, rn); +} +void NEG(VReg_16B rd, VReg_16B rn) +{ + emit<"0110111000100000101110nnnnnddddd", "d", "n">(rd, rn); +} +void NEG(VReg_4H rd, VReg_4H rn) +{ + emit<"0010111001100000101110nnnnnddddd", "d", "n">(rd, rn); +} +void NEG(VReg_8H rd, VReg_8H rn) +{ + emit<"0110111001100000101110nnnnnddddd", "d", "n">(rd, rn); +} +void NEG(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111010100000101110nnnnnddddd", "d", "n">(rd, rn); +} +void NEG(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111010100000101110nnnnnddddd", "d", "n">(rd, rn); +} +void NEG(VReg_2D rd, VReg_2D rn) +{ + emit<"0110111011100000101110nnnnnddddd", "d", "n">(rd, rn); +} +void NOT(VReg_8B rd, VReg_8B rn) +{ + emit<"0010111000100000010110nnnnnddddd", "d", "n">(rd, rn); +} +void NOT(VReg_16B rd, VReg_16B rn) +{ + emit<"0110111000100000010110nnnnnddddd", "d", "n">(rd, rn); +} +void ORN(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110111mmmmm000111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ORN(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110111mmmmm000111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ORR(VReg_4H rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmChoice<0, 8> amount = 0) +{ + emit<"0000111100000vvv10c101vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void ORR(VReg_8H rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmChoice<0, 8> amount = 0) +{ + emit<"0100111100000vvv10c101vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void ORR(VReg_2S rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmChoice<0, 8, 16, 24> amount = 0) +{ + emit<"0000111100000vvv0cc101vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void ORR(VReg_4S rd, Imm<8> imm, LslSymbol = LslSymbol::LSL, ImmChoice<0, 8, 16, 24> amount = 0) +{ + emit<"0100111100000vvv0cc101vvvvvddddd", "d", "v", "c">(rd, imm, amount); +} +void ORR(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110101mmmmm000111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ORR(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110101mmmmm000111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void PMUL(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm100111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void PMUL(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm100111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void PMULL(VReg_8H rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm111000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void PMULL2(VReg_8H rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm111000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void PMULL(VReg_1Q rd, VReg_1D rn, VReg_1D rm) +{ + emit<"00001110111mmmmm111000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void PMULL2(VReg_1Q rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm111000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void RADDHN(VReg_8B rd, VReg_8H rn, VReg_8H rm) +{ + emit<"00101110001mmmmm010000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void RADDHN2(VReg_16B rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110001mmmmm010000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void RADDHN(VReg_4H rd, VReg_4S rn, VReg_4S rm) +{ + emit<"00101110011mmmmm010000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void RADDHN2(VReg_8H rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110011mmmmm010000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void RADDHN(VReg_2S rd, VReg_2D rn, VReg_2D rm) +{ + emit<"00101110101mmmmm010000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void RADDHN2(VReg_4S rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110101mmmmm010000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void RBIT(VReg_8B rd, VReg_8B rn) +{ + emit<"0010111001100000010110nnnnnddddd", "d", "n">(rd, rn); +} +void RBIT(VReg_16B rd, VReg_16B rn) +{ + emit<"0110111001100000010110nnnnnddddd", "d", "n">(rd, rn); +} +void REV16(VReg_8B rd, VReg_8B rn) +{ + emit<"0000111000100000000110nnnnnddddd", "d", "n">(rd, rn); +} +void REV16(VReg_16B rd, VReg_16B rn) +{ + emit<"0100111000100000000110nnnnnddddd", "d", "n">(rd, rn); +} +void REV32(VReg_8B rd, VReg_8B rn) +{ + emit<"0010111000100000000010nnnnnddddd", "d", "n">(rd, rn); +} +void REV32(VReg_16B rd, VReg_16B rn) +{ + emit<"0110111000100000000010nnnnnddddd", "d", "n">(rd, rn); +} +void REV32(VReg_4H rd, VReg_4H rn) +{ + emit<"0010111001100000000010nnnnnddddd", "d", "n">(rd, rn); +} +void REV32(VReg_8H rd, VReg_8H rn) +{ + emit<"0110111001100000000010nnnnnddddd", "d", "n">(rd, rn); +} +void REV64(VReg_8B rd, VReg_8B rn) +{ + emit<"0000111000100000000010nnnnnddddd", "d", "n">(rd, rn); +} +void REV64(VReg_16B rd, VReg_16B rn) +{ + emit<"0100111000100000000010nnnnnddddd", "d", "n">(rd, rn); +} +void REV64(VReg_4H rd, VReg_4H rn) +{ + emit<"0000111001100000000010nnnnnddddd", "d", "n">(rd, rn); +} +void REV64(VReg_8H rd, VReg_8H rn) +{ + emit<"0100111001100000000010nnnnnddddd", "d", "n">(rd, rn); +} +void REV64(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111010100000000010nnnnnddddd", "d", "n">(rd, rn); +} +void REV64(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111010100000000010nnnnnddddd", "d", "n">(rd, rn); +} +void RSHRN(VReg_8B rd, VReg_8H rn, ImmRange<1, 8> shift) +{ + emit<"0000111100001bbb100011nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void RSHRN2(VReg_16B rd, VReg_8H rn, ImmRange<1, 8> shift) +{ + emit<"0100111100001bbb100011nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void RSHRN(VReg_4H rd, VReg_4S rn, ImmRange<1, 16> shift) +{ + emit<"000011110001hbbb100011nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void RSHRN2(VReg_8H rd, VReg_4S rn, ImmRange<1, 16> shift) +{ + emit<"010011110001hbbb100011nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void RSHRN(VReg_2S rd, VReg_2D rn, ImmRange<1, 32> shift) +{ + emit<"00001111001hhbbb100011nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void RSHRN2(VReg_4S rd, VReg_2D rn, ImmRange<1, 32> shift) +{ + emit<"01001111001hhbbb100011nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void RSUBHN(VReg_8B rd, VReg_8H rn, VReg_8H rm) +{ + emit<"00101110001mmmmm011000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void RSUBHN2(VReg_16B rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110001mmmmm011000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void RSUBHN(VReg_4H rd, VReg_4S rn, VReg_4S rm) +{ + emit<"00101110011mmmmm011000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void RSUBHN2(VReg_8H rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110011mmmmm011000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void RSUBHN(VReg_2S rd, VReg_2D rn, VReg_2D rm) +{ + emit<"00101110101mmmmm011000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void RSUBHN2(VReg_4S rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110101mmmmm011000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABA(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm011111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABA(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm011111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABA(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm011111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABA(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm011111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABA(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm011111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABA(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm011111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABAL(VReg_8H rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm010100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABAL2(VReg_8H rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm010100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABAL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm010100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABAL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm010100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABAL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm010100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABAL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm010100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABD(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm011101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABD(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm011101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABD(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm011101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABD(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm011101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABD(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm011101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABD(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm011101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABDL(VReg_8H rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm011100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABDL2(VReg_8H rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm011100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABDL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm011100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABDL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm011100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABDL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm011100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SABDL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm011100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SADALP(VReg_4H rd, VReg_8B rn) +{ + emit<"0000111000100000011010nnnnnddddd", "d", "n">(rd, rn); +} +void SADALP(VReg_8H rd, VReg_16B rn) +{ + emit<"0100111000100000011010nnnnnddddd", "d", "n">(rd, rn); +} +void SADALP(VReg_2S rd, VReg_4H rn) +{ + emit<"0000111001100000011010nnnnnddddd", "d", "n">(rd, rn); +} +void SADALP(VReg_4S rd, VReg_8H rn) +{ + emit<"0100111001100000011010nnnnnddddd", "d", "n">(rd, rn); +} +void SADALP(VReg_1D rd, VReg_2S rn) +{ + emit<"0000111010100000011010nnnnnddddd", "d", "n">(rd, rn); +} +void SADALP(VReg_2D rd, VReg_4S rn) +{ + emit<"0100111010100000011010nnnnnddddd", "d", "n">(rd, rn); +} +void SADDL(VReg_8H rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm000000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SADDL2(VReg_8H rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm000000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SADDL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm000000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SADDL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm000000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SADDL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm000000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SADDL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm000000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SADDLP(VReg_4H rd, VReg_8B rn) +{ + emit<"0000111000100000001010nnnnnddddd", "d", "n">(rd, rn); +} +void SADDLP(VReg_8H rd, VReg_16B rn) +{ + emit<"0100111000100000001010nnnnnddddd", "d", "n">(rd, rn); +} +void SADDLP(VReg_2S rd, VReg_4H rn) +{ + emit<"0000111001100000001010nnnnnddddd", "d", "n">(rd, rn); +} +void SADDLP(VReg_4S rd, VReg_8H rn) +{ + emit<"0100111001100000001010nnnnnddddd", "d", "n">(rd, rn); +} +void SADDLP(VReg_1D rd, VReg_2S rn) +{ + emit<"0000111010100000001010nnnnnddddd", "d", "n">(rd, rn); +} +void SADDLP(VReg_2D rd, VReg_4S rn) +{ + emit<"0100111010100000001010nnnnnddddd", "d", "n">(rd, rn); +} +void SADDLV(HReg rd, VReg_8B rn) +{ + emit<"0000111000110000001110nnnnnddddd", "d", "n">(rd, rn); +} +void SADDLV(HReg rd, VReg_16B rn) +{ + emit<"0100111000110000001110nnnnnddddd", "d", "n">(rd, rn); +} +void SADDLV(SReg rd, VReg_4H rn) +{ + emit<"0000111001110000001110nnnnnddddd", "d", "n">(rd, rn); +} +void SADDLV(SReg rd, VReg_8H rn) +{ + emit<"0100111001110000001110nnnnnddddd", "d", "n">(rd, rn); +} +void SADDLV(DReg rd, VReg_4S rn) +{ + emit<"0100111010110000001110nnnnnddddd", "d", "n">(rd, rn); +} +void SADDW(VReg_8H rd, VReg_8H rn, VReg_8B rm) +{ + emit<"00001110001mmmmm000100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SADDW2(VReg_8H rd, VReg_8H rn, VReg_16B rm) +{ + emit<"01001110001mmmmm000100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SADDW(VReg_4S rd, VReg_4S rn, VReg_4H rm) +{ + emit<"00001110011mmmmm000100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SADDW2(VReg_4S rd, VReg_4S rn, VReg_8H rm) +{ + emit<"01001110011mmmmm000100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SADDW(VReg_2D rd, VReg_2D rn, VReg_2S rm) +{ + emit<"00001110101mmmmm000100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SADDW2(VReg_2D rd, VReg_2D rn, VReg_4S rm) +{ + emit<"01001110101mmmmm000100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SCVTF(SReg rd, WReg wn, ImmRange<1, 32> fbits) +{ + emit<"0001111000000010SSSSSSnnnnnddddd", "d", "n", "S">(rd, wn, 64 - fbits.value()); +} +void SCVTF(DReg rd, WReg wn, ImmRange<1, 32> fbits) +{ + emit<"0001111001000010SSSSSSnnnnnddddd", "d", "n", "S">(rd, wn, 64 - fbits.value()); +} +void SCVTF(SReg rd, XReg xn, ImmRange<1, 64> fbits) +{ + emit<"1001111000000010SSSSSSnnnnnddddd", "d", "n", "S">(rd, xn, 64 - fbits.value()); +} +void SCVTF(DReg rd, XReg xn, ImmRange<1, 64> fbits) +{ + emit<"1001111001000010SSSSSSnnnnnddddd", "d", "n", "S">(rd, xn, 64 - fbits.value()); +} +void SCVTF(SReg rd, WReg wn) +{ + emit<"0001111000100010000000nnnnnddddd", "d", "n">(rd, wn); +} +void SCVTF(DReg rd, WReg wn) +{ + emit<"0001111001100010000000nnnnnddddd", "d", "n">(rd, wn); +} +void SCVTF(SReg rd, XReg xn) +{ + emit<"1001111000100010000000nnnnnddddd", "d", "n">(rd, xn); +} +void SCVTF(DReg rd, XReg xn) +{ + emit<"1001111001100010000000nnnnnddddd", "d", "n">(rd, xn); +} +void SCVTF(HReg rd, HReg rn, ImmRange<1, 16> fbits) +{ + emit<"010111110001hbbb111001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - fbits.value()); +} +void SCVTF(SReg rd, SReg rn, ImmRange<1, 32> fbits) +{ + emit<"01011111001hhbbb111001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - fbits.value()); +} +void SCVTF(DReg rd, DReg rn, ImmRange<1, 64> fbits) +{ + emit<"0101111101hhhbbb111001nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - fbits.value()); +} +void SCVTF(VReg_4H rd, VReg_4H rn, ImmRange<1, 16> fbits) +{ + emit<"000011110001hbbb111001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - fbits.value()); +} +void SCVTF(VReg_8H rd, VReg_8H rn, ImmRange<1, 16> fbits) +{ + emit<"010011110001hbbb111001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - fbits.value()); +} +void SCVTF(VReg_2S rd, VReg_2S rn, ImmRange<1, 32> fbits) +{ + emit<"00001111001hhbbb111001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - fbits.value()); +} +void SCVTF(VReg_4S rd, VReg_4S rn, ImmRange<1, 32> fbits) +{ + emit<"01001111001hhbbb111001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - fbits.value()); +} +void SCVTF(VReg_2D rd, VReg_2D rn, ImmRange<1, 64> fbits) +{ + emit<"0100111101hhhbbb111001nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - fbits.value()); +} +void SCVTF(SReg rd, SReg rn) +{ + emit<"0101111000100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void SCVTF(DReg rd, DReg rn) +{ + emit<"0101111001100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void SCVTF(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111000100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void SCVTF(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111000100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void SCVTF(VReg_2D rd, VReg_2D rn) +{ + emit<"0100111001100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void SHA1C(QReg rd, SReg rn, VReg_4S rm) +{ + emit<"01011110000mmmmm000000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHA1H(SReg rd, SReg rn) +{ + emit<"0101111000101000000010nnnnnddddd", "d", "n">(rd, rn); +} +void SHA1M(QReg rd, SReg rn, VReg_4S rm) +{ + emit<"01011110000mmmmm001000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHA1P(QReg rd, SReg rn, VReg_4S rm) +{ + emit<"01011110000mmmmm000100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHA1SU0(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01011110000mmmmm001100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHA1SU1(VReg_4S rd, VReg_4S rn) +{ + emit<"0101111000101000000110nnnnnddddd", "d", "n">(rd, rn); +} +void SHA256H(QReg rd, QReg rn, VReg_4S rm) +{ + emit<"01011110000mmmmm010000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHA256H2(QReg rd, QReg rn, VReg_4S rm) +{ + emit<"01011110000mmmmm010100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHA256SU0(VReg_4S rd, VReg_4S rn) +{ + emit<"0101111000101000001010nnnnnddddd", "d", "n">(rd, rn); +} +void SHA256SU1(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01011110000mmmmm011000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHADD(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm000001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHADD(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm000001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHADD(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm000001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHADD(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm000001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHADD(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm000001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHADD(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm000001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHL(DReg rd, DReg rn, ImmRange<0, 63> shift) +{ + emit<"0101111101hhhbbb010101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SHL(VReg_8B rd, VReg_8B rn, ImmRange<0, 7> shift) +{ + emit<"0000111100001bbb010101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SHL(VReg_16B rd, VReg_16B rn, ImmRange<0, 7> shift) +{ + emit<"0100111100001bbb010101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SHL(VReg_4H rd, VReg_4H rn, ImmRange<0, 15> shift) +{ + emit<"000011110001hbbb010101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SHL(VReg_8H rd, VReg_8H rn, ImmRange<0, 15> shift) +{ + emit<"010011110001hbbb010101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SHL(VReg_2S rd, VReg_2S rn, ImmRange<0, 31> shift) +{ + emit<"00001111001hhbbb010101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SHL(VReg_4S rd, VReg_4S rn, ImmRange<0, 31> shift) +{ + emit<"01001111001hhbbb010101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SHL(VReg_2D rd, VReg_2D rn, ImmRange<0, 63> shift) +{ + emit<"0100111101hhhbbb010101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SHLL(VReg_8H rd, VReg_8B rn, ImmConst<8>) +{ + emit<"0010111000100001001110nnnnnddddd", "d", "n">(rd, rn); +} +void SHLL2(VReg_8H rd, VReg_16B rn, ImmConst<8>) +{ + emit<"0110111000100001001110nnnnnddddd", "d", "n">(rd, rn); +} +void SHLL(VReg_4S rd, VReg_4H rn, ImmConst<16>) +{ + emit<"0010111001100001001110nnnnnddddd", "d", "n">(rd, rn); +} +void SHLL2(VReg_4S rd, VReg_8H rn, ImmConst<16>) +{ + emit<"0110111001100001001110nnnnnddddd", "d", "n">(rd, rn); +} +void SHLL(VReg_2D rd, VReg_2S rn, ImmConst<32>) +{ + emit<"0010111010100001001110nnnnnddddd", "d", "n">(rd, rn); +} +void SHLL2(VReg_2D rd, VReg_4S rn, ImmConst<32>) +{ + emit<"0110111010100001001110nnnnnddddd", "d", "n">(rd, rn); +} +void SHRN(VReg_8B rd, VReg_8H rn, ImmRange<1, 8> shift) +{ + emit<"0000111100001bbb100001nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SHRN2(VReg_16B rd, VReg_8H rn, ImmRange<1, 8> shift) +{ + emit<"0100111100001bbb100001nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SHRN(VReg_4H rd, VReg_4S rn, ImmRange<1, 16> shift) +{ + emit<"000011110001hbbb100001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SHRN2(VReg_8H rd, VReg_4S rn, ImmRange<1, 16> shift) +{ + emit<"010011110001hbbb100001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SHRN(VReg_2S rd, VReg_2D rn, ImmRange<1, 32> shift) +{ + emit<"00001111001hhbbb100001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SHRN2(VReg_4S rd, VReg_2D rn, ImmRange<1, 32> shift) +{ + emit<"01001111001hhbbb100001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SHSUB(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm001001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHSUB(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm001001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHSUB(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm001001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHSUB(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm001001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHSUB(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm001001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SHSUB(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm001001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SLI(DReg rd, DReg rn, ImmRange<0, 63> shift) +{ + emit<"0111111101hhhbbb010101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SLI(VReg_8B rd, VReg_8B rn, ImmRange<0, 7> shift) +{ + emit<"0010111100001bbb010101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SLI(VReg_16B rd, VReg_16B rn, ImmRange<0, 7> shift) +{ + emit<"0110111100001bbb010101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SLI(VReg_4H rd, VReg_4H rn, ImmRange<0, 15> shift) +{ + emit<"001011110001hbbb010101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SLI(VReg_8H rd, VReg_8H rn, ImmRange<0, 15> shift) +{ + emit<"011011110001hbbb010101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SLI(VReg_2S rd, VReg_2S rn, ImmRange<0, 31> shift) +{ + emit<"00101111001hhbbb010101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SLI(VReg_4S rd, VReg_4S rn, ImmRange<0, 31> shift) +{ + emit<"01101111001hhbbb010101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SLI(VReg_2D rd, VReg_2D rn, ImmRange<0, 63> shift) +{ + emit<"0110111101hhhbbb010101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SMAX(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm011001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMAX(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm011001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMAX(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm011001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMAX(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm011001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMAX(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm011001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMAX(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm011001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMAXP(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm101001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMAXP(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm101001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMAXP(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm101001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMAXP(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm101001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMAXP(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm101001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMAXP(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm101001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMAXV(BReg rd, VReg_8B rn) +{ + emit<"0000111000110000101010nnnnnddddd", "d", "n">(rd, rn); +} +void SMAXV(BReg rd, VReg_16B rn) +{ + emit<"0100111000110000101010nnnnnddddd", "d", "n">(rd, rn); +} +void SMAXV(HReg rd, VReg_4H rn) +{ + emit<"0000111001110000101010nnnnnddddd", "d", "n">(rd, rn); +} +void SMAXV(HReg rd, VReg_8H rn) +{ + emit<"0100111001110000101010nnnnnddddd", "d", "n">(rd, rn); +} +void SMAXV(SReg rd, VReg_4S rn) +{ + emit<"0100111010110000101010nnnnnddddd", "d", "n">(rd, rn); +} +void SMIN(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm011011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMIN(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm011011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMIN(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm011011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMIN(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm011011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMIN(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm011011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMIN(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm011011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMINP(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm101011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMINP(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm101011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMINP(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm101011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMINP(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm101011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMINP(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm101011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMINP(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm101011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMINV(BReg rd, VReg_8B rn) +{ + emit<"0000111000110001101010nnnnnddddd", "d", "n">(rd, rn); +} +void SMINV(BReg rd, VReg_16B rn) +{ + emit<"0100111000110001101010nnnnnddddd", "d", "n">(rd, rn); +} +void SMINV(HReg rd, VReg_4H rn) +{ + emit<"0000111001110001101010nnnnnddddd", "d", "n">(rd, rn); +} +void SMINV(HReg rd, VReg_8H rn) +{ + emit<"0100111001110001101010nnnnnddddd", "d", "n">(rd, rn); +} +void SMINV(SReg rd, VReg_4S rn) +{ + emit<"0100111010110001101010nnnnnddddd", "d", "n">(rd, rn); +} +void SMLAL(VReg_4S rd, VReg_4H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0000111101LMmmmm0010H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SMLAL2(VReg_4S rd, VReg_8H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0100111101LMmmmm0010H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SMLAL(VReg_2D rd, VReg_2S rn, SElem em) +{ + emit<"0000111110LMmmmm0010H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SMLAL2(VReg_2D rd, VReg_4S rn, SElem em) +{ + emit<"0100111110LMmmmm0010H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SMLAL(VReg_8H rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm100000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMLAL2(VReg_8H rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm100000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMLAL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm100000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMLAL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm100000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMLAL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm100000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMLAL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm100000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMLSL(VReg_4S rd, VReg_4H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0000111101LMmmmm0110H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SMLSL2(VReg_4S rd, VReg_8H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0100111101LMmmmm0110H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SMLSL(VReg_2D rd, VReg_2S rn, SElem em) +{ + emit<"0000111110LMmmmm0110H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SMLSL2(VReg_2D rd, VReg_4S rn, SElem em) +{ + emit<"0100111110LMmmmm0110H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SMLSL(VReg_8H rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm101000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMLSL2(VReg_8H rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm101000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMLSL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm101000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMLSL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm101000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMLSL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm101000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMLSL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm101000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMOV(WReg wd, BElem en) +{ + emit<"00001110000xxxx1001011nnnnnddddd", "d", "n", "x">(wd, en.reg_index(), en.elem_index()); +} +void SMOV(WReg wd, HElem en) +{ + emit<"00001110000xxx10001011nnnnnddddd", "d", "n", "x">(wd, en.reg_index(), en.elem_index()); +} +void SMOV(XReg xd, BElem en) +{ + emit<"01001110000xxxx1001011nnnnnddddd", "d", "n", "x">(xd, en.reg_index(), en.elem_index()); +} +void SMOV(XReg xd, HElem en) +{ + emit<"01001110000xxx10001011nnnnnddddd", "d", "n", "x">(xd, en.reg_index(), en.elem_index()); +} +void SMOV(XReg xd, SElem en) +{ + emit<"01001110000xx100001011nnnnnddddd", "d", "n", "x">(xd, en.reg_index(), en.elem_index()); +} +void SMULL(VReg_4S rd, VReg_4H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0000111101LMmmmm1010H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SMULL2(VReg_4S rd, VReg_8H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0100111101LMmmmm1010H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SMULL(VReg_2D rd, VReg_2S rn, SElem em) +{ + emit<"0000111110LMmmmm1010H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SMULL2(VReg_2D rd, VReg_4S rn, SElem em) +{ + emit<"0100111110LMmmmm1010H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SMULL(VReg_8H rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm110000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMULL2(VReg_8H rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm110000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMULL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm110000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMULL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm110000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMULL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm110000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SMULL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm110000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQABS(BReg rd, BReg rn) +{ + emit<"0101111000100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQABS(HReg rd, HReg rn) +{ + emit<"0101111001100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQABS(SReg rd, SReg rn) +{ + emit<"0101111010100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQABS(DReg rd, DReg rn) +{ + emit<"0101111011100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQABS(VReg_8B rd, VReg_8B rn) +{ + emit<"0000111000100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQABS(VReg_16B rd, VReg_16B rn) +{ + emit<"0100111000100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQABS(VReg_4H rd, VReg_4H rn) +{ + emit<"0000111001100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQABS(VReg_8H rd, VReg_8H rn) +{ + emit<"0100111001100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQABS(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111010100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQABS(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111010100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQABS(VReg_2D rd, VReg_2D rn) +{ + emit<"0100111011100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQADD(BReg rd, BReg rn, BReg rm) +{ + emit<"01011110001mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQADD(HReg rd, HReg rn, HReg rm) +{ + emit<"01011110011mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQADD(SReg rd, SReg rn, SReg rm) +{ + emit<"01011110101mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQADD(DReg rd, DReg rn, DReg rm) +{ + emit<"01011110111mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQADD(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQADD(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQADD(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQADD(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQADD(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQADD(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQADD(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMLAL(SReg rd, HReg rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0101111101LMmmmm0011H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SQDMLAL(DReg rd, SReg rn, SElem em) +{ + emit<"0101111110LMmmmm0011H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SQDMLAL(VReg_4S rd, VReg_4H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0000111101LMmmmm0011H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SQDMLAL2(VReg_4S rd, VReg_8H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0100111101LMmmmm0011H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SQDMLAL(VReg_2D rd, VReg_2S rn, SElem em) +{ + emit<"0000111110LMmmmm0011H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SQDMLAL2(VReg_2D rd, VReg_4S rn, SElem em) +{ + emit<"0100111110LMmmmm0011H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SQDMLAL(SReg rd, HReg rn, HReg rm) +{ + emit<"01011110011mmmmm100100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMLAL(DReg rd, SReg rn, SReg rm) +{ + emit<"01011110101mmmmm100100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMLAL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm100100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMLAL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm100100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMLAL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm100100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMLAL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm100100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMLSL(SReg rd, HReg rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0101111101LMmmmm0111H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SQDMLSL(DReg rd, SReg rn, SElem em) +{ + emit<"0101111110LMmmmm0111H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SQDMLSL(VReg_4S rd, VReg_4H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0000111101LMmmmm0111H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SQDMLSL2(VReg_4S rd, VReg_8H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0100111101LMmmmm0111H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SQDMLSL(VReg_2D rd, VReg_2S rn, SElem em) +{ + emit<"0000111110LMmmmm0111H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SQDMLSL2(VReg_2D rd, VReg_4S rn, SElem em) +{ + emit<"0100111110LMmmmm0111H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SQDMLSL(SReg rd, HReg rn, HReg rm) +{ + emit<"01011110011mmmmm101100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMLSL(DReg rd, SReg rn, SReg rm) +{ + emit<"01011110101mmmmm101100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMLSL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm101100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMLSL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm101100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMLSL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm101100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMLSL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm101100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMULH(HReg rd, HReg rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0101111101LMmmmm1100H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SQDMULH(SReg rd, SReg rn, SElem em) +{ + emit<"0101111110LMmmmm1100H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SQDMULH(VReg_4H rd, VReg_4H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0000111101LMmmmm1100H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SQDMULH(VReg_8H rd, VReg_8H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0100111101LMmmmm1100H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SQDMULH(VReg_2S rd, VReg_2S rn, SElem em) +{ + emit<"0000111110LMmmmm1100H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SQDMULH(VReg_4S rd, VReg_4S rn, SElem em) +{ + emit<"0100111110LMmmmm1100H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SQDMULH(HReg rd, HReg rn, HReg rm) +{ + emit<"01011110011mmmmm101101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMULH(SReg rd, SReg rn, SReg rm) +{ + emit<"01011110101mmmmm101101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMULH(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm101101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMULH(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm101101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMULH(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm101101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMULH(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm101101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMULL(SReg rd, HReg rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0101111101LMmmmm1011H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SQDMULL(DReg rd, SReg rn, SElem em) +{ + emit<"0101111110LMmmmm1011H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SQDMULL(VReg_4S rd, VReg_4H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0000111101LMmmmm1011H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SQDMULL2(VReg_4S rd, VReg_8H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0100111101LMmmmm1011H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SQDMULL(VReg_2D rd, VReg_2S rn, SElem em) +{ + emit<"0000111110LMmmmm1011H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SQDMULL2(VReg_2D rd, VReg_4S rn, SElem em) +{ + emit<"0100111110LMmmmm1011H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SQDMULL(SReg rd, HReg rn, HReg rm) +{ + emit<"01011110011mmmmm110100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMULL(DReg rd, SReg rn, SReg rm) +{ + emit<"01011110101mmmmm110100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMULL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm110100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMULL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm110100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMULL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm110100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQDMULL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm110100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQNEG(BReg rd, BReg rn) +{ + emit<"0111111000100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQNEG(HReg rd, HReg rn) +{ + emit<"0111111001100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQNEG(SReg rd, SReg rn) +{ + emit<"0111111010100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQNEG(DReg rd, DReg rn) +{ + emit<"0111111011100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQNEG(VReg_8B rd, VReg_8B rn) +{ + emit<"0010111000100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQNEG(VReg_16B rd, VReg_16B rn) +{ + emit<"0110111000100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQNEG(VReg_4H rd, VReg_4H rn) +{ + emit<"0010111001100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQNEG(VReg_8H rd, VReg_8H rn) +{ + emit<"0110111001100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQNEG(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111010100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQNEG(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111010100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQNEG(VReg_2D rd, VReg_2D rn) +{ + emit<"0110111011100000011110nnnnnddddd", "d", "n">(rd, rn); +} +void SQRDMULH(HReg rd, HReg rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0101111101LMmmmm1101H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SQRDMULH(SReg rd, SReg rn, SElem em) +{ + emit<"0101111110LMmmmm1101H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SQRDMULH(VReg_4H rd, VReg_4H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0000111101LMmmmm1101H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SQRDMULH(VReg_8H rd, VReg_8H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0100111101LMmmmm1101H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void SQRDMULH(VReg_2S rd, VReg_2S rn, SElem em) +{ + emit<"0000111110LMmmmm1101H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SQRDMULH(VReg_4S rd, VReg_4S rn, SElem em) +{ + emit<"0100111110LMmmmm1101H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void SQRDMULH(HReg rd, HReg rn, HReg rm) +{ + emit<"01111110011mmmmm101101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRDMULH(SReg rd, SReg rn, SReg rm) +{ + emit<"01111110101mmmmm101101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRDMULH(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm101101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRDMULH(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm101101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRDMULH(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm101101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRDMULH(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm101101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRSHL(BReg rd, BReg rn, BReg rm) +{ + emit<"01011110001mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRSHL(HReg rd, HReg rn, HReg rm) +{ + emit<"01011110011mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRSHL(SReg rd, SReg rn, SReg rm) +{ + emit<"01011110101mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRSHL(DReg rd, DReg rn, DReg rm) +{ + emit<"01011110111mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRSHL(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRSHL(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRSHL(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRSHL(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRSHL(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRSHL(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRSHL(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQRSHRN(BReg rd, HReg rn, ImmRange<1, 8> shift) +{ + emit<"0101111100001bbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SQRSHRN(HReg rd, SReg rn, ImmRange<1, 16> shift) +{ + emit<"010111110001hbbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SQRSHRN(SReg rd, DReg rn, ImmRange<1, 32> shift) +{ + emit<"01011111001hhbbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SQRSHRN(VReg_8B rd, VReg_8H rn, ImmRange<1, 8> shift) +{ + emit<"0000111100001bbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SQRSHRN2(VReg_16B rd, VReg_8H rn, ImmRange<1, 8> shift) +{ + emit<"0100111100001bbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SQRSHRN(VReg_4H rd, VReg_4S rn, ImmRange<1, 16> shift) +{ + emit<"000011110001hbbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SQRSHRN2(VReg_8H rd, VReg_4S rn, ImmRange<1, 16> shift) +{ + emit<"010011110001hbbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SQRSHRN(VReg_2S rd, VReg_2D rn, ImmRange<1, 32> shift) +{ + emit<"00001111001hhbbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SQRSHRN2(VReg_4S rd, VReg_2D rn, ImmRange<1, 32> shift) +{ + emit<"01001111001hhbbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SQRSHRUN(BReg rd, HReg rn, ImmRange<1, 8> shift) +{ + emit<"0111111100001bbb100011nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SQRSHRUN(HReg rd, SReg rn, ImmRange<1, 16> shift) +{ + emit<"011111110001hbbb100011nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SQRSHRUN(SReg rd, DReg rn, ImmRange<1, 32> shift) +{ + emit<"01111111001hhbbb100011nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SQRSHRUN(VReg_8B rd, VReg_8H rn, ImmRange<1, 8> shift) +{ + emit<"0010111100001bbb100011nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SQRSHRUN2(VReg_16B rd, VReg_8H rn, ImmRange<1, 8> shift) +{ + emit<"0110111100001bbb100011nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SQRSHRUN(VReg_4H rd, VReg_4S rn, ImmRange<1, 16> shift) +{ + emit<"001011110001hbbb100011nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SQRSHRUN2(VReg_8H rd, VReg_4S rn, ImmRange<1, 16> shift) +{ + emit<"011011110001hbbb100011nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SQRSHRUN(VReg_2S rd, VReg_2D rn, ImmRange<1, 32> shift) +{ + emit<"00101111001hhbbb100011nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SQRSHRUN2(VReg_4S rd, VReg_2D rn, ImmRange<1, 32> shift) +{ + emit<"01101111001hhbbb100011nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SQSHL(BReg rd, BReg rn, ImmRange<0, 7> shift) +{ + emit<"0101111100001bbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHL(HReg rd, HReg rn, ImmRange<0, 15> shift) +{ + emit<"010111110001hbbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHL(SReg rd, SReg rn, ImmRange<0, 31> shift) +{ + emit<"01011111001hhbbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHL(DReg rd, DReg rn, ImmRange<0, 63> shift) +{ + emit<"0101111101hhhbbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHL(VReg_8B rd, VReg_8B rn, ImmRange<0, 7> shift) +{ + emit<"0000111100001bbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHL(VReg_16B rd, VReg_16B rn, ImmRange<0, 7> shift) +{ + emit<"0100111100001bbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHL(VReg_4H rd, VReg_4H rn, ImmRange<0, 15> shift) +{ + emit<"000011110001hbbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHL(VReg_8H rd, VReg_8H rn, ImmRange<0, 15> shift) +{ + emit<"010011110001hbbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHL(VReg_2S rd, VReg_2S rn, ImmRange<0, 31> shift) +{ + emit<"00001111001hhbbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHL(VReg_4S rd, VReg_4S rn, ImmRange<0, 31> shift) +{ + emit<"01001111001hhbbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHL(VReg_2D rd, VReg_2D rn, ImmRange<0, 63> shift) +{ + emit<"0100111101hhhbbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHL(BReg rd, BReg rn, BReg rm) +{ + emit<"01011110001mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSHL(HReg rd, HReg rn, HReg rm) +{ + emit<"01011110011mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSHL(SReg rd, SReg rn, SReg rm) +{ + emit<"01011110101mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSHL(DReg rd, DReg rn, DReg rm) +{ + emit<"01011110111mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSHL(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSHL(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSHL(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSHL(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSHL(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSHL(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSHL(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSHLU(BReg rd, BReg rn, ImmRange<0, 7> shift) +{ + emit<"0111111100001bbb011001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHLU(HReg rd, HReg rn, ImmRange<0, 15> shift) +{ + emit<"011111110001hbbb011001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHLU(SReg rd, SReg rn, ImmRange<0, 31> shift) +{ + emit<"01111111001hhbbb011001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHLU(DReg rd, DReg rn, ImmRange<0, 63> shift) +{ + emit<"0111111101hhhbbb011001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHLU(VReg_8B rd, VReg_8B rn, ImmRange<0, 7> shift) +{ + emit<"0010111100001bbb011001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHLU(VReg_16B rd, VReg_16B rn, ImmRange<0, 7> shift) +{ + emit<"0110111100001bbb011001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHLU(VReg_4H rd, VReg_4H rn, ImmRange<0, 15> shift) +{ + emit<"001011110001hbbb011001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHLU(VReg_8H rd, VReg_8H rn, ImmRange<0, 15> shift) +{ + emit<"011011110001hbbb011001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHLU(VReg_2S rd, VReg_2S rn, ImmRange<0, 31> shift) +{ + emit<"00101111001hhbbb011001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHLU(VReg_4S rd, VReg_4S rn, ImmRange<0, 31> shift) +{ + emit<"01101111001hhbbb011001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHLU(VReg_2D rd, VReg_2D rn, ImmRange<0, 63> shift) +{ + emit<"0110111101hhhbbb011001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SQSHRN(BReg rd, HReg rn, ImmRange<1, 8> shift) +{ + emit<"0101111100001bbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SQSHRN(HReg rd, SReg rn, ImmRange<1, 16> shift) +{ + emit<"010111110001hbbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SQSHRN(SReg rd, DReg rn, ImmRange<1, 32> shift) +{ + emit<"01011111001hhbbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SQSHRN(VReg_8B rd, VReg_8H rn, ImmRange<1, 8> shift) +{ + emit<"0000111100001bbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SQSHRN2(VReg_16B rd, VReg_8H rn, ImmRange<1, 8> shift) +{ + emit<"0100111100001bbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SQSHRN(VReg_4H rd, VReg_4S rn, ImmRange<1, 16> shift) +{ + emit<"000011110001hbbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SQSHRN2(VReg_8H rd, VReg_4S rn, ImmRange<1, 16> shift) +{ + emit<"010011110001hbbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SQSHRN(VReg_2S rd, VReg_2D rn, ImmRange<1, 32> shift) +{ + emit<"00001111001hhbbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SQSHRN2(VReg_4S rd, VReg_2D rn, ImmRange<1, 32> shift) +{ + emit<"01001111001hhbbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SQSHRUN(BReg rd, HReg rn, ImmRange<1, 8> shift) +{ + emit<"0111111100001bbb100001nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SQSHRUN(HReg rd, SReg rn, ImmRange<1, 16> shift) +{ + emit<"011111110001hbbb100001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SQSHRUN(SReg rd, DReg rn, ImmRange<1, 32> shift) +{ + emit<"01111111001hhbbb100001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SQSHRUN(VReg_8B rd, VReg_8H rn, ImmRange<1, 8> shift) +{ + emit<"0010111100001bbb100001nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SQSHRUN2(VReg_16B rd, VReg_8H rn, ImmRange<1, 8> shift) +{ + emit<"0110111100001bbb100001nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SQSHRUN(VReg_4H rd, VReg_4S rn, ImmRange<1, 16> shift) +{ + emit<"001011110001hbbb100001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SQSHRUN2(VReg_8H rd, VReg_4S rn, ImmRange<1, 16> shift) +{ + emit<"011011110001hbbb100001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SQSHRUN(VReg_2S rd, VReg_2D rn, ImmRange<1, 32> shift) +{ + emit<"00101111001hhbbb100001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SQSHRUN2(VReg_4S rd, VReg_2D rn, ImmRange<1, 32> shift) +{ + emit<"01101111001hhbbb100001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SQSUB(BReg rd, BReg rn, BReg rm) +{ + emit<"01011110001mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSUB(HReg rd, HReg rn, HReg rm) +{ + emit<"01011110011mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSUB(SReg rd, SReg rn, SReg rm) +{ + emit<"01011110101mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSUB(DReg rd, DReg rn, DReg rm) +{ + emit<"01011110111mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSUB(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSUB(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSUB(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSUB(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSUB(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSUB(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQSUB(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SQXTN(BReg rd, HReg rn) +{ + emit<"0101111000100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTN(HReg rd, SReg rn) +{ + emit<"0101111001100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTN(SReg rd, DReg rn) +{ + emit<"0101111010100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTN(VReg_8B rd, VReg_8H rn) +{ + emit<"0000111000100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTN2(VReg_16B rd, VReg_8H rn) +{ + emit<"0100111000100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTN(VReg_4H rd, VReg_4S rn) +{ + emit<"0000111001100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTN2(VReg_8H rd, VReg_4S rn) +{ + emit<"0100111001100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTN(VReg_2S rd, VReg_2D rn) +{ + emit<"0000111010100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTN2(VReg_4S rd, VReg_2D rn) +{ + emit<"0100111010100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTUN(BReg rd, HReg rn) +{ + emit<"0111111000100001001010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTUN(HReg rd, SReg rn) +{ + emit<"0111111001100001001010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTUN(SReg rd, DReg rn) +{ + emit<"0111111010100001001010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTUN(VReg_8B rd, VReg_8H rn) +{ + emit<"0010111000100001001010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTUN2(VReg_16B rd, VReg_8H rn) +{ + emit<"0110111000100001001010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTUN(VReg_4H rd, VReg_4S rn) +{ + emit<"0010111001100001001010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTUN2(VReg_8H rd, VReg_4S rn) +{ + emit<"0110111001100001001010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTUN(VReg_2S rd, VReg_2D rn) +{ + emit<"0010111010100001001010nnnnnddddd", "d", "n">(rd, rn); +} +void SQXTUN2(VReg_4S rd, VReg_2D rn) +{ + emit<"0110111010100001001010nnnnnddddd", "d", "n">(rd, rn); +} +void SRHADD(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm000101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SRHADD(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm000101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SRHADD(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm000101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SRHADD(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm000101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SRHADD(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm000101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SRHADD(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm000101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SRI(DReg rd, DReg rn, ImmRange<1, 64> shift) +{ + emit<"0111111101hhhbbb010001nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void SRI(VReg_8B rd, VReg_8B rn, ImmRange<1, 8> shift) +{ + emit<"0010111100001bbb010001nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SRI(VReg_16B rd, VReg_16B rn, ImmRange<1, 8> shift) +{ + emit<"0110111100001bbb010001nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SRI(VReg_4H rd, VReg_4H rn, ImmRange<1, 16> shift) +{ + emit<"001011110001hbbb010001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SRI(VReg_8H rd, VReg_8H rn, ImmRange<1, 16> shift) +{ + emit<"011011110001hbbb010001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SRI(VReg_2S rd, VReg_2S rn, ImmRange<1, 32> shift) +{ + emit<"00101111001hhbbb010001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SRI(VReg_4S rd, VReg_4S rn, ImmRange<1, 32> shift) +{ + emit<"01101111001hhbbb010001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SRI(VReg_2D rd, VReg_2D rn, ImmRange<1, 64> shift) +{ + emit<"0110111101hhhbbb010001nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void SRSHL(DReg rd, DReg rn, DReg rm) +{ + emit<"01011110111mmmmm010101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SRSHL(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm010101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SRSHL(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm010101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SRSHL(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm010101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SRSHL(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm010101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SRSHL(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm010101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SRSHL(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm010101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SRSHL(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm010101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SRSHR(DReg rd, DReg rn, ImmRange<1, 64> shift) +{ + emit<"0101111101hhhbbb001001nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void SRSHR(VReg_8B rd, VReg_8B rn, ImmRange<1, 8> shift) +{ + emit<"0000111100001bbb001001nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SRSHR(VReg_16B rd, VReg_16B rn, ImmRange<1, 8> shift) +{ + emit<"0100111100001bbb001001nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SRSHR(VReg_4H rd, VReg_4H rn, ImmRange<1, 16> shift) +{ + emit<"000011110001hbbb001001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SRSHR(VReg_8H rd, VReg_8H rn, ImmRange<1, 16> shift) +{ + emit<"010011110001hbbb001001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SRSHR(VReg_2S rd, VReg_2S rn, ImmRange<1, 32> shift) +{ + emit<"00001111001hhbbb001001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SRSHR(VReg_4S rd, VReg_4S rn, ImmRange<1, 32> shift) +{ + emit<"01001111001hhbbb001001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SRSHR(VReg_2D rd, VReg_2D rn, ImmRange<1, 64> shift) +{ + emit<"0100111101hhhbbb001001nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void SRSRA(DReg rd, DReg rn, ImmRange<1, 64> shift) +{ + emit<"0101111101hhhbbb001101nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void SRSRA(VReg_8B rd, VReg_8B rn, ImmRange<1, 8> shift) +{ + emit<"0000111100001bbb001101nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SRSRA(VReg_16B rd, VReg_16B rn, ImmRange<1, 8> shift) +{ + emit<"0100111100001bbb001101nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SRSRA(VReg_4H rd, VReg_4H rn, ImmRange<1, 16> shift) +{ + emit<"000011110001hbbb001101nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SRSRA(VReg_8H rd, VReg_8H rn, ImmRange<1, 16> shift) +{ + emit<"010011110001hbbb001101nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SRSRA(VReg_2S rd, VReg_2S rn, ImmRange<1, 32> shift) +{ + emit<"00001111001hhbbb001101nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SRSRA(VReg_4S rd, VReg_4S rn, ImmRange<1, 32> shift) +{ + emit<"01001111001hhbbb001101nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SRSRA(VReg_2D rd, VReg_2D rn, ImmRange<1, 64> shift) +{ + emit<"0100111101hhhbbb001101nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void SSHL(DReg rd, DReg rn, DReg rm) +{ + emit<"01011110111mmmmm010001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSHL(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm010001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSHL(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm010001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSHL(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm010001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSHL(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm010001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSHL(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm010001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSHL(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm010001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSHL(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110111mmmmm010001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSHLL(VReg_8H rd, VReg_8B rn, ImmRange<0, 7> shift) +{ + emit<"0000111100001bbb101001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SSHLL2(VReg_8H rd, VReg_16B rn, ImmRange<0, 7> shift) +{ + emit<"0100111100001bbb101001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SSHLL(VReg_4S rd, VReg_4H rn, ImmRange<0, 15> shift) +{ + emit<"000011110001hbbb101001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SSHLL2(VReg_4S rd, VReg_8H rn, ImmRange<0, 15> shift) +{ + emit<"010011110001hbbb101001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SSHLL(VReg_2D rd, VReg_2S rn, ImmRange<0, 31> shift) +{ + emit<"00001111001hhbbb101001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SSHLL2(VReg_2D rd, VReg_4S rn, ImmRange<0, 31> shift) +{ + emit<"01001111001hhbbb101001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void SSHR(DReg rd, DReg rn, ImmRange<1, 64> shift) +{ + emit<"0101111101hhhbbb000001nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void SSHR(VReg_8B rd, VReg_8B rn, ImmRange<1, 8> shift) +{ + emit<"0000111100001bbb000001nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SSHR(VReg_16B rd, VReg_16B rn, ImmRange<1, 8> shift) +{ + emit<"0100111100001bbb000001nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SSHR(VReg_4H rd, VReg_4H rn, ImmRange<1, 16> shift) +{ + emit<"000011110001hbbb000001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SSHR(VReg_8H rd, VReg_8H rn, ImmRange<1, 16> shift) +{ + emit<"010011110001hbbb000001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SSHR(VReg_2S rd, VReg_2S rn, ImmRange<1, 32> shift) +{ + emit<"00001111001hhbbb000001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SSHR(VReg_4S rd, VReg_4S rn, ImmRange<1, 32> shift) +{ + emit<"01001111001hhbbb000001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SSHR(VReg_2D rd, VReg_2D rn, ImmRange<1, 64> shift) +{ + emit<"0100111101hhhbbb000001nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void SSRA(DReg rd, DReg rn, ImmRange<1, 64> shift) +{ + emit<"0101111101hhhbbb000101nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void SSRA(VReg_8B rd, VReg_8B rn, ImmRange<1, 8> shift) +{ + emit<"0000111100001bbb000101nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SSRA(VReg_16B rd, VReg_16B rn, ImmRange<1, 8> shift) +{ + emit<"0100111100001bbb000101nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void SSRA(VReg_4H rd, VReg_4H rn, ImmRange<1, 16> shift) +{ + emit<"000011110001hbbb000101nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SSRA(VReg_8H rd, VReg_8H rn, ImmRange<1, 16> shift) +{ + emit<"010011110001hbbb000101nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void SSRA(VReg_2S rd, VReg_2S rn, ImmRange<1, 32> shift) +{ + emit<"00001111001hhbbb000101nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SSRA(VReg_4S rd, VReg_4S rn, ImmRange<1, 32> shift) +{ + emit<"01001111001hhbbb000101nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void SSRA(VReg_2D rd, VReg_2D rn, ImmRange<1, 64> shift) +{ + emit<"0100111101hhhbbb000101nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void SSUBL(VReg_8H rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110001mmmmm001000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSUBL2(VReg_8H rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110001mmmmm001000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSUBL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110011mmmmm001000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSUBL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110011mmmmm001000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSUBL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110101mmmmm001000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSUBL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110101mmmmm001000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSUBW(VReg_8H rd, VReg_8H rn, VReg_8B rm) +{ + emit<"00001110001mmmmm001100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSUBW2(VReg_8H rd, VReg_8H rn, VReg_16B rm) +{ + emit<"01001110001mmmmm001100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSUBW(VReg_4S rd, VReg_4S rn, VReg_4H rm) +{ + emit<"00001110011mmmmm001100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSUBW2(VReg_4S rd, VReg_4S rn, VReg_8H rm) +{ + emit<"01001110011mmmmm001100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSUBW(VReg_2D rd, VReg_2D rn, VReg_2S rm) +{ + emit<"00001110101mmmmm001100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SSUBW2(VReg_2D rd, VReg_2D rn, VReg_4S rm) +{ + emit<"01001110101mmmmm001100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000011100nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000011100nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000011101nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000011101nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000011110nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000011110nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000011111nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000011111nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000101000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000101000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000101001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000101001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000101010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000101010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000101011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000101011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000011000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000011000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000011001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000011001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000011010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000011010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000011011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000011011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000001000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000001000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000001001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000001001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000001010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000001010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000001011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000001011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0000110010011111011100nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0100110010011111011100nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0000110010011111011101nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0100110010011111011101nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0000110010011111011110nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0100110010011111011110nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0000110010011111011111nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0100110010011111011111nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm011100nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm011100nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm011101nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm011101nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm011110nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm011110nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm011111nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm011111nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0000110010011111101000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110010011111101000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0000110010011111101001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110010011111101001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0000110010011111101010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110010011111101010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0000110010011111101011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110010011111101011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm101000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm101000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm101001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm101001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm101010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm101010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm101011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm101011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0000110010011111011000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<48>) +{ + emit<"0100110010011111011000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0000110010011111011001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<48>) +{ + emit<"0100110010011111011001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0000110010011111011010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<48>) +{ + emit<"0100110010011111011010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0000110010011111011011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<48>) +{ + emit<"0100110010011111011011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm011000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm011000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm011001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm011001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm011010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm011010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm011011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm011011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0000110010011111001000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<64>) +{ + emit<"0100110010011111001000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0000110010011111001001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<64>) +{ + emit<"0100110010011111001001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0000110010011111001010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<64>) +{ + emit<"0100110010011111001010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0000110010011111001011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<64>) +{ + emit<"0100110010011111001011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm001000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm001000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm001001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm001001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm001010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm001010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm001011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm001011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0Q00110100000000000Szznnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0Q00110100000000010Sz0nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0Q00110100000000100S00nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST1(List tlist, XRegSp addr_n) +{ + emit<"0Q00110100000000100001nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<1>) +{ + emit<"0Q00110110011111000Szznnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101100mmmmm000Szznnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<2>) +{ + emit<"0Q00110110011111010Sz0nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101100mmmmm010Sz0nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<4>) +{ + emit<"0Q00110110011111100S00nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101100mmmmm100S00nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0Q00110110011111100001nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST1(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101100mmmmm100001nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void ST2(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000100000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST2(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000100000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST2(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000100001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST2(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000100001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST2(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000100010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST2(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000100010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST2(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000100011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0000110010011111100000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110010011111100000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0000110010011111100001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110010011111100001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0000110010011111100010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110010011111100010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0100110010011111100011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm100000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm100000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm100001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm100001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm100010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm100010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm100011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST2(List tlist, XRegSp addr_n) +{ + emit<"0Q00110100100000000Szznnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST2(List tlist, XRegSp addr_n) +{ + emit<"0Q00110100100000010Sz0nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST2(List tlist, XRegSp addr_n) +{ + emit<"0Q00110100100000100S00nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST2(List tlist, XRegSp addr_n) +{ + emit<"0Q00110100100000100001nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<2>) +{ + emit<"0Q00110110111111000Szznnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101101mmmmm000Szznnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<4>) +{ + emit<"0Q00110110111111010Sz0nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101101mmmmm010Sz0nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0Q00110110111111100S00nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101101mmmmm100S00nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0Q00110110111111100001nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST2(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101101mmmmm100001nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void ST3(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000010000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST3(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000010000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST3(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000010001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST3(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000010001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST3(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000010010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST3(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000010010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST3(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000010011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0000110010011111010000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<48>) +{ + emit<"0100110010011111010000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0000110010011111010001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<48>) +{ + emit<"0100110010011111010001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0000110010011111010010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<48>) +{ + emit<"0100110010011111010010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<48>) +{ + emit<"0100110010011111010011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm010000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm010000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm010001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm010001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm010010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm010010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm010011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST3(List tlist, XRegSp addr_n) +{ + emit<"0Q00110100000000001Szznnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST3(List tlist, XRegSp addr_n) +{ + emit<"0Q00110100000000011Sz0nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST3(List tlist, XRegSp addr_n) +{ + emit<"0Q00110100000000101S00nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST3(List tlist, XRegSp addr_n) +{ + emit<"0Q00110100000000101001nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<3>) +{ + emit<"0Q00110110011111001Szznnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101100mmmmm001Szznnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<6>) +{ + emit<"0Q00110110011111011Sz0nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101100mmmmm011Sz0nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<12>) +{ + emit<"0Q00110110011111101S00nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101100mmmmm101S00nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, ImmConst<24>) +{ + emit<"0Q00110110011111101001nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST3(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101100mmmmm101001nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void ST4(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000000000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST4(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000000000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST4(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000000001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST4(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000000001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST4(List tlist, XRegSp addr_n) +{ + emit<"0000110000000000000010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST4(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000000010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST4(List tlist, XRegSp addr_n) +{ + emit<"0100110000000000000011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0000110010011111000000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<64>) +{ + emit<"0100110010011111000000nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0000110010011111000001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<64>) +{ + emit<"0100110010011111000001nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0000110010011111000010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<64>) +{ + emit<"0100110010011111000010nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<64>) +{ + emit<"0100110010011111000011nnnnnttttt", "t", "n">(tlist, addr_n); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm000000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm000000nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm000001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm000001nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"00001100100mmmmm000010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm000010nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"01001100100mmmmm000011nnnnnttttt", "t", "n", "m">(tlist, addr_n, xm); +} +void ST4(List tlist, XRegSp addr_n) +{ + emit<"0Q00110100100000001Szznnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST4(List tlist, XRegSp addr_n) +{ + emit<"0Q00110100100000011Sz0nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST4(List tlist, XRegSp addr_n) +{ + emit<"0Q00110100100000101S00nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST4(List tlist, XRegSp addr_n) +{ + emit<"0Q00110100100000101001nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<4>) +{ + emit<"0Q00110110111111001Szznnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101101mmmmm001Szznnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<8>) +{ + emit<"0Q00110110111111011Sz0nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101101mmmmm011Sz0nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<16>) +{ + emit<"0Q00110110111111101S00nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101101mmmmm101S00nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, ImmConst<32>) +{ + emit<"0Q00110110111111101001nnnnnttttt", "t", "QSz", "n">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n); +} +void ST4(List tlist, XRegSp addr_n, PostIndexed, XReg xm) +{ + if (xm.index() == 31) + throw "xzr invalid here"; + emit<"0Q001101101mmmmm101001nnnnnttttt", "t", "QSz", "n", "m">(tlist.m_base.reg_index(), tlist.m_base.elem_index(), addr_n, xm); +} +void STNP(SReg rt1, SReg rt2, XRegSp addr_n, SOffset<9, 2> offset = 0) +{ + emit<"0010110000iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void STNP(DReg rt1, DReg rt2, XRegSp addr_n, SOffset<10, 3> offset = 0) +{ + emit<"0110110000iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void STNP(QReg rt1, QReg rt2, XRegSp addr_n, SOffset<11, 4> offset = 0) +{ + emit<"1010110000iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void STP(SReg rt1, SReg rt2, XRegSp addr_n, PostIndexed, SOffset<9, 2> offset) +{ + emit<"0010110010iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void STP(DReg rt1, DReg rt2, XRegSp addr_n, PostIndexed, SOffset<10, 3> offset) +{ + emit<"0110110010iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void STP(QReg rt1, QReg rt2, XRegSp addr_n, PostIndexed, SOffset<11, 4> offset) +{ + emit<"1010110010iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void STP(SReg rt1, SReg rt2, XRegSp addr_n, PreIndexed, SOffset<9, 2> offset) +{ + emit<"0010110110iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void STP(DReg rt1, DReg rt2, XRegSp addr_n, PreIndexed, SOffset<10, 3> offset) +{ + emit<"0110110110iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void STP(QReg rt1, QReg rt2, XRegSp addr_n, PreIndexed, SOffset<11, 4> offset) +{ + emit<"1010110110iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void STP(SReg rt1, SReg rt2, XRegSp addr_n, SOffset<9, 2> offset = 0) +{ + emit<"0010110100iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void STP(DReg rt1, DReg rt2, XRegSp addr_n, SOffset<10, 3> offset = 0) +{ + emit<"0110110100iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void STP(QReg rt1, QReg rt2, XRegSp addr_n, SOffset<11, 4> offset = 0) +{ + emit<"1010110100iiiiiiiuuuuunnnnnttttt", "t", "u", "n", "i">(rt1, rt2, addr_n, offset); +} +void STR(BReg rt, XRegSp addr_n, PostIndexed, SOffset<9, 0> offset) +{ + emit<"00111100000iiiiiiiii01nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STR(HReg rt, XRegSp addr_n, PostIndexed, SOffset<9, 0> offset) +{ + emit<"01111100000iiiiiiiii01nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STR(SReg rt, XRegSp addr_n, PostIndexed, SOffset<9, 0> offset) +{ + emit<"10111100000iiiiiiiii01nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STR(DReg rt, XRegSp addr_n, PostIndexed, SOffset<9, 0> offset) +{ + emit<"11111100000iiiiiiiii01nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STR(QReg rt, XRegSp addr_n, PostIndexed, SOffset<9, 0> offset) +{ + emit<"00111100100iiiiiiiii01nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STR(BReg rt, XRegSp addr_n, PreIndexed, SOffset<9, 0> offset) +{ + emit<"00111100000iiiiiiiii11nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STR(HReg rt, XRegSp addr_n, PreIndexed, SOffset<9, 0> offset) +{ + emit<"01111100000iiiiiiiii11nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STR(SReg rt, XRegSp addr_n, PreIndexed, SOffset<9, 0> offset) +{ + emit<"10111100000iiiiiiiii11nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STR(DReg rt, XRegSp addr_n, PreIndexed, SOffset<9, 0> offset) +{ + emit<"11111100000iiiiiiiii11nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STR(QReg rt, XRegSp addr_n, PreIndexed, SOffset<9, 0> offset) +{ + emit<"00111100100iiiiiiiii11nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STR(BReg rt, XRegSp addr_n, POffset<12, 0> offset = 0) +{ + emit<"0011110100iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STR(HReg rt, XRegSp addr_n, POffset<13, 1> offset = 0) +{ + emit<"0111110100iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STR(SReg rt, XRegSp addr_n, POffset<14, 2> offset = 0) +{ + emit<"1011110100iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STR(DReg rt, XRegSp addr_n, POffset<15, 3> offset = 0) +{ + emit<"1111110100iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STR(QReg rt, XRegSp addr_n, POffset<16, 4> offset = 0) +{ + emit<"0011110110iiiiiiiiiiiinnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STR(BReg rt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 0> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"00111100001mmmmmpppS10nnnnnttttt", "t", "n", "m", "p", "S">(rt, xn, rm, ext, amount); +} +void STR(HReg rt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 1> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"01111100001mmmmmpppS10nnnnnttttt", "t", "n", "m", "p", "S">(rt, xn, rm, ext, amount); +} +void STR(SReg rt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 2> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"10111100001mmmmmpppS10nnnnnttttt", "t", "n", "m", "p", "S">(rt, xn, rm, ext, amount); +} +void STR(DReg rt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 3> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"11111100001mmmmmpppS10nnnnnttttt", "t", "n", "m", "p", "S">(rt, xn, rm, ext, amount); +} +void STR(QReg rt, XRegSp xn, RReg rm, IndexExt ext = IndexExt::LSL, ImmChoice<0, 4> amount = 0) +{ + indexext_verify_reg_size(ext, rm); + emit<"00111100101mmmmmpppS10nnnnnttttt", "t", "n", "m", "p", "S">(rt, xn, rm, ext, amount); +} +void STUR(BReg rt, XRegSp addr_n, SOffset<9, 0> offset = 0) +{ + emit<"00111100000iiiiiiiii00nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STUR(HReg rt, XRegSp addr_n, SOffset<9, 0> offset = 0) +{ + emit<"01111100000iiiiiiiii00nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STUR(SReg rt, XRegSp addr_n, SOffset<9, 0> offset = 0) +{ + emit<"10111100000iiiiiiiii00nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STUR(DReg rt, XRegSp addr_n, SOffset<9, 0> offset = 0) +{ + emit<"11111100000iiiiiiiii00nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void STUR(QReg rt, XRegSp addr_n, SOffset<9, 0> offset = 0) +{ + emit<"00111100100iiiiiiiii00nnnnnttttt", "t", "n", "i">(rt, addr_n, offset); +} +void SUB(DReg rd, DReg rn, DReg rm) +{ + emit<"01111110111mmmmm100001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SUB(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm100001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SUB(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm100001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SUB(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm100001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SUB(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm100001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SUB(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm100001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SUB(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm100001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SUB(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110111mmmmm100001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SUBHN(VReg_8B rd, VReg_8H rn, VReg_8H rm) +{ + emit<"00001110001mmmmm011000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SUBHN2(VReg_16B rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110001mmmmm011000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SUBHN(VReg_4H rd, VReg_4S rn, VReg_4S rm) +{ + emit<"00001110011mmmmm011000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SUBHN2(VReg_8H rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110011mmmmm011000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SUBHN(VReg_2S rd, VReg_2D rn, VReg_2D rm) +{ + emit<"00001110101mmmmm011000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SUBHN2(VReg_4S rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110101mmmmm011000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void SUQADD(BReg rd, BReg rn) +{ + emit<"0101111000100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void SUQADD(HReg rd, HReg rn) +{ + emit<"0101111001100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void SUQADD(SReg rd, SReg rn) +{ + emit<"0101111010100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void SUQADD(DReg rd, DReg rn) +{ + emit<"0101111011100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void SUQADD(VReg_8B rd, VReg_8B rn) +{ + emit<"0000111000100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void SUQADD(VReg_16B rd, VReg_16B rn) +{ + emit<"0100111000100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void SUQADD(VReg_4H rd, VReg_4H rn) +{ + emit<"0000111001100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void SUQADD(VReg_8H rd, VReg_8H rn) +{ + emit<"0100111001100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void SUQADD(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111010100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void SUQADD(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111010100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void SUQADD(VReg_2D rd, VReg_2D rn) +{ + emit<"0100111011100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void SXTL(VReg_8H rd, VReg_8B rn) +{ + emit<"0000111100001000101001nnnnnddddd", "d", "n">(rd, rn); +} +void SXTL2(VReg_8H rd, VReg_16B rn) +{ + emit<"0100111100001000101001nnnnnddddd", "d", "n">(rd, rn); +} +void SXTL(VReg_4S rd, VReg_4H rn) +{ + emit<"000011110001h000101001nnnnnddddd", "d", "n">(rd, rn); +} +void SXTL2(VReg_4S rd, VReg_8H rn) +{ + emit<"010011110001h000101001nnnnnddddd", "d", "n">(rd, rn); +} +void SXTL(VReg_2D rd, VReg_2S rn) +{ + emit<"00001111001hh000101001nnnnnddddd", "d", "n">(rd, rn); +} +void SXTL2(VReg_2D rd, VReg_4S rn) +{ + emit<"01001111001hh000101001nnnnnddddd", "d", "n">(rd, rn); +} +void TBL(VReg_8B rd, List nlist, VReg_8B rm) +{ + emit<"00001110000mmmmm001000nnnnnddddd", "d", "n", "m">(rd, nlist, rm); +} +void TBL(VReg_16B rd, List nlist, VReg_16B rm) +{ + emit<"01001110000mmmmm001000nnnnnddddd", "d", "n", "m">(rd, nlist, rm); +} +void TBL(VReg_8B rd, List nlist, VReg_8B rm) +{ + emit<"00001110000mmmmm010000nnnnnddddd", "d", "n", "m">(rd, nlist, rm); +} +void TBL(VReg_16B rd, List nlist, VReg_16B rm) +{ + emit<"01001110000mmmmm010000nnnnnddddd", "d", "n", "m">(rd, nlist, rm); +} +void TBL(VReg_8B rd, List nlist, VReg_8B rm) +{ + emit<"00001110000mmmmm011000nnnnnddddd", "d", "n", "m">(rd, nlist, rm); +} +void TBL(VReg_16B rd, List nlist, VReg_16B rm) +{ + emit<"01001110000mmmmm011000nnnnnddddd", "d", "n", "m">(rd, nlist, rm); +} +void TBL(VReg_8B rd, List nlist, VReg_8B rm) +{ + emit<"00001110000mmmmm000000nnnnnddddd", "d", "n", "m">(rd, nlist, rm); +} +void TBL(VReg_16B rd, List nlist, VReg_16B rm) +{ + emit<"01001110000mmmmm000000nnnnnddddd", "d", "n", "m">(rd, nlist, rm); +} +void TBX(VReg_8B rd, List nlist, VReg_8B rm) +{ + emit<"00001110000mmmmm001100nnnnnddddd", "d", "n", "m">(rd, nlist, rm); +} +void TBX(VReg_16B rd, List nlist, VReg_16B rm) +{ + emit<"01001110000mmmmm001100nnnnnddddd", "d", "n", "m">(rd, nlist, rm); +} +void TBX(VReg_8B rd, List nlist, VReg_8B rm) +{ + emit<"00001110000mmmmm010100nnnnnddddd", "d", "n", "m">(rd, nlist, rm); +} +void TBX(VReg_16B rd, List nlist, VReg_16B rm) +{ + emit<"01001110000mmmmm010100nnnnnddddd", "d", "n", "m">(rd, nlist, rm); +} +void TBX(VReg_8B rd, List nlist, VReg_8B rm) +{ + emit<"00001110000mmmmm011100nnnnnddddd", "d", "n", "m">(rd, nlist, rm); +} +void TBX(VReg_16B rd, List nlist, VReg_16B rm) +{ + emit<"01001110000mmmmm011100nnnnnddddd", "d", "n", "m">(rd, nlist, rm); +} +void TBX(VReg_8B rd, List nlist, VReg_8B rm) +{ + emit<"00001110000mmmmm000100nnnnnddddd", "d", "n", "m">(rd, nlist, rm); +} +void TBX(VReg_16B rd, List nlist, VReg_16B rm) +{ + emit<"01001110000mmmmm000100nnnnnddddd", "d", "n", "m">(rd, nlist, rm); +} +void TRN1(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110000mmmmm001010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void TRN1(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110000mmmmm001010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void TRN1(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110010mmmmm001010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void TRN1(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110010mmmmm001010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void TRN1(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110100mmmmm001010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void TRN1(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110100mmmmm001010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void TRN1(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110110mmmmm001010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void TRN2(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110000mmmmm011010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void TRN2(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110000mmmmm011010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void TRN2(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110010mmmmm011010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void TRN2(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110010mmmmm011010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void TRN2(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110100mmmmm011010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void TRN2(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110100mmmmm011010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void TRN2(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110110mmmmm011010nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABA(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm011111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABA(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm011111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABA(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm011111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABA(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm011111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABA(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm011111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABA(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm011111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABAL(VReg_8H rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm010100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABAL2(VReg_8H rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm010100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABAL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm010100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABAL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm010100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABAL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm010100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABAL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm010100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABD(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm011101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABD(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm011101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABD(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm011101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABD(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm011101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABD(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm011101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABD(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm011101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABDL(VReg_8H rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm011100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABDL2(VReg_8H rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm011100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABDL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm011100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABDL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm011100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABDL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm011100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UABDL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm011100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UADALP(VReg_4H rd, VReg_8B rn) +{ + emit<"0010111000100000011010nnnnnddddd", "d", "n">(rd, rn); +} +void UADALP(VReg_8H rd, VReg_16B rn) +{ + emit<"0110111000100000011010nnnnnddddd", "d", "n">(rd, rn); +} +void UADALP(VReg_2S rd, VReg_4H rn) +{ + emit<"0010111001100000011010nnnnnddddd", "d", "n">(rd, rn); +} +void UADALP(VReg_4S rd, VReg_8H rn) +{ + emit<"0110111001100000011010nnnnnddddd", "d", "n">(rd, rn); +} +void UADALP(VReg_1D rd, VReg_2S rn) +{ + emit<"0010111010100000011010nnnnnddddd", "d", "n">(rd, rn); +} +void UADALP(VReg_2D rd, VReg_4S rn) +{ + emit<"0110111010100000011010nnnnnddddd", "d", "n">(rd, rn); +} +void UADDL(VReg_8H rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm000000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UADDL2(VReg_8H rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm000000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UADDL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm000000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UADDL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm000000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UADDL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm000000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UADDL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm000000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UADDLP(VReg_4H rd, VReg_8B rn) +{ + emit<"0010111000100000001010nnnnnddddd", "d", "n">(rd, rn); +} +void UADDLP(VReg_8H rd, VReg_16B rn) +{ + emit<"0110111000100000001010nnnnnddddd", "d", "n">(rd, rn); +} +void UADDLP(VReg_2S rd, VReg_4H rn) +{ + emit<"0010111001100000001010nnnnnddddd", "d", "n">(rd, rn); +} +void UADDLP(VReg_4S rd, VReg_8H rn) +{ + emit<"0110111001100000001010nnnnnddddd", "d", "n">(rd, rn); +} +void UADDLP(VReg_1D rd, VReg_2S rn) +{ + emit<"0010111010100000001010nnnnnddddd", "d", "n">(rd, rn); +} +void UADDLP(VReg_2D rd, VReg_4S rn) +{ + emit<"0110111010100000001010nnnnnddddd", "d", "n">(rd, rn); +} +void UADDLV(HReg rd, VReg_8B rn) +{ + emit<"0010111000110000001110nnnnnddddd", "d", "n">(rd, rn); +} +void UADDLV(HReg rd, VReg_16B rn) +{ + emit<"0110111000110000001110nnnnnddddd", "d", "n">(rd, rn); +} +void UADDLV(SReg rd, VReg_4H rn) +{ + emit<"0010111001110000001110nnnnnddddd", "d", "n">(rd, rn); +} +void UADDLV(SReg rd, VReg_8H rn) +{ + emit<"0110111001110000001110nnnnnddddd", "d", "n">(rd, rn); +} +void UADDLV(DReg rd, VReg_4S rn) +{ + emit<"0110111010110000001110nnnnnddddd", "d", "n">(rd, rn); +} +void UADDW(VReg_8H rd, VReg_8H rn, VReg_8B rm) +{ + emit<"00101110001mmmmm000100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UADDW2(VReg_8H rd, VReg_8H rn, VReg_16B rm) +{ + emit<"01101110001mmmmm000100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UADDW(VReg_4S rd, VReg_4S rn, VReg_4H rm) +{ + emit<"00101110011mmmmm000100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UADDW2(VReg_4S rd, VReg_4S rn, VReg_8H rm) +{ + emit<"01101110011mmmmm000100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UADDW(VReg_2D rd, VReg_2D rn, VReg_2S rm) +{ + emit<"00101110101mmmmm000100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UADDW2(VReg_2D rd, VReg_2D rn, VReg_4S rm) +{ + emit<"01101110101mmmmm000100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UCVTF(SReg rd, WReg wn, ImmRange<1, 32> fbits) +{ + emit<"0001111000000011SSSSSSnnnnnddddd", "d", "n", "S">(rd, wn, 64 - fbits.value()); +} +void UCVTF(DReg rd, WReg wn, ImmRange<1, 32> fbits) +{ + emit<"0001111001000011SSSSSSnnnnnddddd", "d", "n", "S">(rd, wn, 64 - fbits.value()); +} +void UCVTF(SReg rd, XReg xn, ImmRange<1, 64> fbits) +{ + emit<"1001111000000011SSSSSSnnnnnddddd", "d", "n", "S">(rd, xn, 64 - fbits.value()); +} +void UCVTF(DReg rd, XReg xn, ImmRange<1, 64> fbits) +{ + emit<"1001111001000011SSSSSSnnnnnddddd", "d", "n", "S">(rd, xn, 64 - fbits.value()); +} +void UCVTF(SReg rd, WReg wn) +{ + emit<"0001111000100011000000nnnnnddddd", "d", "n">(rd, wn); +} +void UCVTF(DReg rd, WReg wn) +{ + emit<"0001111001100011000000nnnnnddddd", "d", "n">(rd, wn); +} +void UCVTF(SReg rd, XReg xn) +{ + emit<"1001111000100011000000nnnnnddddd", "d", "n">(rd, xn); +} +void UCVTF(DReg rd, XReg xn) +{ + emit<"1001111001100011000000nnnnnddddd", "d", "n">(rd, xn); +} +void UCVTF(HReg rd, HReg rn, ImmRange<1, 16> fbits) +{ + emit<"011111110001hbbb111001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - fbits.value()); +} +void UCVTF(SReg rd, SReg rn, ImmRange<1, 32> fbits) +{ + emit<"01111111001hhbbb111001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - fbits.value()); +} +void UCVTF(DReg rd, DReg rn, ImmRange<1, 64> fbits) +{ + emit<"0111111101hhhbbb111001nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - fbits.value()); +} +void UCVTF(VReg_4H rd, VReg_4H rn, ImmRange<1, 16> fbits) +{ + emit<"001011110001hbbb111001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - fbits.value()); +} +void UCVTF(VReg_8H rd, VReg_8H rn, ImmRange<1, 16> fbits) +{ + emit<"011011110001hbbb111001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - fbits.value()); +} +void UCVTF(VReg_2S rd, VReg_2S rn, ImmRange<1, 32> fbits) +{ + emit<"00101111001hhbbb111001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - fbits.value()); +} +void UCVTF(VReg_4S rd, VReg_4S rn, ImmRange<1, 32> fbits) +{ + emit<"01101111001hhbbb111001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - fbits.value()); +} +void UCVTF(VReg_2D rd, VReg_2D rn, ImmRange<1, 64> fbits) +{ + emit<"0110111101hhhbbb111001nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - fbits.value()); +} +void UCVTF(SReg rd, SReg rn) +{ + emit<"0111111000100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void UCVTF(DReg rd, DReg rn) +{ + emit<"0111111001100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void UCVTF(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111000100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void UCVTF(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111000100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void UCVTF(VReg_2D rd, VReg_2D rn) +{ + emit<"0110111001100001110110nnnnnddddd", "d", "n">(rd, rn); +} +void UHADD(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm000001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UHADD(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm000001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UHADD(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm000001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UHADD(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm000001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UHADD(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm000001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UHADD(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm000001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UHSUB(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm001001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UHSUB(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm001001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UHSUB(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm001001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UHSUB(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm001001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UHSUB(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm001001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UHSUB(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm001001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMAX(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm011001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMAX(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm011001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMAX(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm011001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMAX(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm011001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMAX(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm011001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMAX(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm011001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMAXP(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm101001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMAXP(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm101001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMAXP(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm101001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMAXP(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm101001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMAXP(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm101001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMAXP(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm101001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMAXV(BReg rd, VReg_8B rn) +{ + emit<"0010111000110000101010nnnnnddddd", "d", "n">(rd, rn); +} +void UMAXV(BReg rd, VReg_16B rn) +{ + emit<"0110111000110000101010nnnnnddddd", "d", "n">(rd, rn); +} +void UMAXV(HReg rd, VReg_4H rn) +{ + emit<"0010111001110000101010nnnnnddddd", "d", "n">(rd, rn); +} +void UMAXV(HReg rd, VReg_8H rn) +{ + emit<"0110111001110000101010nnnnnddddd", "d", "n">(rd, rn); +} +void UMAXV(SReg rd, VReg_4S rn) +{ + emit<"0110111010110000101010nnnnnddddd", "d", "n">(rd, rn); +} +void UMIN(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm011011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMIN(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm011011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMIN(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm011011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMIN(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm011011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMIN(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm011011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMIN(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm011011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMINP(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm101011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMINP(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm101011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMINP(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm101011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMINP(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm101011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMINP(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm101011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMINP(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm101011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMINV(BReg rd, VReg_8B rn) +{ + emit<"0010111000110001101010nnnnnddddd", "d", "n">(rd, rn); +} +void UMINV(BReg rd, VReg_16B rn) +{ + emit<"0110111000110001101010nnnnnddddd", "d", "n">(rd, rn); +} +void UMINV(HReg rd, VReg_4H rn) +{ + emit<"0010111001110001101010nnnnnddddd", "d", "n">(rd, rn); +} +void UMINV(HReg rd, VReg_8H rn) +{ + emit<"0110111001110001101010nnnnnddddd", "d", "n">(rd, rn); +} +void UMINV(SReg rd, VReg_4S rn) +{ + emit<"0110111010110001101010nnnnnddddd", "d", "n">(rd, rn); +} +void UMLAL(VReg_4S rd, VReg_4H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0010111101LMmmmm0010H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void UMLAL2(VReg_4S rd, VReg_8H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0110111101LMmmmm0010H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void UMLAL(VReg_2D rd, VReg_2S rn, SElem em) +{ + emit<"0010111110LMmmmm0010H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void UMLAL2(VReg_2D rd, VReg_4S rn, SElem em) +{ + emit<"0110111110LMmmmm0010H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void UMLAL(VReg_8H rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm100000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMLAL2(VReg_8H rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm100000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMLAL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm100000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMLAL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm100000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMLAL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm100000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMLAL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm100000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMLSL(VReg_4S rd, VReg_4H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0010111101LMmmmm0110H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void UMLSL2(VReg_4S rd, VReg_8H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0110111101LMmmmm0110H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void UMLSL(VReg_2D rd, VReg_2S rn, SElem em) +{ + emit<"0010111110LMmmmm0110H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void UMLSL2(VReg_2D rd, VReg_4S rn, SElem em) +{ + emit<"0110111110LMmmmm0110H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void UMLSL(VReg_8H rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm101000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMLSL2(VReg_8H rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm101000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMLSL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm101000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMLSL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm101000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMLSL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm101000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMLSL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm101000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMOV(WReg wd, BElem en) +{ + emit<"00001110000xxxx1001111nnnnnddddd", "d", "n", "x">(wd, en.reg_index(), en.elem_index()); +} +void UMOV(WReg wd, HElem en) +{ + emit<"00001110000xxx10001111nnnnnddddd", "d", "n", "x">(wd, en.reg_index(), en.elem_index()); +} +void UMOV(WReg wd, SElem en) +{ + emit<"00001110000xx100001111nnnnnddddd", "d", "n", "x">(wd, en.reg_index(), en.elem_index()); +} +void UMOV(XReg xd, DElem en) +{ + emit<"01001110000i1000001111nnnnnddddd", "d", "n", "x">(xd, en.reg_index(), en.elem_index()); +} +void UMULL(VReg_4S rd, VReg_4H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0010111101LMmmmm1010H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void UMULL2(VReg_4S rd, VReg_8H rn, HElem em) +{ + if (em.reg_index() >= 16) + throw "InvalidCombination"; + emit<"0110111101LMmmmm1010H0nnnnnddddd", "d", "n", "m", "H", "L", "M">(rd, rn, em.reg_index(), em.elem_index() >> 2, (em.elem_index() >> 1) & 1, em.elem_index() & 1); +} +void UMULL(VReg_2D rd, VReg_2S rn, SElem em) +{ + emit<"0010111110LMmmmm1010H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void UMULL2(VReg_2D rd, VReg_4S rn, SElem em) +{ + emit<"0110111110LMmmmm1010H0nnnnnddddd", "d", "n", "Mm", "H", "L">(rd, rn, em.reg_index(), em.elem_index() >> 1, em.elem_index() & 1); +} +void UMULL(VReg_8H rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm110000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMULL2(VReg_8H rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm110000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMULL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm110000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMULL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm110000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMULL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm110000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UMULL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm110000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQADD(BReg rd, BReg rn, BReg rm) +{ + emit<"01111110001mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQADD(HReg rd, HReg rn, HReg rm) +{ + emit<"01111110011mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQADD(SReg rd, SReg rn, SReg rm) +{ + emit<"01111110101mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQADD(DReg rd, DReg rn, DReg rm) +{ + emit<"01111110111mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQADD(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQADD(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQADD(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQADD(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQADD(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQADD(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQADD(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110111mmmmm000011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQRSHL(BReg rd, BReg rn, BReg rm) +{ + emit<"01111110001mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQRSHL(HReg rd, HReg rn, HReg rm) +{ + emit<"01111110011mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQRSHL(SReg rd, SReg rn, SReg rm) +{ + emit<"01111110101mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQRSHL(DReg rd, DReg rn, DReg rm) +{ + emit<"01111110111mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQRSHL(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQRSHL(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQRSHL(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQRSHL(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQRSHL(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQRSHL(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQRSHL(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110111mmmmm010111nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQRSHRN(BReg rd, HReg rn, ImmRange<1, 8> shift) +{ + emit<"0111111100001bbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void UQRSHRN(HReg rd, SReg rn, ImmRange<1, 16> shift) +{ + emit<"011111110001hbbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void UQRSHRN(SReg rd, DReg rn, ImmRange<1, 32> shift) +{ + emit<"01111111001hhbbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void UQRSHRN(VReg_8B rd, VReg_8H rn, ImmRange<1, 8> shift) +{ + emit<"0010111100001bbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void UQRSHRN2(VReg_16B rd, VReg_8H rn, ImmRange<1, 8> shift) +{ + emit<"0110111100001bbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void UQRSHRN(VReg_4H rd, VReg_4S rn, ImmRange<1, 16> shift) +{ + emit<"001011110001hbbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void UQRSHRN2(VReg_8H rd, VReg_4S rn, ImmRange<1, 16> shift) +{ + emit<"011011110001hbbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void UQRSHRN(VReg_2S rd, VReg_2D rn, ImmRange<1, 32> shift) +{ + emit<"00101111001hhbbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void UQRSHRN2(VReg_4S rd, VReg_2D rn, ImmRange<1, 32> shift) +{ + emit<"01101111001hhbbb100111nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void UQSHL(BReg rd, BReg rn, ImmRange<0, 7> shift) +{ + emit<"0111111100001bbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void UQSHL(HReg rd, HReg rn, ImmRange<0, 15> shift) +{ + emit<"011111110001hbbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void UQSHL(SReg rd, SReg rn, ImmRange<0, 31> shift) +{ + emit<"01111111001hhbbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void UQSHL(DReg rd, DReg rn, ImmRange<0, 63> shift) +{ + emit<"0111111101hhhbbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void UQSHL(VReg_8B rd, VReg_8B rn, ImmRange<0, 7> shift) +{ + emit<"0010111100001bbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void UQSHL(VReg_16B rd, VReg_16B rn, ImmRange<0, 7> shift) +{ + emit<"0110111100001bbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void UQSHL(VReg_4H rd, VReg_4H rn, ImmRange<0, 15> shift) +{ + emit<"001011110001hbbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void UQSHL(VReg_8H rd, VReg_8H rn, ImmRange<0, 15> shift) +{ + emit<"011011110001hbbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void UQSHL(VReg_2S rd, VReg_2S rn, ImmRange<0, 31> shift) +{ + emit<"00101111001hhbbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void UQSHL(VReg_4S rd, VReg_4S rn, ImmRange<0, 31> shift) +{ + emit<"01101111001hhbbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void UQSHL(VReg_2D rd, VReg_2D rn, ImmRange<0, 63> shift) +{ + emit<"0110111101hhhbbb011101nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void UQSHL(BReg rd, BReg rn, BReg rm) +{ + emit<"01111110001mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSHL(HReg rd, HReg rn, HReg rm) +{ + emit<"01111110011mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSHL(SReg rd, SReg rn, SReg rm) +{ + emit<"01111110101mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSHL(DReg rd, DReg rn, DReg rm) +{ + emit<"01111110111mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSHL(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSHL(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSHL(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSHL(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSHL(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSHL(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSHL(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110111mmmmm010011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSHRN(BReg rd, HReg rn, ImmRange<1, 8> shift) +{ + emit<"0111111100001bbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void UQSHRN(HReg rd, SReg rn, ImmRange<1, 16> shift) +{ + emit<"011111110001hbbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void UQSHRN(SReg rd, DReg rn, ImmRange<1, 32> shift) +{ + emit<"01111111001hhbbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void UQSHRN(VReg_8B rd, VReg_8H rn, ImmRange<1, 8> shift) +{ + emit<"0010111100001bbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void UQSHRN2(VReg_16B rd, VReg_8H rn, ImmRange<1, 8> shift) +{ + emit<"0110111100001bbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void UQSHRN(VReg_4H rd, VReg_4S rn, ImmRange<1, 16> shift) +{ + emit<"001011110001hbbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void UQSHRN2(VReg_8H rd, VReg_4S rn, ImmRange<1, 16> shift) +{ + emit<"011011110001hbbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void UQSHRN(VReg_2S rd, VReg_2D rn, ImmRange<1, 32> shift) +{ + emit<"00101111001hhbbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void UQSHRN2(VReg_4S rd, VReg_2D rn, ImmRange<1, 32> shift) +{ + emit<"01101111001hhbbb100101nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void UQSUB(BReg rd, BReg rn, BReg rm) +{ + emit<"01111110001mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSUB(HReg rd, HReg rn, HReg rm) +{ + emit<"01111110011mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSUB(SReg rd, SReg rn, SReg rm) +{ + emit<"01111110101mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSUB(DReg rd, DReg rn, DReg rm) +{ + emit<"01111110111mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSUB(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSUB(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSUB(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSUB(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSUB(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSUB(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQSUB(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110111mmmmm001011nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UQXTN(BReg rd, HReg rn) +{ + emit<"0111111000100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void UQXTN(HReg rd, SReg rn) +{ + emit<"0111111001100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void UQXTN(SReg rd, DReg rn) +{ + emit<"0111111010100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void UQXTN(VReg_8B rd, VReg_8H rn) +{ + emit<"0010111000100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void UQXTN2(VReg_16B rd, VReg_8H rn) +{ + emit<"0110111000100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void UQXTN(VReg_4H rd, VReg_4S rn) +{ + emit<"0010111001100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void UQXTN2(VReg_8H rd, VReg_4S rn) +{ + emit<"0110111001100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void UQXTN(VReg_2S rd, VReg_2D rn) +{ + emit<"0010111010100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void UQXTN2(VReg_4S rd, VReg_2D rn) +{ + emit<"0110111010100001010010nnnnnddddd", "d", "n">(rd, rn); +} +void URECPE(VReg_2S rd, VReg_2S rn) +{ + emit<"0000111010100001110010nnnnnddddd", "d", "n">(rd, rn); +} +void URECPE(VReg_4S rd, VReg_4S rn) +{ + emit<"0100111010100001110010nnnnnddddd", "d", "n">(rd, rn); +} +void URHADD(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm000101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void URHADD(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm000101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void URHADD(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm000101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void URHADD(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm000101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void URHADD(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm000101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void URHADD(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm000101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void URSHL(DReg rd, DReg rn, DReg rm) +{ + emit<"01111110111mmmmm010101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void URSHL(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm010101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void URSHL(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm010101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void URSHL(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm010101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void URSHL(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm010101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void URSHL(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm010101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void URSHL(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm010101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void URSHL(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110111mmmmm010101nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void URSHR(DReg rd, DReg rn, ImmRange<1, 64> shift) +{ + emit<"0111111101hhhbbb001001nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void URSHR(VReg_8B rd, VReg_8B rn, ImmRange<1, 8> shift) +{ + emit<"0010111100001bbb001001nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void URSHR(VReg_16B rd, VReg_16B rn, ImmRange<1, 8> shift) +{ + emit<"0110111100001bbb001001nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void URSHR(VReg_4H rd, VReg_4H rn, ImmRange<1, 16> shift) +{ + emit<"001011110001hbbb001001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void URSHR(VReg_8H rd, VReg_8H rn, ImmRange<1, 16> shift) +{ + emit<"011011110001hbbb001001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void URSHR(VReg_2S rd, VReg_2S rn, ImmRange<1, 32> shift) +{ + emit<"00101111001hhbbb001001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void URSHR(VReg_4S rd, VReg_4S rn, ImmRange<1, 32> shift) +{ + emit<"01101111001hhbbb001001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void URSHR(VReg_2D rd, VReg_2D rn, ImmRange<1, 64> shift) +{ + emit<"0110111101hhhbbb001001nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void URSQRTE(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111010100001110010nnnnnddddd", "d", "n">(rd, rn); +} +void URSQRTE(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111010100001110010nnnnnddddd", "d", "n">(rd, rn); +} +void URSRA(DReg rd, DReg rn, ImmRange<1, 64> shift) +{ + emit<"0111111101hhhbbb001101nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void URSRA(VReg_8B rd, VReg_8B rn, ImmRange<1, 8> shift) +{ + emit<"0010111100001bbb001101nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void URSRA(VReg_16B rd, VReg_16B rn, ImmRange<1, 8> shift) +{ + emit<"0110111100001bbb001101nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void URSRA(VReg_4H rd, VReg_4H rn, ImmRange<1, 16> shift) +{ + emit<"001011110001hbbb001101nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void URSRA(VReg_8H rd, VReg_8H rn, ImmRange<1, 16> shift) +{ + emit<"011011110001hbbb001101nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void URSRA(VReg_2S rd, VReg_2S rn, ImmRange<1, 32> shift) +{ + emit<"00101111001hhbbb001101nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void URSRA(VReg_4S rd, VReg_4S rn, ImmRange<1, 32> shift) +{ + emit<"01101111001hhbbb001101nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void URSRA(VReg_2D rd, VReg_2D rn, ImmRange<1, 64> shift) +{ + emit<"0110111101hhhbbb001101nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void USHL(DReg rd, DReg rn, DReg rm) +{ + emit<"01111110111mmmmm010001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USHL(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm010001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USHL(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm010001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USHL(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm010001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USHL(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm010001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USHL(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm010001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USHL(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm010001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USHL(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01101110111mmmmm010001nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USHLL(VReg_8H rd, VReg_8B rn, ImmRange<0, 7> shift) +{ + emit<"0010111100001bbb101001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void USHLL2(VReg_8H rd, VReg_16B rn, ImmRange<0, 7> shift) +{ + emit<"0110111100001bbb101001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void USHLL(VReg_4S rd, VReg_4H rn, ImmRange<0, 15> shift) +{ + emit<"001011110001hbbb101001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void USHLL2(VReg_4S rd, VReg_8H rn, ImmRange<0, 15> shift) +{ + emit<"011011110001hbbb101001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void USHLL(VReg_2D rd, VReg_2S rn, ImmRange<0, 31> shift) +{ + emit<"00101111001hhbbb101001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void USHLL2(VReg_2D rd, VReg_4S rn, ImmRange<0, 31> shift) +{ + emit<"01101111001hhbbb101001nnnnnddddd", "d", "n", "hb">(rd, rn, shift.value()); +} +void USHR(DReg rd, DReg rn, ImmRange<1, 64> shift) +{ + emit<"0111111101hhhbbb000001nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void USHR(VReg_8B rd, VReg_8B rn, ImmRange<1, 8> shift) +{ + emit<"0010111100001bbb000001nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void USHR(VReg_16B rd, VReg_16B rn, ImmRange<1, 8> shift) +{ + emit<"0110111100001bbb000001nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void USHR(VReg_4H rd, VReg_4H rn, ImmRange<1, 16> shift) +{ + emit<"001011110001hbbb000001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void USHR(VReg_8H rd, VReg_8H rn, ImmRange<1, 16> shift) +{ + emit<"011011110001hbbb000001nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void USHR(VReg_2S rd, VReg_2S rn, ImmRange<1, 32> shift) +{ + emit<"00101111001hhbbb000001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void USHR(VReg_4S rd, VReg_4S rn, ImmRange<1, 32> shift) +{ + emit<"01101111001hhbbb000001nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void USHR(VReg_2D rd, VReg_2D rn, ImmRange<1, 64> shift) +{ + emit<"0110111101hhhbbb000001nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void USQADD(BReg rd, BReg rn) +{ + emit<"0111111000100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void USQADD(HReg rd, HReg rn) +{ + emit<"0111111001100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void USQADD(SReg rd, SReg rn) +{ + emit<"0111111010100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void USQADD(DReg rd, DReg rn) +{ + emit<"0111111011100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void USQADD(VReg_8B rd, VReg_8B rn) +{ + emit<"0010111000100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void USQADD(VReg_16B rd, VReg_16B rn) +{ + emit<"0110111000100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void USQADD(VReg_4H rd, VReg_4H rn) +{ + emit<"0010111001100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void USQADD(VReg_8H rd, VReg_8H rn) +{ + emit<"0110111001100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void USQADD(VReg_2S rd, VReg_2S rn) +{ + emit<"0010111010100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void USQADD(VReg_4S rd, VReg_4S rn) +{ + emit<"0110111010100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void USQADD(VReg_2D rd, VReg_2D rn) +{ + emit<"0110111011100000001110nnnnnddddd", "d", "n">(rd, rn); +} +void USRA(DReg rd, DReg rn, ImmRange<1, 64> shift) +{ + emit<"0111111101hhhbbb000101nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void USRA(VReg_8B rd, VReg_8B rn, ImmRange<1, 8> shift) +{ + emit<"0010111100001bbb000101nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void USRA(VReg_16B rd, VReg_16B rn, ImmRange<1, 8> shift) +{ + emit<"0110111100001bbb000101nnnnnddddd", "d", "n", "hb">(rd, rn, 16 - shift.value()); +} +void USRA(VReg_4H rd, VReg_4H rn, ImmRange<1, 16> shift) +{ + emit<"001011110001hbbb000101nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void USRA(VReg_8H rd, VReg_8H rn, ImmRange<1, 16> shift) +{ + emit<"011011110001hbbb000101nnnnnddddd", "d", "n", "hb">(rd, rn, 32 - shift.value()); +} +void USRA(VReg_2S rd, VReg_2S rn, ImmRange<1, 32> shift) +{ + emit<"00101111001hhbbb000101nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void USRA(VReg_4S rd, VReg_4S rn, ImmRange<1, 32> shift) +{ + emit<"01101111001hhbbb000101nnnnnddddd", "d", "n", "hb">(rd, rn, 64 - shift.value()); +} +void USRA(VReg_2D rd, VReg_2D rn, ImmRange<1, 64> shift) +{ + emit<"0110111101hhhbbb000101nnnnnddddd", "d", "n", "hb">(rd, rn, 128 - shift.value()); +} +void USUBL(VReg_8H rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00101110001mmmmm001000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USUBL2(VReg_8H rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01101110001mmmmm001000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USUBL(VReg_4S rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00101110011mmmmm001000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USUBL2(VReg_4S rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01101110011mmmmm001000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USUBL(VReg_2D rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00101110101mmmmm001000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USUBL2(VReg_2D rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01101110101mmmmm001000nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USUBW(VReg_8H rd, VReg_8H rn, VReg_8B rm) +{ + emit<"00101110001mmmmm001100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USUBW2(VReg_8H rd, VReg_8H rn, VReg_16B rm) +{ + emit<"01101110001mmmmm001100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USUBW(VReg_4S rd, VReg_4S rn, VReg_4H rm) +{ + emit<"00101110011mmmmm001100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USUBW2(VReg_4S rd, VReg_4S rn, VReg_8H rm) +{ + emit<"01101110011mmmmm001100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USUBW(VReg_2D rd, VReg_2D rn, VReg_2S rm) +{ + emit<"00101110101mmmmm001100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void USUBW2(VReg_2D rd, VReg_2D rn, VReg_4S rm) +{ + emit<"01101110101mmmmm001100nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UXTL(VReg_8H rd, VReg_8B rn) +{ + emit<"0010111100001000101001nnnnnddddd", "d", "n">(rd, rn); +} +void UXTL2(VReg_8H rd, VReg_16B rn) +{ + emit<"0110111100001000101001nnnnnddddd", "d", "n">(rd, rn); +} +void UXTL(VReg_4S rd, VReg_4H rn) +{ + emit<"001011110001h000101001nnnnnddddd", "d", "n">(rd, rn); +} +void UXTL2(VReg_4S rd, VReg_8H rn) +{ + emit<"011011110001h000101001nnnnnddddd", "d", "n">(rd, rn); +} +void UXTL(VReg_2D rd, VReg_2S rn) +{ + emit<"00101111001hh000101001nnnnnddddd", "d", "n">(rd, rn); +} +void UXTL2(VReg_2D rd, VReg_4S rn) +{ + emit<"01101111001hh000101001nnnnnddddd", "d", "n">(rd, rn); +} +void UZP1(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110000mmmmm000110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UZP1(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110000mmmmm000110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UZP1(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110010mmmmm000110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UZP1(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110010mmmmm000110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UZP1(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110100mmmmm000110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UZP1(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110100mmmmm000110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UZP1(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110110mmmmm000110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UZP2(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110000mmmmm010110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UZP2(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110000mmmmm010110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UZP2(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110010mmmmm010110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UZP2(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110010mmmmm010110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UZP2(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110100mmmmm010110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UZP2(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110100mmmmm010110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void UZP2(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110110mmmmm010110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void XTN(VReg_8B rd, VReg_8H rn) +{ + emit<"0000111000100001001010nnnnnddddd", "d", "n">(rd, rn); +} +void XTN2(VReg_16B rd, VReg_8H rn) +{ + emit<"0100111000100001001010nnnnnddddd", "d", "n">(rd, rn); +} +void XTN(VReg_4H rd, VReg_4S rn) +{ + emit<"0000111001100001001010nnnnnddddd", "d", "n">(rd, rn); +} +void XTN2(VReg_8H rd, VReg_4S rn) +{ + emit<"0100111001100001001010nnnnnddddd", "d", "n">(rd, rn); +} +void XTN(VReg_2S rd, VReg_2D rn) +{ + emit<"0000111010100001001010nnnnnddddd", "d", "n">(rd, rn); +} +void XTN2(VReg_4S rd, VReg_2D rn) +{ + emit<"0100111010100001001010nnnnnddddd", "d", "n">(rd, rn); +} +void ZIP1(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110000mmmmm001110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ZIP1(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110000mmmmm001110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ZIP1(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110010mmmmm001110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ZIP1(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110010mmmmm001110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ZIP1(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110100mmmmm001110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ZIP1(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110100mmmmm001110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ZIP1(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110110mmmmm001110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ZIP2(VReg_8B rd, VReg_8B rn, VReg_8B rm) +{ + emit<"00001110000mmmmm011110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ZIP2(VReg_16B rd, VReg_16B rn, VReg_16B rm) +{ + emit<"01001110000mmmmm011110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ZIP2(VReg_4H rd, VReg_4H rn, VReg_4H rm) +{ + emit<"00001110010mmmmm011110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ZIP2(VReg_8H rd, VReg_8H rn, VReg_8H rm) +{ + emit<"01001110010mmmmm011110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ZIP2(VReg_2S rd, VReg_2S rn, VReg_2S rm) +{ + emit<"00001110100mmmmm011110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ZIP2(VReg_4S rd, VReg_4S rn, VReg_4S rm) +{ + emit<"01001110100mmmmm011110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} +void ZIP2(VReg_2D rd, VReg_2D rn, VReg_2D rm) +{ + emit<"01001110110mmmmm011110nnnnnddddd", "d", "n", "m">(rd, rn, rm); +} diff --git a/include/oaknut/impl/imm.hpp b/include/oaknut/impl/imm.hpp new file mode 100644 index 00000000..927ebcf9 --- /dev/null +++ b/include/oaknut/impl/imm.hpp @@ -0,0 +1,317 @@ +// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime +// SPDX-License-Identifier: MIT + +#pragma once + +#include +#include +#include +#include +#include + +namespace oaknut { + +template +struct Imm { +public: + static_assert(bit_size_ != 0 && bit_size_ <= 32, "Invalid bit_size"); + static constexpr std::size_t bit_size = bit_size_; + static constexpr std::uint32_t mask = (1 << bit_size) - 1; + + constexpr /* implicit */ Imm(std::uint32_t value_) + : m_value(value_) + { + if (!is_valid(value_)) + throw "outsized Imm value"; + } + + constexpr auto operator<=>(const Imm& other) const { return m_value <=> other.m_value; } + constexpr auto operator<=>(std::uint32_t other) const { return operator<=>(Imm{other}); } + + constexpr std::uint32_t value() const { return m_value; } + + static bool is_valid(std::uint32_t value_) + { + return ((value_ & mask) == value_); + } + +private: + template + friend class BasicCodeGenerator; + std::uint32_t m_value; +}; + +enum class AddSubImmShift { + SHL_0, + SHL_12, +}; + +struct AddSubImm { +public: + constexpr AddSubImm(std::uint32_t value_, AddSubImmShift shift_) + : m_encoded(value_ | ((shift_ == AddSubImmShift::SHL_12) ? 1 << 12 : 0)) + { + if ((value_ & 0xFFF) != value_) + throw "invalid AddSubImm"; + } + + constexpr /* implicit */ AddSubImm(std::uint64_t value_) + { + if ((value_ & 0xFFF) == value_) { + m_encoded = value_; + } else if ((value_ & 0xFFF000) == value_) { + m_encoded = (value_ >> 12) | (1 << 12); + } else { + throw "invalid AddSubImm"; + } + } + + static constexpr bool is_valid(std::uint64_t value_) + { + return ((value_ & 0xFFF) == value_) || ((value_ & 0xFFF000) == value_); + } + +private: + template + friend class BasicCodeGenerator; + std::uint32_t m_encoded; +}; + +enum class MovImm16Shift { + SHL_0, + SHL_16, + SHL_32, + SHL_48, +}; + +struct MovImm16 { +public: + MovImm16(std::uint16_t value_, MovImm16Shift shift_) + : m_encoded(static_cast(value_) | (static_cast(shift_) << 16)) + {} + + constexpr /* implict */ MovImm16(std::uint64_t value_) + { + std::uint32_t shift = 0; + while (value_ != 0) { + const std::uint32_t lsw = static_cast(value_ & 0xFFFF); + if (value_ == lsw) { + m_encoded = lsw | (shift << 16); + return; + } else if (lsw != 0) { + throw "invalid MovImm16"; + } + value_ >>= 16; + shift++; + } + } + + static constexpr bool is_valid(std::uint64_t value_) + { + return ((value_ & 0xFFFF) == value_) || ((value_ & 0xFFFF0000) == value_) || ((value_ & 0xFFFF00000000) == value_) || ((value_ & 0xFFFF000000000000) == value_); + } + +private: + template + friend class BasicCodeGenerator; + std::uint32_t m_encoded = 0; +}; + +namespace detail { + +constexpr std::optional encode_bit_imm(std::uint64_t value) +{ + if (value == 0 || (~value) == 0) + return std::nullopt; + + const std::size_t rotation = std::countr_zero(value & (value + 1)); + const std::uint64_t rot_value = std::rotr(value, rotation); + + const std::size_t esize = std::countr_zero(rot_value & (rot_value + 1)); + const std::size_t ones = std::countr_one(rot_value); + + if (std::rotr(value, esize) != value) + return std::nullopt; + + const std::uint32_t S = ((-esize) << 1) | (ones - 1); + const std::uint32_t R = (esize - rotation) & (esize - 1); + const std::uint32_t N = (~S >> 6) & 1; + + return static_cast((S & 0b111111) | (R << 6) | (N << 12)); +} + +constexpr std::optional encode_bit_imm(std::uint32_t value) +{ + const std::uint64_t value_u64 = (static_cast(value) << 32) | static_cast(value); + const auto result = encode_bit_imm(value_u64); + if (result && (*result & 0b0'111111'111111) != *result) + return std::nullopt; + return result; +} + +} // namespace detail + +struct BitImm32 { +public: + constexpr BitImm32(Imm<6> imms, Imm<6> immr) + : m_encoded((imms.value() << 6) | immr.value()) + {} + + constexpr /* implicit */ BitImm32(std::uint32_t value) + { + const auto encoded = detail::encode_bit_imm(value); + if (!encoded || (*encoded & 0x1000) != 0) + throw "invalid BitImm32"; + m_encoded = *encoded; + } + +private: + template + friend class BasicCodeGenerator; + std::uint32_t m_encoded; +}; + +struct BitImm64 { +public: + constexpr BitImm64(bool N, Imm<6> imms, Imm<6> immr) + : m_encoded((N ? 1 << 12 : 0) | (imms.value() << 6) | immr.value()) + {} + + constexpr /* implicit */ BitImm64(std::uint64_t value) + { + const auto encoded = detail::encode_bit_imm(value); + if (!encoded) + throw "invalid BitImm64"; + m_encoded = *encoded; + } + +private: + template + friend class BasicCodeGenerator; + std::uint32_t m_encoded; +}; + +struct FImm8 { +public: + constexpr explicit FImm8(std::uint8_t encoded) + : m_encoded(encoded) + {} + + constexpr FImm8(bool sign, Imm<3> exp, Imm<4> mantissa) + : m_encoded((sign ? 1 << 7 : 0) | (exp.value() << 4) | (mantissa.value())) + {} + +private: + template + friend class BasicCodeGenerator; + std::uint32_t m_encoded; +}; + +struct RepImm { +public: + constexpr explicit RepImm(std::uint8_t encoded) + : m_encoded(encoded) + {} + +private: + template + friend class BasicCodeGenerator; + std::uint32_t m_encoded; +}; + +template +struct ImmConst { + constexpr /* implicit */ ImmConst(int value) + { + if (value != A) { + throw "invalid ImmConst"; + } + } +}; + +struct ImmConstFZero { + constexpr /* implicit */ ImmConstFZero(double value) + { + if (value != 0) { + throw "invalid ImmConstFZero"; + } + } +}; + +template +struct ImmChoice; + +template +struct ImmChoice { + constexpr /* implicit */ ImmChoice(int value) + { + if (value == A) { + m_encoded = 0; + } else if (value == B) { + m_encoded = 1; + } else { + throw "invalid ImmChoice"; + } + } + +private: + template + friend class BasicCodeGenerator; + std::uint32_t m_encoded; +}; + +template +struct ImmChoice { + constexpr /* implicit */ ImmChoice(int value) + { + if (value == A) { + m_encoded = 0; + } else if (value == B) { + m_encoded = 1; + } else if (value == C) { + m_encoded = 2; + } else if (value == D) { + m_encoded = 3; + } else { + throw "invalid ImmChoice"; + } + } + +private: + template + friend class BasicCodeGenerator; + std::uint32_t m_encoded; +}; + +template +struct ImmRange { + constexpr /* implicit */ ImmRange(unsigned value_) + : m_value(value_) + { + if (value_ < Start || value_ > End) { + throw "invalid ImmRange"; + } + } + + constexpr unsigned value() const { return m_value; } + +private: + unsigned m_value; +}; + +template +struct LslShift { + constexpr /* implicit */ LslShift(std::size_t amount) + : m_encoded((((-amount) & (max_value - 1)) << 6) | (max_value - amount - 1)) + { + if (amount >= max_value) + throw "LslShift out of range"; + } + +private: + template + friend class BasicCodeGenerator; + std::uint32_t m_encoded; +}; + +} // namespace oaknut diff --git a/include/oaknut/impl/list.hpp b/include/oaknut/impl/list.hpp new file mode 100644 index 00000000..9ad4bd9b --- /dev/null +++ b/include/oaknut/impl/list.hpp @@ -0,0 +1,80 @@ +// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime +// SPDX-License-Identifier: MIT + +#pragma once + +#include +#include +#include + +namespace oaknut { + +struct Elem; +template +struct ElemSelector; +struct VRegArranged; + +namespace detail { + +template +struct is_instance_of_ElemSelector : std::false_type {}; + +template +struct is_instance_of_ElemSelector> : std::true_type {}; + +template +constexpr bool is_instance_of_ElemSelector_v = is_instance_of_ElemSelector::value; + +struct BaseOnlyTag {}; + +} // namespace detail + +template +struct List { + template + constexpr explicit List(U... args) + : m_base(std::get<0>(std::tie(args...))) + { + static_assert((std::is_same_v && ...)); + static_assert(sizeof...(args) == N); + static_assert(std::is_base_of_v || std::is_base_of_v || detail::is_instance_of_ElemSelector_v); + + if (!verify(std::index_sequence_for{}, args...)) + throw "invalid List"; + } + + constexpr auto operator[](unsigned elem_index) const + { + using S = decltype(m_base[elem_index]); + return List(detail::BaseOnlyTag{}, m_base[elem_index]); + } + +private: + template + friend class BasicCodeGenerator; + template + friend struct List; + + constexpr explicit List(detail::BaseOnlyTag, T base_) + : m_base(base_) + {} + + template + constexpr bool verify(std::index_sequence, U... args) + { + if constexpr (std::is_base_of_v) { + return (((m_base.index() + indexes) % 32 == static_cast(args.index())) && ...); + } else if constexpr (std::is_base_of_v) { + return (((m_base.reg_index() + indexes) % 32 == static_cast(args.reg_index()) && m_base.elem_index() == args.elem_index()) && ...); + } else { + return (((m_base.reg_index() + indexes) % 32 == static_cast(args.reg_index())) && ...); + } + } + + T m_base; +}; + +template +List(U...) -> List, sizeof...(U)>; + +} // namespace oaknut diff --git a/include/oaknut/impl/multi_typed_name.hpp b/include/oaknut/impl/multi_typed_name.hpp new file mode 100644 index 00000000..d0a113c8 --- /dev/null +++ b/include/oaknut/impl/multi_typed_name.hpp @@ -0,0 +1,19 @@ +// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime +// SPDX-License-Identifier: MIT + +#pragma once + +namespace oaknut { + +template +struct MultiTypedName; + +template<> +struct MultiTypedName<> {}; + +template +struct MultiTypedName : public MultiTypedName { + constexpr operator decltype(V)() const { return V; } +}; + +} // namespace oaknut diff --git a/include/oaknut/impl/offset.hpp b/include/oaknut/impl/offset.hpp new file mode 100644 index 00000000..4f66dac6 --- /dev/null +++ b/include/oaknut/impl/offset.hpp @@ -0,0 +1,129 @@ +// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime +// SPDX-License-Identifier: MIT + +#pragma once + +#include +#include +#include + +namespace oaknut { + +struct Label; + +namespace detail { + +constexpr std::uint64_t inverse_mask_from_size(std::size_t size) +{ + return (~std::uint64_t{0}) << size; +} + +constexpr std::uint64_t mask_from_size(std::size_t size) +{ + return (~std::uint64_t{0}) >> (64 - size); +} + +template +constexpr std::uint64_t sign_extend(std::uint64_t value) +{ + static_assert(bit_count != 0, "cannot sign-extend zero-sized value"); + constexpr size_t shift_amount = 64 - bit_count; + return static_cast(static_cast(value << shift_amount) >> shift_amount); +} + +} // namespace detail + +template +struct AddrOffset { + AddrOffset(std::ptrdiff_t diff) + : m_payload(encode(diff)) + {} + + AddrOffset(Label& label) + : m_payload(&label) + {} + + AddrOffset(void* ptr) + : m_payload(ptr) + {} + + static std::uint32_t encode(std::ptrdiff_t diff) + { + const std::uint64_t diff_u64 = static_cast(diff); + if (detail::sign_extend(diff_u64) != diff_u64) + throw "out of range"; + if (diff_u64 != (diff_u64 & detail::inverse_mask_from_size(alignment))) + throw "misalignment"; + + return static_cast((diff_u64 & detail::mask_from_size(bitsize)) >> alignment); + } + +private: + template + friend class BasicCodeGenerator; + std::variant m_payload; +}; + +template +struct PageOffset { + PageOffset(void* ptr) + : m_payload(ptr) + {} + + PageOffset(Label& label) + : m_payload(&label) + {} + + static std::uint32_t encode(std::uintptr_t current_addr, std::uintptr_t target) + { + const std::int64_t page_diff = (static_cast(target) >> 12) - (static_cast(current_addr) >> 12); + if (detail::sign_extend(page_diff) != page_diff) + throw "out of range"; + return static_cast(page_diff & detail::mask_from_size(bitsize)); + } + +private: + template + friend class BasicCodeGenerator; + std::variant m_payload; +}; + +template +struct SOffset { + SOffset(std::int64_t offset) + { + const std::uint64_t diff_u64 = static_cast(offset); + if (detail::sign_extend(diff_u64) != diff_u64) + throw "out of range"; + if (diff_u64 != (diff_u64 & detail::inverse_mask_from_size(alignment))) + throw "misalignment"; + + m_encoded = static_cast((diff_u64 & detail::mask_from_size(bitsize)) >> alignment); + } + +private: + template + friend class BasicCodeGenerator; + std::uint32_t m_encoded; +}; + +template +struct POffset { + POffset(std::int64_t offset) + { + const std::uint64_t diff_u64 = static_cast(offset); + if (diff_u64 > detail::mask_from_size(bitsize)) + throw "out of range"; + if (diff_u64 != (diff_u64 & detail::inverse_mask_from_size(alignment))) + throw "misalignment"; + + m_encoded = static_cast((diff_u64 & detail::mask_from_size(bitsize)) >> alignment); + } + +private: + template + friend class BasicCodeGenerator; + std::uint32_t m_encoded; +}; + +} // namespace oaknut diff --git a/include/oaknut/impl/reg.hpp b/include/oaknut/impl/reg.hpp new file mode 100644 index 00000000..aad2fd54 --- /dev/null +++ b/include/oaknut/impl/reg.hpp @@ -0,0 +1,441 @@ +// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime +// SPDX-License-Identifier: MIT + +#pragma once + +#include +#include +#include + +namespace oaknut { + +struct Reg; + +struct RReg; +struct ZrReg; +struct WzrReg; +struct XReg; +struct WReg; +struct SpReg; +struct WspReg; +struct XRegSp; +struct XRegWsp; + +struct VReg; +struct VRegArranged; +struct BReg; +struct HReg; +struct SReg; +struct DReg; +struct QReg; +struct VReg_8B; +struct VReg_4H; +struct VReg_2S; +struct VReg_1D; +struct VReg_16B; +struct VReg_8H; +struct VReg_4S; +struct VReg_2D; +struct VReg_1Q; + +struct VRegSelector; + +template +struct ElemSelector; +struct BElem; +struct HElem; +struct SElem; +struct DElem; + +struct Reg { + constexpr explicit Reg(bool is_vector_, unsigned bitsize_, int index_) + : m_index(index_) + , m_bitsize(bitsize_) + , m_is_vector(is_vector_) + { + assert(index_ >= -1 && index_ <= 31); + assert(bitsize_ != 0 && (bitsize_ & (bitsize_ - 1)) == 0 && "Bitsize must be a power of two"); + } + + constexpr int index() const { return m_index; } + constexpr unsigned bitsize() const { return m_bitsize; } + constexpr bool is_vector() const { return m_is_vector; } + +private: + int m_index : 8; + unsigned m_bitsize : 8; + bool m_is_vector; +}; + +struct RReg : public Reg { + constexpr explicit RReg(unsigned bitsize_, int index_) + : Reg(false, bitsize_, index_) + { + assert(bitsize_ == 32 || bitsize_ == 64); + } + + XReg toX() const; + WReg toW() const; + + template + friend class BasicCodeGenerator; +}; + +struct ZrReg : public RReg { + constexpr explicit ZrReg() + : RReg(64, 31) {} +}; + +struct WzrReg : public RReg { + constexpr explicit WzrReg() + : RReg(32, 31) {} +}; + +struct XReg : public RReg { + constexpr explicit XReg(int index_) + : RReg(64, index_) {} + + constexpr /* implicit */ XReg(ZrReg) + : RReg(64, 31) {} + + template + friend class BasicCodeGenerator; +}; + +struct WReg : public RReg { + constexpr explicit WReg(int index_) + : RReg(32, index_) {} + + constexpr /* implicit */ WReg(WzrReg) + : RReg(32, 31) {} + + template + friend class BasicCodeGenerator; +}; + +inline XReg RReg::toX() const +{ + if (index() == -1) + throw "cannot convert SP/WSP to XReg"; + return XReg{index()}; +} + +inline WReg RReg::toW() const +{ + if (index() == -1) + throw "cannot convert SP/WSP to WReg"; + return WReg{index()}; +} + +struct SpReg : public RReg { + constexpr explicit SpReg() + : RReg(64, -1) {} +}; + +struct WspReg : public RReg { + constexpr explicit WspReg() + : RReg(64, -1) {} +}; + +struct XRegSp : public RReg { + constexpr /* implict */ XRegSp(SpReg) + : RReg(64, -1) {} + + constexpr /* implict */ XRegSp(XReg xr) + : RReg(64, xr.index()) + { + if (xr.index() == 31) + throw "unexpected ZR passed into an XRegSp"; + } + + template + friend class BasicCodeGenerator; +}; + +struct WRegWsp : public RReg { + constexpr /* implict */ WRegWsp(WspReg) + : RReg(32, -1) {} + + constexpr /* implict */ WRegWsp(WReg wr) + : RReg(32, wr.index()) + { + if (wr.index() == 31) + throw "unexpected WZR passed into an WRegWsp"; + } + + template + friend class BasicCodeGenerator; +}; + +struct VReg : public Reg { + constexpr explicit VReg(unsigned bitsize_, int index_) + : Reg(true, bitsize_, index_) + { + assert(bitsize_ == 8 || bitsize_ == 16 || bitsize_ == 32 || bitsize_ == 64 || bitsize_ == 128); + } + + constexpr BReg toB() const; + constexpr HReg toH() const; + constexpr SReg toS() const; + constexpr DReg toD() const; + constexpr QReg toQ() const; + + template + friend class BasicCodeGenerator; +}; + +struct VRegArranged : public Reg { + constexpr explicit VRegArranged(unsigned bitsize_, int index_, unsigned esize_) + : Reg(true, bitsize_, index_), m_esize(esize_) + { + assert(bitsize_ == 64 || bitsize_ == 128); + assert(esize_ != 0 && (esize_ & (esize_ - 1)) == 0 && "esize must be a power of two"); + assert(esize_ <= bitsize_); + } + + template + friend class BasicCodeGenerator; + +private: + int m_esize : 8; +}; + +struct BReg : public VReg { + constexpr explicit BReg(int index_) + : VReg(8, index_) + {} + + template + friend class BasicCodeGenerator; +}; + +struct HReg : public VReg { + constexpr explicit HReg(int index_) + : VReg(16, index_) + {} + + template + friend class BasicCodeGenerator; +}; + +struct SReg : public VReg { + constexpr explicit SReg(int index_) + : VReg(32, index_) + {} + + template + friend class BasicCodeGenerator; +}; + +struct DReg : public VReg { + constexpr explicit DReg(int index_) + : VReg(64, index_) + {} + + template + friend class BasicCodeGenerator; +}; + +struct QReg : public VReg { + constexpr explicit QReg(int index_) + : VReg(128, index_) + {} + + template + friend class BasicCodeGenerator; +}; + +struct VReg_8B : public VRegArranged { + constexpr explicit VReg_8B(int reg_index_) + : VRegArranged(64, reg_index_, 64 / 8) + {} + + template + friend class BasicCodeGenerator; +}; + +struct VReg_4H : public VRegArranged { + constexpr explicit VReg_4H(int reg_index_) + : VRegArranged(64, reg_index_, 64 / 4) + {} + + template + friend class BasicCodeGenerator; +}; + +struct VReg_2S : public VRegArranged { + constexpr explicit VReg_2S(int reg_index_) + : VRegArranged(64, reg_index_, 64 / 2) + {} + + template + friend class BasicCodeGenerator; +}; + +struct VReg_1D : public VRegArranged { + constexpr explicit VReg_1D(int reg_index_) + : VRegArranged(64, reg_index_, 64 / 1) + {} + + template + friend class BasicCodeGenerator; +}; + +struct VReg_16B : public VRegArranged { + constexpr explicit VReg_16B(int reg_index_) + : VRegArranged(128, reg_index_, 128 / 16) + {} + + template + friend class BasicCodeGenerator; +}; + +struct VReg_8H : public VRegArranged { + constexpr explicit VReg_8H(int reg_index_) + : VRegArranged(128, reg_index_, 128 / 8) + {} + + template + friend class BasicCodeGenerator; +}; + +struct VReg_4S : public VRegArranged { + constexpr explicit VReg_4S(int reg_index_) + : VRegArranged(128, reg_index_, 128 / 4) + {} + + template + friend class BasicCodeGenerator; +}; + +struct VReg_2D : public VRegArranged { + constexpr explicit VReg_2D(int reg_index_) + : VRegArranged(128, reg_index_, 128 / 2) + {} + + template + friend class BasicCodeGenerator; +}; + +struct VReg_1Q : public VRegArranged { + constexpr explicit VReg_1Q(int reg_index_) + : VRegArranged(128, reg_index_, 128 / 1) + {} + + template + friend class BasicCodeGenerator; +}; + +struct Elem { + constexpr explicit Elem(unsigned esize_, int reg_, unsigned elem_index_) + : m_esize(esize_), m_reg(reg_), m_elem_index(elem_index_) + { + if (elem_index_ >= 128 / esize_) + throw "invalid elem_index"; + } + + constexpr unsigned esize() const { return m_esize; } + constexpr int reg_index() const { return m_reg; } + constexpr unsigned elem_index() const { return m_elem_index; } + +private: + unsigned m_esize; + int m_reg; + unsigned m_elem_index; +}; + +template +struct ElemSelector { + constexpr explicit ElemSelector(int reg_index_) + : m_reg_index(reg_index_) + {} + + constexpr int reg_index() const { return m_reg_index; } + + constexpr E operator[](unsigned elem_index) const { return E{m_reg_index, elem_index}; } + +private: + int m_reg_index; +}; + +struct BElem : public Elem { + constexpr explicit BElem(int reg_, unsigned elem_index_) + : Elem(2, reg_, elem_index_) + {} +}; + +struct HElem : public Elem { + constexpr explicit HElem(int reg_, unsigned elem_index_) + : Elem(2, reg_, elem_index_) + {} +}; + +struct SElem : public Elem { + constexpr explicit SElem(int reg_, unsigned elem_index_) + : Elem(4, reg_, elem_index_) + {} +}; + +struct DElem : public Elem { + constexpr explicit DElem(int reg_, unsigned elem_index_) + : Elem(8, reg_, elem_index_) + {} +}; + +struct DElem_1 : public DElem { + constexpr /* implict */ DElem_1(DElem inner) + : DElem(inner) + { + if (inner.elem_index() != 1) + throw "invalid DElem_1"; + } +}; + +constexpr BReg VReg::toB() const +{ + return BReg{index()}; +} +constexpr HReg VReg::toH() const +{ + return HReg{index()}; +} +constexpr SReg VReg::toS() const +{ + return SReg{index()}; +} +constexpr DReg VReg::toD() const +{ + return DReg{index()}; +} +constexpr QReg VReg::toQ() const +{ + return QReg{index()}; +} + +struct VRegSelector { + constexpr explicit VRegSelector(int reg_index) + : m_reg_index(reg_index) + {} + + constexpr int index() const { return m_reg_index; } + + constexpr ElemSelector B() const { return ElemSelector(index()); } + constexpr ElemSelector H() const { return ElemSelector(index()); } + constexpr ElemSelector S() const { return ElemSelector(index()); } + constexpr ElemSelector D() const { return ElemSelector(index()); } + + constexpr VReg_8B B8() const { return VReg_8B{index()}; } + constexpr VReg_4H H4() const { return VReg_4H{index()}; } + constexpr VReg_2S S2() const { return VReg_2S{index()}; } + constexpr VReg_1D D1() const { return VReg_1D{index()}; } + constexpr VReg_16B B16() const { return VReg_16B{index()}; } + constexpr VReg_8H H8() const { return VReg_8H{index()}; } + constexpr VReg_4S S4() const { return VReg_4S{index()}; } + constexpr VReg_2D D2() const { return VReg_2D{index()}; } + constexpr VReg_1Q Q1() const { return VReg_1Q{index()}; } + +private: + int m_reg_index; +}; + +} // namespace oaknut diff --git a/include/oaknut/impl/string_literal.hpp b/include/oaknut/impl/string_literal.hpp new file mode 100644 index 00000000..e09dfa65 --- /dev/null +++ b/include/oaknut/impl/string_literal.hpp @@ -0,0 +1,24 @@ +// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime +// SPDX-License-Identifier: MIT + +#pragma once + +#include +#include + +namespace oaknut { + +template +struct StringLiteral { + constexpr StringLiteral(const char (&str)[N]) + { + std::copy_n(str, N, value); + } + + static constexpr std::size_t strlen = N - 1; + static constexpr std::size_t size = N; + + char value[N]; +}; + +} // namespace oaknut diff --git a/include/oaknut/oaknut.hpp b/include/oaknut/oaknut.hpp new file mode 100644 index 00000000..ce0e96e7 --- /dev/null +++ b/include/oaknut/oaknut.hpp @@ -0,0 +1,306 @@ +// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime +// SPDX-License-Identifier: MIT + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "oaknut/impl/enum.hpp" +#include "oaknut/impl/imm.hpp" +#include "oaknut/impl/list.hpp" +#include "oaknut/impl/multi_typed_name.hpp" +#include "oaknut/impl/offset.hpp" +#include "oaknut/impl/reg.hpp" +#include "oaknut/impl/string_literal.hpp" + +namespace oaknut { + +namespace detail { + +template +constexpr std::uint32_t get_bits() +{ + std::uint32_t result = 0; + for (std::size_t i = 0; i < 32; i++) { + for (std::size_t a = 0; a < barg.strlen; a++) { + if (bs.value[i] == barg.value[a]) { + result |= 1 << (31 - i); + } + } + } + return result; +} + +template +struct overloaded : Ts... { + using Ts::operator()...; +}; + +template +overloaded(Ts...) -> overloaded; + +} // namespace detail + +struct Label { +public: + Label() = default; + +private: + template + friend class BasicCodeGenerator; + + explicit Label(std::uintptr_t addr) + : m_addr(addr) + {} + + using EmitFunctionType = std::uint32_t (*)(std::uintptr_t wb_addr, std::uintptr_t resolved_addr); + + struct Writeback { + std::uintptr_t m_wb_addr; + std::uint32_t m_mask; + EmitFunctionType m_fn; + }; + + std::optional m_addr; + std::vector m_wbs; +}; + +template +class BasicCodeGenerator : public Policy { +public: + BasicCodeGenerator(typename Policy::constructor_argument_type arg) + : Policy(arg) + {} + + Label l() + { + return Label{Policy::current_address()}; + } + + void l(Label& label) + { + if (label.m_addr) + throw "label already resolved"; + + const auto target_addr = Policy::current_address(); + label.m_addr = target_addr; + for (auto& wb : label.m_wbs) { + const std::uint32_t value = wb.m_fn(wb.m_wb_addr, target_addr); + Policy::set_at_address(wb.m_wb_addr, value, wb.m_mask); + } + label.m_wbs.clear(); + } + +#include "oaknut/impl/arm64_mnemonics.inc.hpp" +#include "oaknut/impl/fpsimd_mnemonics.inc.hpp" + + void RET() + { + return RET(XReg{30}); + } + + void MOV(WReg wd, uint32_t imm) + { + if (wd.index() == 31) + return; + if (MovImm16::is_valid(imm)) + return MOVZ(wd, imm); + if (MovImm16::is_valid(~static_cast(imm))) + return MOVN(wd, imm); + if (detail::encode_bit_imm(imm)) + return ORR(wd, WzrReg{}, imm); + + MOVZ(wd, {static_cast(imm >> 0), MovImm16Shift::SHL_0}); + MOVK(wd, {static_cast(imm >> 16), MovImm16Shift::SHL_16}); + } + + void MOV(XReg xd, uint64_t imm) + { + if (xd.index() == 31) + return; + if (imm >> 32 == 0) + return MOV(xd.toW(), static_cast(imm)); + if (MovImm16::is_valid(imm)) + return MOVZ(xd, imm); + if (MovImm16::is_valid(~imm)) + return MOVN(xd, imm); + if (detail::encode_bit_imm(imm)) + return ORR(xd, ZrReg{}, imm); + + bool movz_done = false; + int shift_count = 0; + + if (detail::encode_bit_imm(static_cast(imm))) { + ORR(xd.toW(), WzrReg{}, static_cast(imm)); + imm >>= 32; + movz_done = true; + shift_count = 2; + } + + while (imm != 0) { + const uint16_t hw = static_cast(imm); + if (hw != 0) { + if (movz_done) { + MOVK(xd, {hw, static_cast(shift_count)}); + } else { + MOVZ(xd, {hw, static_cast(shift_count)}); + movz_done = true; + } + } + imm >>= 16; + shift_count++; + } + } + +private: +#include "oaknut/impl/arm64_encode_helpers.inc.hpp" + + template + void emit(Ts... args) + { + std::uint32_t encoding = detail::get_bits(); + encoding |= (0 | ... | encode()>(std::forward(args))); + Policy::append(encoding); + } + + template + std::uint32_t encode(AddrOffset v) + { + static_assert(std::popcount(splat) == size - align); + + const auto encode_fn = [](std::uintptr_t current_addr, std::uintptr_t target) { + const std::ptrdiff_t diff = target - current_addr; + return pdep(AddrOffset::encode(diff)); + }; + + return std::visit(detail::overloaded{ + [&](std::uint32_t encoding) { + return pdep(encoding); + }, + [&](Label* label) { + if (label->m_addr) { + return encode_fn(Policy::current_address(), *label->m_addr); + } + + label->m_wbs.emplace_back(Label::Writeback{Policy::current_address(), ~splat, static_cast(encode_fn)}); + return 0u; + }, + [&](void* p) { + return encode_fn(Policy::current_address(), reinterpret_cast(p)); + }, + }, + v.m_payload); + } + + template + std::uint32_t encode(PageOffset v) + { + static_assert(std::popcount(splat) == size); + + const auto encode_fn = [](std::uintptr_t current_addr, std::uintptr_t target) { + return pdep(PageOffset::encode(current_addr, target)); + }; + + return std::visit(detail::overloaded{ + [&](Label* label) { + if (label->m_addr) { + return encode_fn(Policy::current_address(), *label->m_addr); + } + + label->m_wbs.emplace_back(Label::Writeback{Policy::current_address(), ~splat, static_cast(encode_fn)}); + return 0u; + }, + [&](void* p) { + return encode_fn(Policy::current_address(), reinterpret_cast(p)); + }, + }, + v.m_payload); + } +}; + +struct PointerCodeGeneratorPolicy { +public: + template + T ptr() + { + static_assert(std::is_pointer_v); + return reinterpret_cast(m_ptr); + } + + void set_ptr(std::uint32_t* ptr_) + { + m_ptr = ptr_; + } + +protected: + using constructor_argument_type = std::uint32_t*; + + PointerCodeGeneratorPolicy(std::uint32_t* ptr_) + : m_ptr(ptr_) + {} + + void append(std::uint32_t instruction) + { + *m_ptr++ = instruction; + } + + std::uintptr_t current_address() + { + return reinterpret_cast(m_ptr); + } + + void set_at_address(std::uintptr_t addr, std::uint32_t value, std::uint32_t mask) + { + std::uint32_t* p = reinterpret_cast(addr); + *p = (*p & mask) | value; + } + +private: + std::uint32_t* m_ptr; +}; + +using CodeGenerator = BasicCodeGenerator; + +namespace util { + +inline constexpr WReg W0{0}, W1{1}, W2{2}, W3{3}, W4{4}, W5{5}, W6{6}, W7{7}, W8{8}, W9{9}, W10{10}, W11{11}, W12{12}, W13{13}, W14{14}, W15{15}, W16{16}, W17{17}, W18{18}, W19{19}, W20{20}, W21{21}, W22{22}, W23{23}, W24{24}, W25{25}, W26{26}, W27{27}, W28{28}, W29{29}, W30{30}; +inline constexpr XReg X0{0}, X1{1}, X2{2}, X3{3}, X4{4}, X5{5}, X6{6}, X7{7}, X8{8}, X9{9}, X10{10}, X11{11}, X12{12}, X13{13}, X14{14}, X15{15}, X16{16}, X17{17}, X18{18}, X19{19}, X20{20}, X21{21}, X22{22}, X23{23}, X24{24}, X25{25}, X26{26}, X27{27}, X28{28}, X29{29}, X30{30}; +inline constexpr ZrReg ZR{}, XZR{}; +inline constexpr WzrReg WZR{}; +inline constexpr SpReg SP{}, XSP{}; +inline constexpr WspReg WSP{}; + +inline constexpr VRegSelector V0{0}, V1{1}, V2{2}, V3{3}, V4{4}, V5{5}, V6{6}, V7{7}, V8{8}, V9{9}, V10{10}, V11{11}, V12{12}, V13{13}, V14{14}, V15{15}, V16{16}, V17{17}, V18{18}, V19{19}, V20{20}, V21{21}, V22{22}, V23{23}, V24{24}, V25{25}, V26{26}, V27{27}, V28{28}, V29{29}, V30{30}, V31{31}; +inline constexpr QReg Q0{0}, Q1{1}, Q2{2}, Q3{3}, Q4{4}, Q5{5}, Q6{6}, Q7{7}, Q8{8}, Q9{9}, Q10{10}, Q11{11}, Q12{12}, Q13{13}, Q14{14}, Q15{15}, Q16{16}, Q17{17}, Q18{18}, Q19{19}, Q20{20}, Q21{21}, Q22{22}, Q23{23}, Q24{24}, Q25{25}, Q26{26}, Q27{27}, Q28{28}, Q29{29}, Q30{30}, Q31{31}; +inline constexpr DReg D0{0}, D1{1}, D2{2}, D3{3}, D4{4}, D5{5}, D6{6}, D7{7}, D8{8}, D9{9}, D10{10}, D11{11}, D12{12}, D13{13}, D14{14}, D15{15}, D16{16}, D17{17}, D18{18}, D19{19}, D20{20}, D21{21}, D22{22}, D23{23}, D24{24}, D25{25}, D26{26}, D27{27}, D28{28}, D29{29}, D30{30}, D31{31}; +inline constexpr SReg S0{0}, S1{1}, S2{2}, S3{3}, S4{4}, S5{5}, S6{6}, S7{7}, S8{8}, S9{9}, S10{10}, S11{11}, S12{12}, S13{13}, S14{14}, S15{15}, S16{16}, S17{17}, S18{18}, S19{19}, S20{20}, S21{21}, S22{22}, S23{23}, S24{24}, S25{25}, S26{26}, S27{27}, S28{28}, S29{29}, S30{30}, S31{31}; +inline constexpr HReg H0{0}, H1{1}, H2{2}, H3{3}, H4{4}, H5{5}, H6{6}, H7{7}, H8{8}, H9{9}, H10{10}, H11{11}, H12{12}, H13{13}, H14{14}, H15{15}, H16{16}, H17{17}, H18{18}, H19{19}, H20{20}, H21{21}, H22{22}, H23{23}, H24{24}, H25{25}, H26{26}, H27{27}, H28{28}, H29{29}, H30{30}, H31{31}; +inline constexpr BReg B0{0}, B1{1}, B2{2}, B3{3}, B4{4}, B5{5}, B6{6}, B7{7}, B8{8}, B9{9}, B10{10}, B11{11}, B12{12}, B13{13}, B14{14}, B15{15}, B16{16}, B17{17}, B18{18}, B19{19}, B20{20}, B21{21}, B22{22}, B23{23}, B24{24}, B25{25}, B26{26}, B27{27}, B28{28}, B29{29}, B30{30}, B31{31}; + +inline constexpr Cond EQ{Cond::EQ}, NE{Cond::NE}, CS{Cond::CS}, CC{Cond::CC}, MI{Cond::MI}, PL{Cond::PL}, VS{Cond::VS}, VC{Cond::VC}, HI{Cond::HI}, LS{Cond::LS}, GE{Cond::GE}, LT{Cond::LT}, GT{Cond::GT}, LE{Cond::LE}, AL{Cond::AL}, NV{Cond::NV}, HS{Cond::HS}, LO{Cond::LO}; + +inline constexpr auto UXTB{MultiTypedName{}}; +inline constexpr auto UXTH{MultiTypedName{}}; +inline constexpr auto UXTW{MultiTypedName{}}; +inline constexpr auto UXTX{MultiTypedName{}}; +inline constexpr auto SXTB{MultiTypedName{}}; +inline constexpr auto SXTH{MultiTypedName{}}; +inline constexpr auto SXTW{MultiTypedName{}}; +inline constexpr auto SXTX{MultiTypedName{}}; +inline constexpr auto LSL{MultiTypedName{}}; +inline constexpr auto LSR{MultiTypedName{}}; +inline constexpr auto ASR{MultiTypedName{}}; +inline constexpr auto ROR{MultiTypedName{}}; + +inline constexpr PostIndexed POST_INDEXED{}; +inline constexpr PreIndexed PRE_INDEXED{}; +inline constexpr MslSymbol MSL{MslSymbol::MSL}; + +} // namespace util + +} // namespace oaknut diff --git a/tests/basic.cpp b/tests/basic.cpp new file mode 100644 index 00000000..2f11c316 --- /dev/null +++ b/tests/basic.cpp @@ -0,0 +1,117 @@ +// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime +// SPDX-License-Identifier: MIT + +#include +#include + +#include + +#include "oaknut/code_block.hpp" +#include "oaknut/oaknut.hpp" +#include "rand_int.hpp" + +using namespace oaknut; +using namespace oaknut::util; + +TEST_CASE("Basic Test") +{ + CodeBlock mem{4096}; + CodeGenerator code{mem.ptr()}; + + mem.unprotect(); + + code.MOV(W0, 42); + code.RET(); + + mem.protect(); + mem.invalidate_all(); + + int result = ((int (*)())mem.ptr())(); + REQUIRE(result == 42); +} + +TEST_CASE("Fibonacci") +{ + CodeBlock mem{4096}; + CodeGenerator code{mem.ptr()}; + + mem.unprotect(); + + auto fib = code.ptr(); + Label start, end, zero, recurse; + + code.l(start); + code.STP(X29, X30, SP, PRE_INDEXED, -32); + code.STP(X20, X19, SP, 16); + code.MOV(X29, SP); + code.MOV(W19, W0); + code.SUBS(W0, W0, 1); + code.B(LT, zero); + code.B(NE, recurse); + code.MOV(W0, 1); + code.B(end); + + code.l(zero); + code.MOV(W0, WZR); + code.B(end); + + code.l(recurse); + code.BL(start); + code.MOV(W20, W0); + code.SUB(W0, W19, 2); + code.BL(start); + code.ADD(W0, W0, W20); + + code.l(end); + code.LDP(X20, X19, SP, 16); + code.LDP(X29, X30, SP, POST_INDEXED, 32); + code.RET(); + + mem.protect(); + mem.invalidate_all(); + + REQUIRE(fib(0) == 0); + REQUIRE(fib(1) == 1); + REQUIRE(fib(5) == 5); + REQUIRE(fib(9) == 34); +} + +TEST_CASE("Immediate generation (32-bit)") +{ + CodeBlock mem{4096}; + + for (int i = 0; i < 0x100000; i++) { + const std::uint32_t value = RandInt(0, 0xffffffff); + + CodeGenerator code{mem.ptr()}; + + auto f = code.ptr(); + mem.unprotect(); + code.MOV(W0, value); + code.RET(); + mem.protect(); + mem.invalidate_all(); + + REQUIRE(f() == value); + } +} + +TEST_CASE("Immediate generation (64-bit)") +{ + CodeBlock mem{4096}; + + for (int i = 0; i < 0x100000; i++) { + const std::uint64_t value = RandInt(0, 0xffffffff'ffffffff); + + CodeGenerator code{mem.ptr()}; + + auto f = code.ptr(); + mem.unprotect(); + code.MOV(X0, value); + code.RET(); + mem.protect(); + mem.invalidate_all(); + + REQUIRE(f() == value); + } +} diff --git a/tests/fpsimd.cpp b/tests/fpsimd.cpp new file mode 100644 index 00000000..3d71d862 --- /dev/null +++ b/tests/fpsimd.cpp @@ -0,0 +1,785 @@ +// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime +// SPDX-License-Identifier: MIT + +#include +#include + +#include + +#include "oaknut/oaknut.hpp" + +#define T(HEX, CMD) \ + TEST_CASE(#CMD) \ + { \ + using namespace oaknut; \ + using namespace oaknut::util; \ + \ + std::uint32_t result; \ + CodeGenerator code{&result}; \ + \ + code.CMD; \ + \ + REQUIRE(result == HEX); \ + } + +T(0x5ee0bb61, ABS(D1, D27)) +T(0x4e20ba03, ABS(V3.B16(), V16.B16())) +T(0x5ef98449, ADD(D9, D2, D25)) +T(0x4eef8697, ADD(V23.D2(), V20.D2(), V15.D2())) +T(0x0eb743d1, ADDHN(V17.S2(), V30.D2(), V23.D2())) +T(0x5ef1b933, ADDP(D19, V9.D2())) +T(0x0e7ebf6e, ADDP(V14.H4(), V27.H4(), V30.H4())) +T(0x4e31ba47, ADDV(B7, V18.B16())) +// AESD +// AESE +// AESIMC +// AESMC +T(0x4e2b1d4c, AND(V12.B16(), V10.B16(), V11.B16())) +T(0x6f01b7f4, BIC(V20.H8(), 63, LSL, 8)) +T(0x2f017752, BIC(V18.S2(), 58, LSL, 24)) +T(0x0e751c85, BIC(V5.B8(), V4.B8(), V21.B8())) +T(0x2ef11d4d, BIF(V13.B8(), V10.B8(), V17.B8())) +T(0x2eb31f3b, BIT(V27.B8(), V25.B8(), V19.B8())) +T(0x2e711ed8, BSL(V24.B8(), V22.B8(), V17.B8())) +T(0x0e604aaf, CLS(V15.H4(), V21.H4())) +T(0x6e604808, CLZ(V8.H8(), V0.H8())) +T(0x7eff8ec2, CMEQ(D2, D22, D31)) +T(0x2e2b8d57, CMEQ(V23.B8(), V10.B8(), V11.B8())) +T(0x5ee09bbf, CMEQ(D31, D29, 0)) +T(0x4ea09876, CMEQ(V22.S4(), V3.S4(), 0)) +T(0x5ef23c04, CMGE(D4, D0, D18)) +T(0x4e203c6f, CMGE(V15.B16(), V3.B16(), V0.B16())) +T(0x7ee08822, CMGE(D2, D1, 0)) +T(0x2ea08bb9, CMGE(V25.S2(), V29.S2(), 0)) +T(0x5ef036a5, CMGT(D5, D21, D16)) +T(0x0eb7358b, CMGT(V11.S2(), V12.S2(), V23.S2())) +T(0x5ee08957, CMGT(D23, D10, 0)) +T(0x4ea088eb, CMGT(V11.S4(), V7.S4(), 0)) +T(0x7ee235f2, CMHI(D18, D15, D2)) +T(0x6e243596, CMHI(V22.B16(), V12.B16(), V4.B16())) +T(0x7ef23faf, CMHS(D15, D29, D18)) +T(0x2e2d3d8a, CMHS(V10.B8(), V12.B8(), V13.B8())) +T(0x7ee098a4, CMLE(D4, D5, 0)) +T(0x2e2098d3, CMLE(V19.B8(), V6.B8(), 0)) +T(0x5ee0a980, CMLT(D0, D12, 0)) +T(0x4e60a892, CMLT(V18.H8(), V4.H8(), 0)) +T(0x5ee18e03, CMTST(D3, D16, D1)) +T(0x4e708f65, CMTST(V5.H8(), V27.H8(), V16.H8())) +T(0x4e20598d, CNT(V13.B16(), V12.B16())) +// DUP +T(0x0e0d06cd, DUP(V13.B8(), V22.B()[6])) +T(0x0e010fe7, DUP(V7.B8(), WZR)) +T(0x2e2b1e6e, EOR(V14.B8(), V19.B8(), V11.B8())) +T(0x6e1c0a35, EXT(V21.B16(), V17.B16(), V28.B16(), 1)) +T(0x7ea0d7a4, FABD(S4, S29, S0)) +T(0x6eecd418, FABD(V24.D2(), V0.D2(), V12.D2())) +T(0x1e20c299, FABS(S25, S20)) +T(0x1e60c114, FABS(D20, D8)) +T(0x4ee0f999, FABS(V25.D2(), V12.D2())) +T(0x7e71ef5b, FACGE(D27, D26, D17)) +T(0x6e6eed17, FACGE(V23.D2(), V8.D2(), V14.D2())) +T(0x7ef8efc0, FACGT(D0, D30, D24)) +T(0x6eb0ec54, FACGT(V20.S4(), V2.S4(), V16.S4())) +T(0x1e242b23, FADD(S3, S25, S4)) +T(0x1e672a8b, FADD(D11, D20, D7)) +T(0x4e34d46b, FADD(V11.S4(), V3.S4(), V20.S4())) +T(0x7e30db16, FADDP(S22, V24.S2())) +T(0x6e21d626, FADDP(V6.S4(), V17.S4(), V1.S4())) +T(0x1e23c4ce, FCCMP(S6, S3, 14, GT)) +T(0x1e7104aa, FCCMP(D5, D17, 10, EQ)) +T(0x1e28c678, FCCMPE(S19, S8, 8, GT)) +T(0x1e6195dd, FCCMPE(D14, D1, 13, LS)) +T(0x5e31e659, FCMEQ(S25, S18, S17)) +T(0x0e27e7ba, FCMEQ(V26.S2(), V29.S2(), V7.S2())) +T(0x5ea0da1d, FCMEQ(S29, S16, 0.0)) +T(0x4ee0db8a, FCMEQ(V10.D2(), V28.D2(), 0.0)) +T(0x7e2de473, FCMGE(S19, S3, S13)) +T(0x2e33e726, FCMGE(V6.S2(), V25.S2(), V19.S2())) +T(0x7ea0c8d3, FCMGE(S19, S6, 0.0)) +T(0x6ea0ca7b, FCMGE(V27.S4(), V19.S4(), 0.0)) +T(0x7eb7e65d, FCMGT(S29, S18, S23)) +T(0x6ef0e6ac, FCMGT(V12.D2(), V21.D2(), V16.D2())) +T(0x5ee0cb5a, FCMGT(D26, D26, 0.0)) +T(0x4ea0c917, FCMGT(V23.S4(), V8.S4(), 0.0)) +T(0x7ea0dbe1, FCMLE(S1, S31, 0.0)) +T(0x6ea0da69, FCMLE(V9.S4(), V19.S4(), 0.0)) +T(0x5ea0ea5f, FCMLT(S31, S18, 0.0)) +T(0x4ee0e8de, FCMLT(V30.D2(), V6.D2(), 0.0)) +T(0x1e322040, FCMP(S2, S18)) +T(0x1e202248, FCMP(S18, 0.0)) +T(0x1e6520a0, FCMP(D5, D5)) +T(0x1e602108, FCMP(D8, 0.0)) +T(0x1e332370, FCMPE(S27, S19)) +T(0x1e202018, FCMPE(S0, 0.0)) +T(0x1e7120b0, FCMPE(D5, D17)) +T(0x1e602298, FCMPE(D20, 0.0)) +T(0x1e32ed68, FCSEL(S8, S11, S18, AL)) +T(0x1e7b1e21, FCSEL(D1, D17, D27, NE)) +T(0x1ee24022, FCVT(S2, H1)) +T(0x1ee2c33c, FCVT(D28, H25)) +T(0x1e23c379, FCVT(H25, S27)) +T(0x1e22c1a5, FCVT(D5, S13)) +T(0x1e63c2b1, FCVT(H17, D21)) +T(0x1e624309, FCVT(S9, D24)) +T(0x1e2400a0, FCVTAS(W0, S5)) +T(0x9e24000e, FCVTAS(X14, S0)) +T(0x1e640191, FCVTAS(W17, D12)) +T(0x9e6403d6, FCVTAS(X22, D30)) +T(0x5e21c8a7, FCVTAS(S7, S5)) +T(0x0e21c8df, FCVTAS(V31.S2(), V6.S2())) +T(0x1e25036b, FCVTAU(W11, S27)) +T(0x9e25030c, FCVTAU(X12, S24)) +T(0x1e65002e, FCVTAU(W14, D1)) +T(0x9e65003e, FCVTAU(X30, D1)) +T(0x7e61cabd, FCVTAU(D29, D21)) +T(0x2e21c880, FCVTAU(V0.S2(), V4.S2())) +T(0x4e217b66, FCVTL2(V6.S4(), V27.H8())) +T(0x1e30016d, FCVTMS(W13, S11)) +T(0x9e3002b5, FCVTMS(X21, S21)) +T(0x1e7003dd, FCVTMS(W29, D30)) +T(0x9e700080, FCVTMS(X0, D4)) +T(0x5e21b9b6, FCVTMS(S22, S13)) +T(0x4e61ba4e, FCVTMS(V14.D2(), V18.D2())) +T(0x1e31002d, FCVTMU(W13, S1)) +T(0x9e310281, FCVTMU(X1, S20)) +T(0x1e71000e, FCVTMU(W14, D0)) +T(0x9e710010, FCVTMU(X16, D0)) +T(0x7e61bb3b, FCVTMU(D27, D25)) +T(0x2e21b918, FCVTMU(V24.S2(), V8.S2())) +T(0x0e616a68, FCVTN(V8.S2(), V19.D2())) +T(0x1e200100, FCVTNS(W0, S8)) +T(0x9e20037f, FCVTNS(XZR, S27)) +T(0x1e60015e, FCVTNS(W30, D10)) +T(0x9e600018, FCVTNS(X24, D0)) +T(0x5e61a846, FCVTNS(D6, D2)) +T(0x4e21aa81, FCVTNS(V1.S4(), V20.S4())) +T(0x1e210248, FCVTNU(W8, S18)) +T(0x9e2103da, FCVTNU(X26, S30)) +T(0x1e610120, FCVTNU(W0, D9)) +T(0x9e61013a, FCVTNU(X26, D9)) +T(0x7e61aaba, FCVTNU(D26, D21)) +T(0x6e21aa16, FCVTNU(V22.S4(), V16.S4())) +T(0x1e28010d, FCVTPS(W13, S8)) +T(0x9e2803df, FCVTPS(XZR, S30)) +T(0x1e6802e9, FCVTPS(W9, D23)) +T(0x9e6801f7, FCVTPS(X23, D15)) +T(0x5ee1a986, FCVTPS(D6, D12)) +T(0x4ea1aa32, FCVTPS(V18.S4(), V17.S4())) +T(0x1e29022b, FCVTPU(W11, S17)) +T(0x9e290381, FCVTPU(X1, S28)) +T(0x1e690095, FCVTPU(W21, D4)) +T(0x9e6902b3, FCVTPU(X19, D21)) +T(0x7ea1abbb, FCVTPU(S27, S29)) +T(0x6ee1ab06, FCVTPU(V6.D2(), V24.D2())) +T(0x7e61687a, FCVTXN(S26, D3)) +T(0x2e61694c, FCVTXN(V12.S2(), V10.D2())) +T(0x1e18c4d6, FCVTZS(W22, S6, 15)) +T(0x9e18d131, FCVTZS(X17, S9, 12)) +T(0x1e58fd9b, FCVTZS(W27, D12, 1)) +T(0x9e5899ee, FCVTZS(X14, D15, 26)) +T(0x1e380091, FCVTZS(W17, S4)) +T(0x9e380289, FCVTZS(X9, S20)) +T(0x1e780117, FCVTZS(W23, D8)) +T(0x9e7800f5, FCVTZS(X21, D7)) +T(0x5f2fffdb, FCVTZS(S27, S30, 17)) +T(0x4f65ff65, FCVTZS(V5.D2(), V27.D2(), 27)) +T(0x5ee1b932, FCVTZS(D18, D9)) +T(0x4ee1ba41, FCVTZS(V1.D2(), V18.D2())) +T(0x1e19b5d8, FCVTZU(W24, S14, 19)) +T(0x9e199462, FCVTZU(X2, S3, 27)) +T(0x1e59fca1, FCVTZU(W1, D5, 1)) +T(0x9e599bbd, FCVTZU(X29, D29, 26)) +T(0x1e3900f6, FCVTZU(W22, S7)) +T(0x9e3900b7, FCVTZU(X23, S5)) +T(0x1e79031a, FCVTZU(W26, D24)) +T(0x9e790248, FCVTZU(X8, D18)) +T(0x7f5afd37, FCVTZU(D23, D9, 38)) +T(0x2f34fd38, FCVTZU(V24.S2(), V9.S2(), 12)) +T(0x7ea1baa3, FCVTZU(S3, S21)) +T(0x6ee1b8c1, FCVTZU(V1.D2(), V6.D2())) +T(0x1e3d1999, FDIV(S25, S12, S29)) +T(0x1e7e1a4e, FDIV(D14, D18, D30)) +T(0x2e2cfe45, FDIV(V5.S2(), V18.S2(), V12.S2())) +T(0x1f114362, FMADD(S2, S27, S17, S16)) +T(0x1f482240, FMADD(D0, D18, D8, D8)) +T(0x1e234b5f, FMAX(S31, S26, S3)) +T(0x1e694894, FMAX(D20, D4, D9)) +T(0x4e29f568, FMAX(V8.S4(), V11.S4(), V9.S4())) +T(0x1e2f6a40, FMAXNM(S0, S18, S15)) +T(0x1e6d6a99, FMAXNM(D25, D20, D13)) +T(0x4e2dc6da, FMAXNM(V26.S4(), V22.S4(), V13.S4())) +T(0x7e30c9b9, FMAXNMP(S25, V13.S2())) +T(0x6e36c794, FMAXNMP(V20.S4(), V28.S4(), V22.S4())) +T(0x6e30c8f6, FMAXNMV(S22, V7.S4())) +T(0x7e30f8dd, FMAXP(S29, V6.S2())) +T(0x6e61f4ab, FMAXP(V11.D2(), V5.D2(), V1.D2())) +T(0x6e30fb85, FMAXV(S5, V28.S4())) +T(0x1e3c5aae, FMIN(S14, S21, S28)) +T(0x1e7f58f8, FMIN(D24, D7, D31)) +T(0x0eb0f63b, FMIN(V27.S2(), V17.S2(), V16.S2())) +T(0x1e317886, FMINNM(S6, S4, S17)) +T(0x1e6e7a5d, FMINNM(D29, D18, D14)) +T(0x4ea4c44c, FMINNM(V12.S4(), V2.S4(), V4.S4())) +T(0x7ef0c895, FMINNMP(D21, V4.D2())) +T(0x6efbc4e3, FMINNMP(V3.D2(), V7.D2(), V27.D2())) +T(0x6eb0c93d, FMINNMV(S29, V9.S4())) +T(0x7ef0fa13, FMINP(D19, V16.D2())) +T(0x2eb4f4ac, FMINP(V12.S2(), V5.S2(), V20.S2())) +T(0x6eb0f801, FMINV(S1, V0.S4())) +T(0x5f8219a6, FMLA(S6, S13, V2.S()[2])) +T(0x4fc512a1, FMLA(V1.D2(), V21.D2(), V5.D()[0])) +T(0x4e6bcecf, FMLA(V15.D2(), V22.D2(), V11.D2())) +T(0x5f8a5094, FMLS(S20, S4, V10.S()[0])) +T(0x4fd85b79, FMLS(V25.D2(), V27.D2(), V24.D()[1])) +T(0x0ebacca4, FMLS(V4.S2(), V5.S2(), V26.S2())) +T(0x1e270027, FMOV(S7, W1)) +T(0x1e260164, FMOV(W4, S11)) +T(0x9e670008, FMOV(D8, X0)) +T(0x9eaf03e0, FMOV(V0.D()[1], XZR)) +T(0x9e660090, FMOV(X16, D4)) +T(0x9eae025f, FMOV(XZR, V18.D()[1])) +T(0x1e204079, FMOV(S25, S3)) +T(0x1e6042f8, FMOV(D24, D23)) +T(0x1e32f01c, FMOV(S28, FImm8{true, 0b001, 0b0111})) // -5.75 +T(0x1e74901e, FMOV(D30, FImm8{true, 0b010, 0b0100})) // -10.0 +T(0x0f03f51a, FMOV(V26.S2(), FImm8{false, 0b110, 0b1000})) // 0.75 +T(0x6f02f58e, FMOV(V14.D2(), FImm8{false, 0b100, 0b1100})) // 0.21875 +T(0x1f0adaf5, FMSUB(S21, S23, S10, S22)) +T(0x1f5da840, FMSUB(D0, D2, D29, D10)) +T(0x5fa39bba, FMUL(S26, S29, V3.S()[3])) +T(0x4fb89ad2, FMUL(V18.S4(), V22.S4(), V24.S()[3])) +T(0x1e2b0a3c, FMUL(S28, S17, S11)) +T(0x1e720933, FMUL(D19, D9, D18)) +T(0x6e7edfa3, FMUL(V3.D2(), V29.D2(), V30.D2())) +T(0x5e32dee6, FMULX(S6, S23, S18)) +T(0x0e27deec, FMULX(V12.S2(), V23.S2(), V7.S2())) +T(0x7f879a1f, FMULX(S31, S16, V7.S()[2])) +T(0x6fce9836, FMULX(V22.D2(), V1.D2(), V14.D()[1])) +T(0x1e2142cc, FNEG(S12, S22)) +T(0x1e61434b, FNEG(D11, D26)) +T(0x6ea0fb90, FNEG(V16.S4(), V28.S4())) +T(0x1f361be5, FNMADD(S5, S31, S22, S6)) +T(0x1f7a316d, FNMADD(D13, D11, D26, D12)) +T(0x1f3e9957, FNMSUB(S23, S10, S30, S6)) +T(0x1f79da66, FNMSUB(D6, D19, D25, D22)) +T(0x1e208ab5, FNMUL(S21, S21, S0)) +T(0x1e6f89eb, FNMUL(D11, D15, D15)) +T(0x5ea1da18, FRECPE(S24, S16)) +T(0x0ea1d9df, FRECPE(V31.S2(), V14.S2())) +T(0x5e2dfe37, FRECPS(S23, S17, S13)) +T(0x0e29fcec, FRECPS(V12.S2(), V7.S2(), V9.S2())) +T(0x5ee1f998, FRECPX(D24, D12)) +T(0x1e264106, FRINTA(S6, S8)) +T(0x1e664376, FRINTA(D22, D27)) +T(0x6e6188a9, FRINTA(V9.D2(), V5.D2())) +T(0x1e27c216, FRINTI(S22, S16)) +T(0x1e67c071, FRINTI(D17, D3)) +T(0x6ea19b9d, FRINTI(V29.S4(), V28.S4())) +T(0x1e25413e, FRINTM(S30, S9)) +T(0x1e6541a1, FRINTM(D1, D13)) +T(0x4e619ad8, FRINTM(V24.D2(), V22.D2())) +T(0x1e244098, FRINTN(S24, S4)) +T(0x1e6440b4, FRINTN(D20, D5)) +T(0x4e618835, FRINTN(V21.D2(), V1.D2())) +T(0x1e24c188, FRINTP(S8, S12)) +T(0x1e64c292, FRINTP(D18, D20)) +T(0x0ea18a69, FRINTP(V9.S2(), V19.S2())) +T(0x1e274146, FRINTX(S6, S10)) +T(0x1e674333, FRINTX(D19, D25)) +T(0x6e619902, FRINTX(V2.D2(), V8.D2())) +T(0x1e25c2b2, FRINTZ(S18, S21)) +T(0x1e65c008, FRINTZ(D8, D0)) +T(0x0ea19918, FRINTZ(V24.S2(), V8.S2())) +T(0x7ea1dbdb, FRSQRTE(S27, S30)) +T(0x6ee1d8df, FRSQRTE(V31.D2(), V6.D2())) +T(0x5ee0ff40, FRSQRTS(D0, D26, D0)) +T(0x4eb6fe31, FRSQRTS(V17.S4(), V17.S4(), V22.S4())) +T(0x1e21c204, FSQRT(S4, S16)) +T(0x1e61c31c, FSQRT(D28, D24)) +T(0x6ea1fa1f, FSQRT(V31.S4(), V16.S4())) +T(0x1e273b28, FSUB(S8, S25, S7)) +T(0x1e6139b9, FSUB(D25, D13, D1)) +T(0x0eadd6b0, FSUB(V16.S2(), V21.S2(), V13.S2())) +// INS +// INS +T(0x0c407b24, LD1(List{V4.S2()}, X25)) +T(0x4c40a891, LD1(List{V17.S4(), V18.S4()}, X4)) +T(0x0c406d31, LD1(List{V17.D1(), V18.D1(), V19.D1()}, X9)) +T(0x4c402b00, LD1(List{V0.S4(), V1.S4(), V2.S4(), V3.S4()}, X24)) +T(0x4cdf72c8, LD1(List{V8.B16()}, X22, POST_INDEXED, 16)) +T(0x0cd67504, LD1(List{V4.H4()}, X8, POST_INDEXED, X22)) +T(0x0cdfaeb7, LD1(List{V23.D1(), V24.D1()}, X21, POST_INDEXED, 16)) +T(0x0cd0a837, LD1(List{V23.S2(), V24.S2()}, X1, POST_INDEXED, X16)) +T(0x4cdf6d36, LD1(List{V22.D2(), V23.D2(), V24.D2()}, X9, POST_INDEXED, 48)) +T(0x0cdc685b, LD1(List{V27.S2(), V28.S2(), V29.S2()}, X2, POST_INDEXED, X28)) +T(0x0cdf2ebc, LD1(List{V28.D1(), V29.D1(), V30.D1(), V31.D1()}, X21, POST_INDEXED, 32)) +T(0x0cc0260c, LD1(List{V12.H4(), V13.H4(), V14.H4(), V15.H4()}, X16, POST_INDEXED, X0)) +T(0x0d400665, LD1(List{V5.B()}[1], X19)) +T(0x0d4041da, LD1(List{V26.H()}[0], X14)) +T(0x0d40815b, LD1(List{V27.S()}[0], X10)) +T(0x0d408755, LD1(List{V21.D()}[0], X26)) +T(0x4ddf0966, LD1(List{V6.B()}[10], X11, POST_INDEXED, 1)) +T(0x4dcc1951, LD1(List{V17.B()}[14], X10, POST_INDEXED, X12)) +T(0x0ddf58cf, LD1(List{V15.H()}[3], X6, POST_INDEXED, 2)) +T(0x0dd14a3d, LD1(List{V29.H()}[1], X17, POST_INDEXED, X17)) +T(0x0ddf8072, LD1(List{V18.S()}[0], X3, POST_INDEXED, 4)) +T(0x4dcb90bb, LD1(List{V27.S()}[3], X5, POST_INDEXED, X11)) +T(0x4ddf8537, LD1(List{V23.D()}[1], X9, POST_INDEXED, 8)) +T(0x0dcf8784, LD1(List{V4.D()}[0], X28, POST_INDEXED, X15)) +T(0x0d40c0f1, LD1R(List{V17.B8()}, X7)) +T(0x0ddfceac, LD1R(List{V12.D1()}, X21, POST_INDEXED, 8)) +T(0x4dd5c9c2, LD1R(List{V2.S4()}, X14, POST_INDEXED, X21)) +T(0x0c408bc8, LD2(List{V8.S2(), V9.S2()}, X30)) +T(0x0cdf842a, LD2(List{V10.H4(), V11.H4()}, X1, POST_INDEXED, 16)) +T(0x0cd58678, LD2(List{V24.H4(), V25.H4()}, X19, POST_INDEXED, X21)) +T(0x0d60132f, LD2(List{V15.B(), V16.B()}[4], X25)) +T(0x4d605156, LD2(List{V22.H(), V23.H()}[6], X10)) +T(0x0d609293, LD2(List{V19.S(), V20.S()}[1], X20)) +T(0x4d608599, LD2(List{V25.D(), V26.D()}[1], X12)) +T(0x4dff0bd6, LD2(List{V22.B(), V23.B()}[10], X30, POST_INDEXED, 2)) +T(0x0df90bab, LD2(List{V11.B(), V12.B()}[2], X29, POST_INDEXED, X25)) +T(0x4dff42c3, LD2(List{V3.H(), V4.H()}[4], X22, POST_INDEXED, 4)) +T(0x4dfa5816, LD2(List{V22.H(), V23.H()}[7], X0, POST_INDEXED, X26)) +T(0x4dff9372, LD2(List{V18.S(), V19.S()}[3], X27, POST_INDEXED, 8)) +T(0x4de483c0, LD2(List{V0.S(), V1.S()}[2], X30, POST_INDEXED, X4)) +T(0x4dff8714, LD2(List{V20.D(), V21.D()}[1], X24, POST_INDEXED, 16)) +T(0x4dfa854d, LD2(List{V13.D(), V14.D()}[1], X10, POST_INDEXED, X26)) +T(0x4d60ca33, LD2R(List{V19.S4(), V20.S4()}, X17)) +T(0x0dffc777, LD2R(List{V23.H4(), V24.H4()}, X27, POST_INDEXED, 4)) +T(0x4de9c3cd, LD2R(List{V13.B16(), V14.B16()}, X30, POST_INDEXED, X9)) +T(0x0c404032, LD3(List{V18.B8(), V19.B8(), V20.B8()}, X1)) +T(0x0cdf4bc8, LD3(List{V8.S2(), V9.S2(), V10.S2()}, X30, POST_INDEXED, 24)) +T(0x4ccb4960, LD3(List{V0.S4(), V1.S4(), V2.S4()}, X11, POST_INDEXED, X11)) +T(0x0d40217c, LD3(List{V28.B(), V29.B(), V30.B()}[0], X11)) +T(0x4d407a38, LD3(List{V24.H(), V25.H(), V26.H()}[7], X17)) +T(0x4d40a119, LD3(List{V25.S(), V26.S(), V27.S()}[2], X8)) +T(0x0d40a6bb, LD3(List{V27.D(), V28.D(), V29.D()}[0], X21)) +T(0x4ddf2bb1, LD3(List{V17.B(), V18.B(), V19.B()}[10], X29, POST_INDEXED, 3)) +T(0x4dc13519, LD3(List{V25.B(), V26.B(), V27.B()}[13], X8, POST_INDEXED, X1)) +T(0x4ddf6b3f, LD3(List{V31.H(), V0.H(), V1.H()}[5], X25, POST_INDEXED, 6)) +T(0x4dc16243, LD3(List{V3.H(), V4.H(), V5.H()}[4], X18, POST_INDEXED, X1)) +T(0x4ddfa329, LD3(List{V9.S(), V10.S(), V11.S()}[2], X25, POST_INDEXED, 12)) +T(0x4ddab328, LD3(List{V8.S(), V9.S(), V10.S()}[3], X25, POST_INDEXED, X26)) +T(0x4ddfa4e4, LD3(List{V4.D(), V5.D(), V6.D()}[1], X7, POST_INDEXED, 24)) +T(0x0ddba58c, LD3(List{V12.D(), V13.D(), V14.D()}[0], X12, POST_INDEXED, X27)) +T(0x0d40e3b3, LD3R(List{V19.B8(), V20.B8(), V21.B8()}, X29)) +T(0x0ddfe2f3, LD3R(List{V19.B8(), V20.B8(), V21.B8()}, X23, POST_INDEXED, 3)) +T(0x0ddbe8e4, LD3R(List{V4.S2(), V5.S2(), V6.S2()}, X7, POST_INDEXED, X27)) +T(0x4c400a69, LD4(List{V9.S4(), V10.S4(), V11.S4(), V12.S4()}, X19)) +T(0x0cdf0bea, LD4(List{V10.S2(), V11.S2(), V12.S2(), V13.S2()}, SP, POST_INDEXED, 32)) +T(0x4cd705ad, LD4(List{V13.H8(), V14.H8(), V15.H8(), V16.H8()}, X13, POST_INDEXED, X23)) +T(0x0d603b97, LD4(List{V23.B(), V24.B(), V25.B(), V26.B()}[6], X28)) +T(0x0d606941, LD4(List{V1.H(), V2.H(), V3.H(), V4.H()}[1], X10)) +T(0x0d60a039, LD4(List{V25.S(), V26.S(), V27.S(), V28.S()}[0], X1)) +T(0x4d60a4c5, LD4(List{V5.D(), V6.D(), V7.D(), V8.D()}[1], X6)) +T(0x0dff2139, LD4(List{V25.B(), V26.B(), V27.B(), V28.B()}[0], X9, POST_INDEXED, 4)) +T(0x4df32513, LD4(List{V19.B(), V20.B(), V21.B(), V22.B()}[9], X8, POST_INDEXED, X19)) +T(0x0dff7b45, LD4(List{V5.H(), V6.H(), V7.H(), V8.H()}[3], X26, POST_INDEXED, 8)) +T(0x0dfa6839, LD4(List{V25.H(), V26.H(), V27.H(), V28.H()}[1], X1, POST_INDEXED, X26)) +T(0x4dffa176, LD4(List{V22.S(), V23.S(), V24.S(), V25.S()}[2], X11, POST_INDEXED, 16)) +T(0x4de0a125, LD4(List{V5.S(), V6.S(), V7.S(), V8.S()}[2], X9, POST_INDEXED, X0)) +T(0x0dffa4ab, LD4(List{V11.D(), V12.D(), V13.D(), V14.D()}[0], X5, POST_INDEXED, 32)) +T(0x0dfba784, LD4(List{V4.D(), V5.D(), V6.D(), V7.D()}[0], X28, POST_INDEXED, X27)) +T(0x4d60ef82, LD4R(List{V2.D2(), V3.D2(), V4.D2(), V5.D2()}, X28)) +T(0x0dffef23, LD4R(List{V3.D1(), V4.D1(), V5.D1(), V6.D1()}, X25, POST_INDEXED, 32)) +T(0x4df5e36a, LD4R(List{V10.B16(), V11.B16(), V12.B16(), V13.B16()}, X27, POST_INDEXED, X21)) +T(0x2c6dde58, LDNP(S24, S23, X18, -148)) +T(0x6c5f8ad5, LDNP(D21, D2, X22, 504)) +T(0xac793251, LDNP(Q17, Q12, X18, -224)) +T(0x2cf1b345, LDP(S5, S12, X26, POST_INDEXED, -116)) +T(0x6cc9489a, LDP(D26, D18, X4, POST_INDEXED, 144)) +T(0xace34b69, LDP(Q9, Q18, X27, POST_INDEXED, -928)) +T(0x2dca159f, LDP(S31, S5, X12, PRE_INDEXED, 80)) +T(0x6df9682d, LDP(D13, D26, X1, PRE_INDEXED, -112)) +T(0xadc7566f, LDP(Q15, Q21, X19, PRE_INDEXED, 224)) +T(0x2d4efb01, LDP(S1, S30, X24, 116)) +T(0x6d710b5a, LDP(D26, D2, X26, -240)) +T(0xad74fbb0, LDP(Q16, Q30, X29, -368)) +T(0x3c5b76a9, LDR(B9, X21, POST_INDEXED, -73)) +T(0x7c5fd798, LDR(H24, X28, POST_INDEXED, -3)) +T(0xbc4336b6, LDR(S22, X21, POST_INDEXED, 51)) +T(0xfc53b4d5, LDR(D21, X6, POST_INDEXED, -197)) +T(0x3cdf571d, LDR(Q29, X24, POST_INDEXED, -11)) +T(0x3c5baf77, LDR(B23, X27, PRE_INDEXED, -70)) +T(0x7c41bc79, LDR(H25, X3, PRE_INDEXED, 27)) +T(0xbc48ecb2, LDR(S18, X5, PRE_INDEXED, 142)) +T(0xfc4b1dee, LDR(D14, X15, PRE_INDEXED, 177)) +T(0x3cc31c6a, LDR(Q10, X3, PRE_INDEXED, 49)) +T(0x3d5a0ef6, LDR(B22, X23, 1667)) +T(0x7d5d8dd7, LDR(H23, X14, 3782)) +T(0xbd55d41a, LDR(S26, X0, 5588)) +T(0xfd58c566, LDR(D6, X11, 12680)) +T(0x3dce966e, LDR(Q14, X19, 14928)) +T(0x1c8599c0, LDR(S0, -1002696)) +T(0x5c8a1ca4, LDR(D4, -965740)) +T(0x9cfd90fa, LDR(Q26, -19940)) +T(0x3c634a12, LDR(B18, X16, W3, UXTW)) +T(0x3c7368e7, LDR(B7, X7, X19, LSL, 0)) +T(0x7c646a38, LDR(H24, X17, X4)) +T(0xbc727bda, LDR(S26, X30, X18, LSL, 2)) +T(0xfc63eb36, LDR(D22, X25, X3, SXTX)) +T(0x3ce2ca06, LDR(Q6, X16, W2, SXTW)) +T(0x3c4233e6, LDUR(B6, SP, 35)) +T(0x7c4d52f1, LDUR(H17, X23, 213)) +T(0xbc5be12f, LDUR(S15, X9, -66)) +T(0xfc474197, LDUR(D23, X12, 116)) +T(0x3cd703db, LDUR(Q27, X30, -144)) +T(0x2f9a0354, MLA(V20.S2(), V26.S2(), V26.S()[0])) +T(0x4e7e9643, MLA(V3.H8(), V18.H8(), V30.H8())) +T(0x2f80484e, MLS(V14.S2(), V2.S2(), V0.S()[2])) +T(0x6ebb9572, MLS(V18.S4(), V11.S4(), V27.S4())) +T(0x6e135ec1, MOV(V1.B()[9], V22.B()[11])) +T(0x4e0f1da9, MOV(V9.B()[7], W13)) +T(0x5e0e045d, MOV(H29, V2.H()[3])) +T(0x0e043ca1, MOV(W1, V5.S()[0])) +T(0x4e083df7, MOV(X23, V15.D()[0])) +// MOV +T(0x0f06e58e, MOVI(V14.B8(), 204)) +T(0x4f058559, MOVI(V25.H8(), 170)) +T(0x0f030565, MOVI(V5.S2(), 107)) +T(0x0f05c4dc, MOVI(V28.S2(), 166, MSL, 8)) +T(0x2f07e47e, MOVI(D30, RepImm{0b11100011})) // +T(0x6f03e65b, MOVI(V27.D2(), RepImm{0b01110010})) // +T(0x0f9e813e, MUL(V30.S2(), V9.S2(), V30.S()[0])) +T(0x4ea59f8e, MUL(V14.S4(), V28.S4(), V5.S4())) +T(0x2e205acd, MVN(V13.B8(), V22.B8())) +T(0x2f0084e1, MVNI(V1.H4(), 7)) +T(0x6f026602, MVNI(V2.S4(), 80, LSL, 24)) +T(0x2f03c71a, MVNI(V26.S2(), 120, MSL, 8)) +T(0x7ee0ba9e, NEG(D30, D20)) +T(0x2ea0b9f7, NEG(V23.S2(), V15.S2())) +// NOT +T(0x4ef81f0f, ORN(V15.B16(), V24.B16(), V24.B16())) +T(0x4f03b4e0, ORR(V0.H8(), 103, LSL, 8)) +T(0x4f043508, ORR(V8.S4(), 136, LSL, 8)) +T(0x4eb21c9c, ORR(V28.B16(), V4.B16(), V18.B16())) +T(0x2e279d77, PMUL(V23.B8(), V11.B8(), V7.B8())) +T(0x4e27e299, PMULL2(V25.H8(), V20.B16(), V7.B16())) +T(0x2eab4048, RADDHN(V8.S2(), V2.D2(), V11.D2())) +T(0x6e605b7e, RBIT(V30.B16(), V27.B16())) +T(0x0e201b37, REV16(V23.B8(), V25.B8())) +T(0x6e60098a, REV32(V10.H8(), V12.H8())) +T(0x0e2009de, REV64(V30.B8(), V14.B8())) +T(0x4f218e4e, RSHRN2(V14.S4(), V18.D2(), 31)) +T(0x6e7460f2, RSUBHN2(V18.H8(), V7.S4(), V20.S4())) +T(0x0e377f74, SABA(V20.B8(), V27.B8(), V23.B8())) +T(0x4ea851f6, SABAL2(V22.D2(), V15.S4(), V8.S4())) +T(0x0e777752, SABD(V18.H4(), V26.H4(), V23.H4())) +T(0x0eba7005, SABDL(V5.D2(), V0.S2(), V26.S2())) +T(0x4e2069c4, SADALP(V4.H8(), V14.B16())) +T(0x4e270017, SADDL2(V23.H8(), V0.B16(), V7.B16())) +T(0x0ea028ca, SADDLP(V10.D1(), V6.S2())) +T(0x4e703b2a, SADDLV(S10, V25.H8())) +T(0x0e6311d2, SADDW(V18.S4(), V14.S4(), V3.H4())) +T(0x1e02c782, SCVTF(S2, W28, 15)) +T(0x1e42d0e2, SCVTF(D2, W7, 12)) +T(0x9e02e80e, SCVTF(S14, X0, 6)) +T(0x9e423dda, SCVTF(D26, X14, 49)) +T(0x1e2202f3, SCVTF(S19, W23)) +T(0x1e6201e7, SCVTF(D7, W15)) +T(0x9e22016c, SCVTF(S12, X11)) +T(0x9e620316, SCVTF(D22, X24)) +T(0x5f34e509, SCVTF(S9, S8, 12)) +T(0x4f5ae716, SCVTF(V22.D2(), V24.D2(), 38)) +T(0x5e61d946, SCVTF(D6, D10)) +T(0x4e61d86b, SCVTF(V11.D2(), V3.D2())) +// SHA1C +// SHA1H +// SHA1M +// SHA1P +// SHA1SU0 +// SHA1SU1 +// SHA256H +// SHA256H2 +// SHA256SU0 +// SHA256SU1 +T(0x4eb90506, SHADD(V6.S4(), V8.S4(), V25.S4())) +T(0x5f4d5767, SHL(D7, D27, 13)) +T(0x4f1f542f, SHL(V15.H8(), V1.H8(), 15)) +T(0x2ea13a71, SHLL(V17.D2(), V19.S2(), 32)) +T(0x4f0885fd, SHRN2(V29.B16(), V15.H8(), 8)) +T(0x0eb42794, SHSUB(V20.S2(), V28.S2(), V20.S2())) +T(0x7f5f54ad, SLI(D13, D5, 31)) +T(0x6f09554e, SLI(V14.B16(), V10.B16(), 1)) +T(0x0e316452, SMAX(V18.B8(), V2.B8(), V17.B8())) +T(0x4e66a478, SMAXP(V24.H8(), V3.H8(), V6.H8())) +T(0x0e30a9e6, SMAXV(B6, V15.B8())) +T(0x4e276e2a, SMIN(V10.B16(), V17.B16(), V7.B16())) +T(0x4e29ad73, SMINP(V19.B16(), V11.B16(), V9.B16())) +T(0x0e71aac5, SMINV(H5, V22.H4())) +T(0x4f9f2b00, SMLAL2(V0.D2(), V24.S4(), V31.S()[2])) +T(0x4e788037, SMLAL2(V23.S4(), V1.H8(), V24.H8())) +T(0x4f7362b9, SMLSL2(V25.S4(), V21.H8(), V3.H()[3])) +T(0x0e31a0d5, SMLSL(V21.H8(), V6.B8(), V17.B8())) +T(0x0e162fc3, SMOV(W3, V30.H()[5])) +T(0x4e0a2cf2, SMOV(X18, V7.H()[2])) +T(0x0f6ba85c, SMULL(V28.S4(), V2.H4(), V11.H()[6])) +T(0x4e61c2a1, SMULL2(V1.S4(), V21.H8(), V1.H8())) +T(0x5e20794c, SQABS(B12, B10)) +T(0x4e607b9b, SQABS(V27.H8(), V28.H8())) +T(0x5eb50df4, SQADD(S20, S15, S21)) +T(0x0e370ff4, SQADD(V20.B8(), V31.B8(), V23.B8())) +T(0x5fab3a4e, SQDMLAL(D14, S18, V11.S()[3])) +T(0x4f5b3805, SQDMLAL2(V5.S4(), V0.H8(), V11.H()[5])) +T(0x5e7f90ed, SQDMLAL(S13, H7, H31)) +T(0x0ea992b2, SQDMLAL(V18.D2(), V21.S2(), V9.S2())) +T(0x5f867ba2, SQDMLSL(D2, S29, V6.S()[2])) +T(0x4f997118, SQDMLSL2(V24.D2(), V8.S4(), V25.S()[0])) +T(0x5e62b0b2, SQDMLSL(S18, H5, H2)) +T(0x0e74b089, SQDMLSL(V9.S4(), V4.H4(), V20.H4())) +T(0x5f5acb3c, SQDMULH(H28, H25, V10.H()[5])) +T(0x4f7bc13d, SQDMULH(V29.H8(), V9.H8(), V11.H()[3])) +T(0x5e6ab724, SQDMULH(H4, H25, H10)) +T(0x4ea6b543, SQDMULH(V3.S4(), V10.S4(), V6.S4())) +T(0x5f89b899, SQDMULL(D25, S4, V9.S()[2])) +T(0x0f53b2ee, SQDMULL(V14.S4(), V23.H4(), V3.H()[1])) +T(0x5e60d01a, SQDMULL(S26, H0, H0)) +T(0x0eb4d146, SQDMULL(V6.D2(), V10.S2(), V20.S2())) +T(0x7ee07b81, SQNEG(D1, D28)) +T(0x2e607a04, SQNEG(V4.H4(), V16.H4())) +T(0x5f47dac8, SQRDMULH(H8, H22, V7.H()[4])) +T(0x0f45db93, SQRDMULH(V19.H4(), V28.H4(), V5.H()[4])) +T(0x7ea3b621, SQRDMULH(S1, S17, S3)) +T(0x6ea2b672, SQRDMULH(V18.S4(), V19.S4(), V2.S4())) +T(0x5e7c5ee7, SQRSHL(H7, H23, H28)) +T(0x4e655e4b, SQRSHL(V11.H8(), V18.H8(), V5.H8())) +T(0x5f0c9c10, SQRSHRN(B16, H0, 4)) +T(0x4f309e99, SQRSHRN2(V25.S4(), V20.D2(), 16)) +T(0x7f1f8de7, SQRSHRUN(H7, S15, 1)) +T(0x6f178f67, SQRSHRUN2(V7.H8(), V27.S4(), 9)) +T(0x5f7977b8, SQSHL(D24, D29, 57)) +T(0x4f1e75f3, SQSHL(V19.H8(), V15.H8(), 14)) +T(0x5eb24f5d, SQSHL(S29, S26, S18)) +T(0x4e7c4c93, SQSHL(V19.H8(), V4.H8(), V28.H8())) +T(0x7f2e66a1, SQSHLU(S1, S21, 14)) +T(0x6f4c65a2, SQSHLU(V2.D2(), V13.D2(), 12)) +T(0x5f3f950b, SQSHRN(S11, D8, 1)) +T(0x4f329646, SQSHRN2(V6.S4(), V18.D2(), 14)) +T(0x7f188469, SQSHRUN(H9, S3, 8)) +T(0x6f328478, SQSHRUN2(V24.S4(), V3.D2(), 14)) +T(0x5e362dae, SQSUB(B14, B13, B22)) +T(0x0e3c2c86, SQSUB(V6.B8(), V4.B8(), V28.B8())) +T(0x5ea149fc, SQXTN(S28, D15)) +T(0x4e214b24, SQXTN2(V4.B16(), V25.H8())) +T(0x7e61290e, SQXTUN(H14, S8)) +T(0x6ea12b96, SQXTUN2(V22.S4(), V28.D2())) +T(0x4eae1673, SRHADD(V19.S4(), V19.S4(), V14.S4())) +T(0x7f794647, SRI(D7, D18, 7)) +T(0x6f654787, SRI(V7.D2(), V28.D2(), 27)) +T(0x5ee0549e, SRSHL(D30, D4, D0)) +T(0x4eba55d2, SRSHL(V18.S4(), V14.S4(), V26.S4())) +T(0x5f712744, SRSHR(D4, D26, 15)) +T(0x4f2025f5, SRSHR(V21.S4(), V15.S4(), 32)) +T(0x5f7734a9, SRSRA(D9, D5, 9)) +T(0x0f3a371a, SRSRA(V26.S2(), V24.S2(), 6)) +T(0x5eed44ee, SSHL(D14, D7, D13)) +T(0x0e704683, SSHL(V3.H4(), V20.H4(), V16.H4())) +T(0x4f2aa7c3, SSHLL2(V3.D2(), V30.S4(), 10)) +T(0x5f5e058d, SSHR(D13, D12, 34)) +T(0x4f730496, SSHR(V22.D2(), V4.D2(), 13)) +T(0x5f5e152a, SSRA(D10, D9, 34)) +T(0x0f21172b, SSRA(V11.S2(), V25.S2(), 31)) +T(0x4e24220f, SSUBL2(V15.H8(), V16.B16(), V4.B16())) +T(0x4e3f32a2, SSUBW2(V2.H8(), V21.H8(), V31.B16())) +T(0x0c007a62, ST1(List{V2.S2()}, X19)) +T(0x4c00adb7, ST1(List{V23.D2(), V24.D2()}, X13)) +T(0x0c006b92, ST1(List{V18.S2(), V19.S2(), V20.S2()}, X28)) +T(0x4c0029b8, ST1(List{V24.S4(), V25.S4(), V26.S4(), V27.S4()}, X13)) +T(0x0c9f7f60, ST1(List{V0.D1()}, X27, POST_INDEXED, 8)) +T(0x0c9f7ebc, ST1(List{V28.D1()}, X21, POST_INDEXED, 8)) +T(0x0c9faf06, ST1(List{V6.D1(), V7.D1()}, X24, POST_INDEXED, 16)) +T(0x4c93aff5, ST1(List{V21.D2(), V22.D2()}, SP, POST_INDEXED, X19)) +T(0x4c9f6398, ST1(List{V24.B16(), V25.B16(), V26.B16()}, X28, POST_INDEXED, 48)) +T(0x4c8162ff, ST1(List{V31.B16(), V0.B16(), V1.B16()}, X23, POST_INDEXED, X1)) +T(0x0c9f23ee, ST1(List{V14.B8(), V15.B8(), V16.B8(), V17.B8()}, SP, POST_INDEXED, 32)) +T(0x4c862148, ST1(List{V8.B16(), V9.B16(), V10.B16(), V11.B16()}, X10, POST_INDEXED, X6)) +T(0x0d001c7a, ST1(List{V26.B()}[7], X3)) +T(0x0d005b54, ST1(List{V20.H()}[3], X26)) +T(0x4d009392, ST1(List{V18.S()}[3], X28)) +T(0x4d008509, ST1(List{V9.D()}[1], X8)) +T(0x4d9f1246, ST1(List{V6.B()}[12], X18, POST_INDEXED, 1)) +T(0x0d8c17f5, ST1(List{V21.B()}[5], SP, POST_INDEXED, X12)) +T(0x4d9f53ee, ST1(List{V14.H()}[6], SP, POST_INDEXED, 2)) +T(0x0d8f48c4, ST1(List{V4.H()}[1], X6, POST_INDEXED, X15)) +T(0x4d9f8185, ST1(List{V5.S()}[2], X12, POST_INDEXED, 4)) +T(0x0d8c92bc, ST1(List{V28.S()}[1], X21, POST_INDEXED, X12)) +T(0x4d9f86b3, ST1(List{V19.D()}[1], X21, POST_INDEXED, 8)) +T(0x4d9c8442, ST1(List{V2.D()}[1], X2, POST_INDEXED, X28)) +T(0x4c008a69, ST2(List{V9.S4(), V10.S4()}, X19)) +T(0x4c9f8930, ST2(List{V16.S4(), V17.S4()}, X9, POST_INDEXED, 32)) +T(0x0c9a8993, ST2(List{V19.S2(), V20.S2()}, X12, POST_INDEXED, X26)) +T(0x0d2001ac, ST2(List{V12.B(), V13.B()}[0], X13)) +T(0x4d20495c, ST2(List{V28.H(), V29.H()}[5], X10)) +T(0x4d2093e4, ST2(List{V4.S(), V5.S()}[3], SP)) +T(0x4d208482, ST2(List{V2.D(), V3.D()}[1], X4)) +T(0x4dbf0e40, ST2(List{V0.B(), V1.B()}[11], X18, POST_INDEXED, 2)) +T(0x0db8085f, ST2(List{V31.B(), V0.B()}[2], X2, POST_INDEXED, X24)) +T(0x0dbf4a2d, ST2(List{V13.H(), V14.H()}[1], X17, POST_INDEXED, 4)) +T(0x4db1417e, ST2(List{V30.H(), V31.H()}[4], X11, POST_INDEXED, X17)) +T(0x0dbf81af, ST2(List{V15.S(), V16.S()}[0], X13, POST_INDEXED, 8)) +T(0x0dbf831c, ST2(List{V28.S(), V29.S()}[0], X24, POST_INDEXED, 8)) +T(0x0dbf846a, ST2(List{V10.D(), V11.D()}[0], X3, POST_INDEXED, 16)) +T(0x0dab85dc, ST2(List{V28.D(), V29.D()}[0], X14, POST_INDEXED, X11)) +T(0x0c004a09, ST3(List{V9.S2(), V10.S2(), V11.S2()}, X16)) +T(0x4c9f4768, ST3(List{V8.H8(), V9.H8(), V10.H8()}, X27, POST_INDEXED, 48)) +T(0x0c944918, ST3(List{V24.S2(), V25.S2(), V26.S2()}, X8, POST_INDEXED, X20)) +T(0x0d003f80, ST3(List{V0.B(), V1.B(), V2.B()}[7], X28)) +T(0x0d007306, ST3(List{V6.H(), V7.H(), V8.H()}[2], X24)) +T(0x0d00b131, ST3(List{V17.S(), V18.S(), V19.S()}[1], X9)) +T(0x4d00a5f8, ST3(List{V24.D(), V25.D(), V26.D()}[1], X15)) +T(0x0d9f27c1, ST3(List{V1.B(), V2.B(), V3.B()}[1], X30, POST_INDEXED, 3)) +T(0x4d992bb2, ST3(List{V18.B(), V19.B(), V20.B()}[10], X29, POST_INDEXED, X25)) +T(0x0d9f785d, ST3(List{V29.H(), V30.H(), V31.H()}[3], X2, POST_INDEXED, 6)) +T(0x4d8b726b, ST3(List{V11.H(), V12.H(), V13.H()}[6], X19, POST_INDEXED, X11)) +T(0x4d9fa342, ST3(List{V2.S(), V3.S(), V4.S()}[2], X26, POST_INDEXED, 12)) +T(0x4d80b206, ST3(List{V6.S(), V7.S(), V8.S()}[3], X16, POST_INDEXED, X0)) +T(0x4d9fa5de, ST3(List{V30.D(), V31.D(), V0.D()}[1], X14, POST_INDEXED, 24)) +T(0x4d8ba6d7, ST3(List{V23.D(), V24.D(), V25.D()}[1], X22, POST_INDEXED, X11)) +T(0x0c00034f, ST4(List{V15.B8(), V16.B8(), V17.B8(), V18.B8()}, X26)) +T(0x4c9f038c, ST4(List{V12.B16(), V13.B16(), V14.B16(), V15.B16()}, X28, POST_INDEXED, 64)) +T(0x4c800719, ST4(List{V25.H8(), V26.H8(), V27.H8(), V28.H8()}, X24, POST_INDEXED, X0)) +T(0x0d2021a8, ST4(List{V8.B(), V9.B(), V10.B(), V11.B()}[0], X13)) +T(0x4d2062cd, ST4(List{V13.H(), V14.H(), V15.H(), V16.H()}[4], X22)) +T(0x0d20b146, ST4(List{V6.S(), V7.S(), V8.S(), V9.S()}[1], X10)) +T(0x4d20a6f5, ST4(List{V21.D(), V22.D(), V23.D(), V24.D()}[1], X23)) +T(0x0dbf2d56, ST4(List{V22.B(), V23.B(), V24.B(), V25.B()}[3], X10, POST_INDEXED, 4)) +T(0x4da631df, ST4(List{V31.B(), V0.B(), V1.B(), V2.B()}[12], X14, POST_INDEXED, X6)) +T(0x0dbf7a76, ST4(List{V22.H(), V23.H(), V24.H(), V25.H()}[3], X19, POST_INDEXED, 8)) +T(0x0dbb698e, ST4(List{V14.H(), V15.H(), V16.H(), V17.H()}[1], X12, POST_INDEXED, X27)) +T(0x4dbfb37f, ST4(List{V31.S(), V0.S(), V1.S(), V2.S()}[3], X27, POST_INDEXED, 16)) +T(0x4dadb3d1, ST4(List{V17.S(), V18.S(), V19.S(), V20.S()}[3], X30, POST_INDEXED, X13)) +T(0x4dbfa5b3, ST4(List{V19.D(), V20.D(), V21.D(), V22.D()}[1], X13, POST_INDEXED, 32)) +T(0x4db5a7cf, ST4(List{V15.D(), V16.D(), V17.D(), V18.D()}[1], X30, POST_INDEXED, X21)) +T(0x2c29149a, STNP(S26, S5, X4, -184)) +T(0x6c229316, STNP(D22, D4, X24, -472)) +T(0xac3bc3c8, STNP(Q8, Q16, X30, -144)) +T(0x2cacdf66, STP(S6, S23, X27, POST_INDEXED, -156)) +T(0x6c826f4f, STP(D15, D27, X26, POST_INDEXED, 32)) +T(0xac97955a, STP(Q26, Q5, X10, POST_INDEXED, 752)) +T(0x2da7ba37, STP(S23, S14, X17, PRE_INDEXED, -196)) +T(0x6d8bcbce, STP(D14, D18, X30, PRE_INDEXED, 184)) +T(0xad8b4ba6, STP(Q6, Q18, X29, PRE_INDEXED, 352)) +T(0x2d1f7434, STP(S20, S29, X1, 248)) +T(0x6d3bb5d8, STP(D24, D13, X14, -72)) +T(0xad09088a, STP(Q10, Q2, X4, 288)) +T(0x3c066467, STR(B7, X3, POST_INDEXED, 102)) +T(0x7c070723, STR(H3, X25, POST_INDEXED, 112)) +T(0xbc13175a, STR(S26, X26, POST_INDEXED, -207)) +T(0xfc1be536, STR(D22, X9, POST_INDEXED, -66)) +T(0x3c99b56b, STR(Q11, X11, POST_INDEXED, -101)) +T(0x3c002d49, STR(B9, X10, PRE_INDEXED, 2)) +T(0x7c158e09, STR(H9, X16, PRE_INDEXED, -168)) +T(0xbc06bc8d, STR(S13, X4, PRE_INDEXED, 107)) +T(0xfc080eae, STR(D14, X21, PRE_INDEXED, 128)) +T(0x3c8e7ed9, STR(Q25, X22, PRE_INDEXED, 231)) +T(0x3d275492, STR(B18, X4, 2517)) +T(0x7d0b4265, STR(H5, X19, 1440)) +T(0xbd0d2595, STR(S21, X12, 3364)) +T(0xfd237a73, STR(D19, X19, 18160)) +T(0x3db4a5f5, STR(Q21, X15, 53904)) +T(0x3c3e693c, STR(B28, X9, X30, LSL, 0)) +T(0x3c3b6ac5, STR(B5, X22, X27, LSL, 0)) +T(0x7c36faf0, STR(H16, X23, X22, SXTX, 1)) +T(0xbc27f838, STR(S24, X1, X7, SXTX, 2)) +T(0xfc29db51, STR(D17, X26, W9, SXTW, 3)) +T(0x3cbfea8f, STR(Q15, X20, XZR, SXTX)) +T(0x3c0441c8, STUR(B8, X14, 68)) +T(0x7c00b0d7, STUR(H23, X6, 11)) +T(0xbc0d117d, STUR(S29, X11, 209)) +T(0xfc1f03c0, STUR(D0, X30, -16)) +T(0x3c9753f0, STUR(Q16, SP, -139)) +T(0x7eeb84f9, SUB(D25, D7, D11)) +T(0x6e708714, SUB(V20.H8(), V24.H8(), V16.H8())) +T(0x4e766323, SUBHN2(V3.H8(), V25.S4(), V22.S4())) +T(0x5e203935, SUQADD(B21, B9)) +T(0x4e203b33, SUQADD(V19.B16(), V25.B16())) +// SXTL +T(0x0e0c20db, TBL(V27.B8(), List{V6.B16(), V7.B16()}, V12.B8())) +T(0x4e1d43ab, TBL(V11.B16(), List{V29.B16(), V30.B16(), V31.B16()}, V29.B16())) +T(0x0e07634f, TBL(V15.B8(), List{V26.B16(), V27.B16(), V28.B16(), V29.B16()}, V7.B8())) +T(0x0e0603b9, TBL(V25.B8(), List{V29.B16()}, V6.B8())) +T(0x0e05317a, TBX(V26.B8(), List{V11.B16(), V12.B16()}, V5.B8())) +T(0x4e0150ca, TBX(V10.B16(), List{V6.B16(), V7.B16(), V8.B16()}, V1.B16())) +T(0x4e0e7190, TBX(V16.B16(), List{V12.B16(), V13.B16(), V14.B16(), V15.B16()}, V14.B16())) +T(0x4e1b1333, TBX(V19.B16(), List{V25.B16()}, V27.B16())) +T(0x4e0829e3, TRN1(V3.B16(), V15.B16(), V8.B16())) +T(0x4ecc6b24, TRN2(V4.D2(), V25.D2(), V12.D2())) +T(0x2e697f5d, UABA(V29.H4(), V26.H4(), V9.H4())) +T(0x2e36519e, UABAL(V30.H8(), V12.B8(), V22.B8())) +T(0x6e6975e0, UABD(V0.H8(), V15.H8(), V9.H8())) +T(0x2e2e718a, UABDL(V10.H8(), V12.B8(), V14.B8())) +T(0x6ea069b1, UADALP(V17.D2(), V13.S4())) +T(0x2e6d0349, UADDL(V9.S4(), V26.H4(), V13.H4())) +T(0x6e602bfc, UADDLP(V28.S4(), V31.H8())) +T(0x6e703b6d, UADDLV(S13, V27.H8())) +T(0x2e781352, UADDW(V18.S4(), V26.S4(), V24.H4())) +T(0x1e03ec95, UCVTF(S21, W4, 5)) +T(0x1e43fd36, UCVTF(D22, W9, 1)) +T(0x9e03a27b, UCVTF(S27, X19, 24)) +T(0x9e43e9c4, UCVTF(D4, X14, 6)) +T(0x1e230096, UCVTF(S22, W4)) +T(0x1e630076, UCVTF(D22, W3)) +T(0x9e2302c8, UCVTF(S8, X22)) +T(0x9e6302cd, UCVTF(D13, X22)) +T(0x7f2ce5a2, UCVTF(S2, S13, 20)) +T(0x6f4be788, UCVTF(V8.D2(), V28.D2(), 53)) +T(0x7e21d87f, UCVTF(S31, S3)) +T(0x2e21da7d, UCVTF(V29.S2(), V19.S2())) +T(0x2e7b0674, UHADD(V20.H4(), V19.H4(), V27.H4())) +T(0x6ea9277f, UHSUB(V31.S4(), V27.S4(), V9.S4())) +T(0x6e7a6658, UMAX(V24.H8(), V18.H8(), V26.H8())) +T(0x2e23a513, UMAXP(V19.B8(), V8.B8(), V3.B8())) +T(0x2e70a9b5, UMAXV(H21, V13.H4())) +T(0x6e7d6ef2, UMIN(V18.H8(), V23.H8(), V29.H8())) +T(0x2e6eae4e, UMINP(V14.H4(), V18.H4(), V14.H4())) +T(0x2e71abe6, UMINV(H6, V31.H4())) +T(0x6fb820fa, UMLAL2(V26.D2(), V7.S4(), V24.S()[1])) +T(0x6ebc83ab, UMLAL2(V11.D2(), V29.S4(), V28.S4())) +T(0x2f5c61cf, UMLSL(V15.S4(), V14.H4(), V12.H()[1])) +T(0x6e6aa2e2, UMLSL2(V2.S4(), V23.H8(), V10.H8())) +T(0x0e0f3fb8, UMOV(W24, V29.B()[7])) +// UMOV +T(0x6f62a05c, UMULL2(V28.S4(), V2.H8(), V2.H()[2])) +T(0x6e6cc3b0, UMULL2(V16.S4(), V29.H8(), V12.H8())) +T(0x7ea40f68, UQADD(S8, S27, S4)) +T(0x6eac0e8f, UQADD(V15.S4(), V20.S4(), V12.S4())) +T(0x7e2a5df5, UQRSHL(B21, B15, B10)) +T(0x6ef55fc9, UQRSHL(V9.D2(), V30.D2(), V21.D2())) +T(0x7f0b9db4, UQRSHRN(B20, H13, 5)) +T(0x2f159d7d, UQRSHRN(V29.H4(), V11.S4(), 11)) +T(0x7f6c755c, UQSHL(D28, D10, 44)) +T(0x6f6175ec, UQSHL(V12.D2(), V15.D2(), 33)) +T(0x7eef4ff4, UQSHL(D20, D31, D15)) +T(0x6e3d4f2e, UQSHL(V14.B16(), V25.B16(), V29.B16())) +T(0x7f1f94d2, UQSHRN(H18, S6, 1)) +T(0x6f3397e4, UQSHRN2(V4.S4(), V31.D2(), 13)) +T(0x7ee12cad, UQSUB(D13, D5, D1)) +T(0x2e712ff3, UQSUB(V19.H4(), V31.H4(), V17.H4())) +T(0x7e614b06, UQXTN(H6, S24)) +T(0x6e2149ec, UQXTN2(V12.B16(), V15.H8())) +T(0x0ea1c849, URECPE(V9.S2(), V2.S2())) +T(0x6eb51740, URHADD(V0.S4(), V26.S4(), V21.S4())) +T(0x7eeb57f8, URSHL(D24, D31, D11)) +T(0x6e335531, URSHL(V17.B16(), V9.B16(), V19.B16())) +T(0x7f65253d, URSHR(D29, D9, 27)) +T(0x2f102566, URSHR(V6.H4(), V11.H4(), 16)) +T(0x2ea1cb59, URSQRTE(V25.S2(), V26.S2())) +T(0x7f54345f, URSRA(D31, D2, 44)) +T(0x2f1b345f, URSRA(V31.H4(), V2.H4(), 5)) +T(0x7ef94448, USHL(D8, D2, D25)) +T(0x6ea14621, USHL(V1.S4(), V17.S4(), V1.S4())) +T(0x2f33a5a1, USHLL(V1.D2(), V13.S2(), 19)) +T(0x7f5405d0, USHR(D16, D14, 44)) +T(0x6f450505, USHR(V5.D2(), V8.D2(), 59)) +T(0x7ea038c1, USQADD(S1, S6)) +T(0x2e203b60, USQADD(V0.B8(), V27.B8())) +T(0x7f4616d2, USRA(D18, D22, 58)) +T(0x2f1a1713, USRA(V19.H4(), V24.H4(), 6)) +T(0x2e3f226e, USUBL(V14.H8(), V19.B8(), V31.B8())) +T(0x6e7a33a0, USUBW2(V0.S4(), V29.S4(), V26.H8())) +// UXTL +T(0x4e1b1a1f, UZP1(V31.B16(), V16.B16(), V27.B16())) +T(0x4ecc597b, UZP2(V27.D2(), V11.D2(), V12.D2())) +T(0x0e212af7, XTN(V23.B8(), V23.H8())) +T(0x4e853928, ZIP1(V8.S4(), V9.S4(), V5.S4())) +T(0x0e977a78, ZIP2(V24.S2(), V19.S2(), V23.S2())) diff --git a/tests/general.cpp b/tests/general.cpp new file mode 100644 index 00000000..2caf4652 --- /dev/null +++ b/tests/general.cpp @@ -0,0 +1,1079 @@ +// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime +// SPDX-License-Identifier: MIT + +#include +#include + +#include + +#include "oaknut/oaknut.hpp" + +#define T(HEX, CMD) \ + TEST_CASE(#CMD) \ + { \ + using namespace oaknut; \ + using namespace oaknut::util; \ + \ + std::uint32_t result; \ + CodeGenerator code{&result}; \ + \ + code.CMD; \ + \ + REQUIRE(result == HEX); \ + } + +T(0x1a0f01c3, ADC(W3, W14, W15)) +T(0x1a1803a5, ADC(W5, W29, W24)) +T(0x1a0f02b3, ADC(W19, W21, W15)) +T(0x9a0101a0, ADC(X0, X13, X1)) +T(0x9a0e01e7, ADC(X7, X15, X14)) +T(0x9a18031e, ADC(X30, X24, X24)) +T(0x3a04030d, ADCS(W13, W24, W4)) +T(0x3a0f0159, ADCS(W25, W10, W15)) +T(0x3a070042, ADCS(W2, W2, W7)) +T(0xba1003ce, ADCS(X14, X30, X16)) +T(0xba190368, ADCS(X8, X27, X25)) +T(0xba0d01e1, ADCS(X1, X15, X13)) +T(0x0b3c11db, ADD(W27, W14, W28, UXTB, 4)) +T(0x0b27e567, ADD(W7, W11, W7, SXTX, 1)) +T(0x0b232890, ADD(W16, W4, W3, UXTH, 2)) +T(0x8b218f83, ADD(X3, X28, W1, SXTB, 3)) +T(0x8b21d262, ADD(X2, X19, W1, SXTW, 4)) +T(0x11549545, ADD(W5, W10, 1317, LSL, 12)) +T(0x1170da5c, ADD(W28, W18, 3126, LSL, 12)) +T(0x113d5da2, ADD(W2, W13, 3927)) +T(0x91204aa8, ADD(X8, X21, 2066)) +T(0x9123368b, ADD(X11, X20, 2253)) +T(0x917f9912, ADD(X18, X8, 4070, LSL, 12)) +T(0x0b874fb9, ADD(W25, W29, W7, ASR, 19)) +T(0x0b446a2c, ADD(W12, W17, W4, LSR, 26)) +T(0x8b494f4d, ADD(X13, X26, X9, LSR, 19)) +T(0x8b5ff514, ADD(X20, X8, XZR, LSR, 61)) +T(0x2b3e2aa2, ADDS(W2, W21, W30, UXTH, 2)) +T(0x2b34e14a, ADDS(W10, W10, W20, SXTX)) +T(0x2b2a6565, ADDS(W5, W11, W10, UXTX, 1)) +T(0xab226edb, ADDS(X27, X22, X2, UXTX, 3)) +T(0xab29b19a, ADDS(X26, X12, W9, SXTH, 4)) +T(0xab3583f0, ADDS(X16, SP, W21, SXTB)) +T(0x31592de5, ADDS(W5, W15, 1611, LSL, 12)) +T(0x3166dcdd, ADDS(W29, W6, 2487, LSL, 12)) +T(0x312f1c18, ADDS(W24, W0, 3015)) +T(0xb158ff7c, ADDS(X28, X27, 1599, LSL, 12)) +T(0xb108b6af, ADDS(X15, X21, 557)) +T(0xb106c869, ADDS(X9, X3, 434)) +T(0x2b5b05a8, ADDS(W8, W13, W27, LSR, 1)) +T(0xab52ca62, ADDS(X2, X19, X18, LSR, 50)) +// T(0x30075141, ADR(X1, 59945)) +// T(0x100fd28d, ADR(X13, 129616)) +// T(0x7075db19, ADR(X25, 965475)) +// T(0xb0e688f1, ADRP(X17, -854470656)) +// T(0xf03be0fc, ADRP(X28, 2009198592)) +// T(0x90cbd7d4, ADRP(X20, -1750106112)) +T(0x12071254, AND(W20, W18, 0x3e000000)) +T(0x1206a3a4, AND(W4, W29, 0xfc07fc07)) +T(0x12185f4b, AND(W11, W26, 0xffffff00)) +T(0x924f7a4f, AND(X15, X18, 0xfffe00000000ffff)) +T(0x926122c3, AND(X3, X22, 0xff80000000)) +T(0x9265fbce, AND(X14, X30, 0xfffffffffbffffff)) +T(0x0a071d7d, AND(W29, W11, W7, LSL, 7)) +T(0x0a5376ff, AND(WZR, W23, W19, LSR, 29)) +T(0x0a5900b8, AND(W24, W5, W25, LSR, 0)) +T(0x8ad9dc44, AND(X4, X2, X25, ROR, 55)) +T(0x8a872dcc, AND(X12, X14, X7, ASR, 11)) +T(0x8a10d18f, AND(X15, X12, X16, LSL, 52)) +T(0x72086584, ANDS(W4, W12, 0xff03ffff)) +T(0x720e3614, ANDS(W20, W16, 0xfffc0000)) +T(0x720a7a7e, ANDS(W30, W19, 0xffdfffff)) +T(0xf20e4d1b, ANDS(X27, X8, 0xfffc003ffffc003f)) +T(0xf21d6250, ANDS(X16, X18, 0xffffff80ffffff8)) +T(0xf251019a, ANDS(X26, X12, 0x800000000000)) +T(0x6a5875b7, ANDS(W23, W13, W24, LSR, 29)) +T(0x6a5937b7, ANDS(W23, W29, W25, LSR, 13)) +T(0xead7637b, ANDS(X27, X27, X23, ROR, 24)) +T(0xea11f241, ANDS(X1, X18, X17, LSL, 60)) +T(0xeacfca26, ANDS(X6, X17, X15, ROR, 50)) +T(0x13167d11, ASR(W17, W8, 22)) +T(0x9347ff0d, ASR(X13, X24, 7)) +T(0x9361feb4, ASR(X20, X21, 33)) +T(0x9356fda2, ASR(X2, X13, 22)) +T(0x1ac4280a, ASR(W10, W0, W4)) +T(0x1ada2913, ASR(W19, W8, W26)) +T(0x1ac92800, ASR(W0, W0, W9)) +T(0x9ad228b9, ASR(X25, X5, X18)) +T(0x9acf29f8, ASR(X24, X15, X15)) +T(0x9ac82afa, ASR(X26, X23, X8)) +T(0x1ac7293c, ASRV(W28, W9, W7)) +T(0x1ace2a6d, ASRV(W13, W19, W14)) +T(0x1ac929e6, ASRV(W6, W15, W9)) +T(0x9acc2a99, ASRV(X25, X20, X12)) +T(0x9ac129ba, ASRV(X26, X13, X1)) +T(0x9ac22a3f, ASRV(XZR, X17, X2)) +// T(0xd50f78af, AT(SYS 7, C7, C8, 5, X15)) +// T(0xd50c79a4, AT(SYS 4, C7, C9, 5, X4)) +// T(0xd5087926, AT(SYS 0, C7, C9, 1, X6)) +T(0x161e54bf, B(-126266628)) +T(0x17a62057, B(-23559844)) +T(0x16345f90, B(-120488384)) +T(0x5460c564, B(MI, 792748)) +T(0x5436d620, B(EQ, 449220)) +T(0x54036427, B(VC, 27780)) +T(0xb3641538, BFI(X24, X9, 28, 6)) +T(0xb34a08a7, BFI(X7, X5, 54, 3)) +T(0xb34c03e9, BFI(X9, XZR, 52, 1)) +T(0xb36e6c95, BFI(X21, X4, 18, 28)) +T(0xb3621d4f, BFI(X15, X10, 30, 8)) +T(0x330313fb, BFXIL(W27, WZR, 3, 2)) +T(0xb35fc877, BFXIL(X23, X3, 31, 20)) +T(0xb357d093, BFXIL(X19, X4, 23, 30)) +T(0xb377f01b, BFXIL(X27, X0, 55, 6)) +T(0xb377e391, BFXIL(X17, X28, 55, 2)) +T(0xa3920b0, BIC(W16, W5, W25, LSL, 8)) +T(0x8a29fb68, BIC(X8, X27, X9, LSL, 62)) +T(0x8aa8e15d, BIC(X29, X10, X8, ASR, 56)) +T(0x8ab733b6, BIC(X22, X29, X23, ASR, 12)) +T(0x6a7b1ff9, BICS(W25, WZR, W27, LSR, 7)) +T(0xea3d86fd, BICS(X29, X23, X29, LSL, 33)) +T(0xeaf4af4c, BICS(X12, X26, X20, ROR, 43)) +T(0xeaf46b96, BICS(X22, X28, X20, ROR, 26)) +T(0x9708781e, BL(-64888712)) +T(0x95b27a60, BL(113895808)) +T(0x956ab105, BL(95077396)) +T(0xd63f0160, BLR(X11)) +T(0xd63f0220, BLR(X17)) +T(0xd61f0280, BR(X20)) +T(0xd61f0260, BR(X19)) +T(0xd61f0320, BR(X25)) +T(0xd433f1c0, BRK(0x9f8e)) +T(0xd43f7820, BRK(0xfbc1)) +T(0xd43127c0, BRK(0x893e)) +T(0x35a95593, CBNZ(W19, -709968)) +T(0x358d6ef5, CBNZ(W21, -938532)) +T(0x358d05f9, CBNZ(W25, -941892)) +T(0xb5bfb71c, CBNZ(X28, -526624)) +T(0xb5e62555, CBNZ(X21, -211800)) +T(0xb5b24165, CBNZ(X5, -636884)) +T(0x34d12762, CBZ(W2, -383764)) +T(0x34e9aa59, CBZ(W25, -182968)) +T(0x3495c7a7, CBZ(W7, -870156)) +T(0xb429394d, CBZ(X13, 337704)) +T(0xb4acb60f, CBZ(X15, -682304)) +T(0xb445904f, CBZ(X15, 569864)) +T(0x3a406be9, CCMN(WZR, 0, 9, VS)) +T(0x3a4cb9ef, CCMN(W15, 12, 15, LT)) +T(0x3a483a2f, CCMN(W17, 8, 15, LO)) +T(0xba55e821, CCMN(X1, 21, 1, AL)) +T(0xba5fba49, CCMN(X18, 31, 9, LT)) +T(0xba4c4947, CCMN(X10, 12, 7, MI)) +T(0x3a44336e, CCMN(W27, W4, 14, LO)) +T(0x3a4a9046, CCMN(W2, W10, 6, LS)) +T(0x3a4390ce, CCMN(W6, W3, 14, LS)) +T(0xba55e225, CCMN(X17, X21, 5, AL)) +T(0xba52438d, CCMN(X28, X18, 13, MI)) +T(0xba591164, CCMN(X11, X25, 4, NE)) +T(0x7a43ea0e, CCMP(W16, 3, 14, AL)) +T(0x7a57fb0f, CCMP(W24, 23, 15, NV)) +T(0x7a53e9ce, CCMP(W14, 19, 14, AL)) +T(0xfa4a0ba7, CCMP(X29, 10, 7, EQ)) +T(0xfa49daae, CCMP(X21, 9, 14, LE)) +T(0xfa438b89, CCMP(X28, 3, 9, HI)) +T(0x7a4253cc, CCMP(W30, W2, 12, PL)) +T(0x7a48610b, CCMP(W8, W8, 11, VS)) +T(0x7a5400c3, CCMP(W6, W20, 3, EQ)) +T(0xfa44936d, CCMP(X27, X4, 13, LS)) +T(0xfa46220a, CCMP(X16, X6, 10, HS)) +T(0xfa46404c, CCMP(X2, X6, 12, MI)) +T(0x1a92b680, CSINC(W0, W20, W18, LT)) +T(0x1a87651d, CSINC(W29, W8, W7, VS)) +T(0x1a8bb43a, CSINC(W26, W1, W11, LT)) +T(0x9a92e6c4, CSINC(X4, X22, X18, AL)) +T(0x9a99a75c, CSINC(X28, X26, X25, GE)) +T(0x9a993524, CSINC(X4, X9, X25, LO)) +T(0x5a92532b, CSINV(W11, W25, W18, PL)) +T(0x5a987219, CSINV(W25, W16, W24, VC)) +T(0x5a805309, CSINV(W9, W24, W0, PL)) +T(0xda8bb1b1, CSINV(X17, X13, X11, LT)) +T(0xda971187, CSINV(X7, X12, X23, NE)) +T(0xda944246, CSINV(X6, X18, X20, MI)) +T(0xd503315f, CLREX(1)) +T(0xd5033a5f, CLREX(10)) +T(0x5ac0145b, CLS(W27, W2)) +T(0x5ac0152e, CLS(W14, W9)) +T(0x5ac01530, CLS(W16, W9)) +T(0xdac0145b, CLS(X27, X2)) +T(0xdac014b4, CLS(X20, X5)) +T(0xdac0150d, CLS(X13, X8)) +T(0x5ac01274, CLZ(W20, W19)) +T(0x5ac010fc, CLZ(W28, W7)) +T(0x5ac01106, CLZ(W6, W8)) +T(0xdac0105e, CLZ(X30, X2)) +T(0xdac013c3, CLZ(X3, X30)) +T(0xdac010f9, CLZ(X25, X7)) +T(0xab9b277f, CMN(X27, X27, ASR, 9)) +T(0xab25653f, CMN(X9, X5, UXTX, 1)) +T(0xab2cd13f, CMN(X9, W12, SXTW, 4)) +T(0x313834df, CMN(W6, 3597)) +T(0x317958bf, CMN(W5, 3670, LSL, 12)) +T(0x3133573f, CMN(W25, 3285)) +T(0xb15ccd7f, CMN(X11, 1843, LSL, 12)) +T(0xb153569f, CMN(X20, 1237, LSL, 12)) +T(0xb17d193f, CMN(X9, 3910, LSL, 12)) +T(0x2b9b225f, CMN(W18, W27, ASR, 8)) +T(0xab4cfd9f, CMN(X12, X12, LSR, 63)) +T(0xab56fcbf, CMN(X5, X22, LSR, 63)) +T(0x6b35c6df, CMP(W22, W21, SXTW, 1)) +T(0xeb24a7ff, CMP(SP, W4, SXTH, 1)) +T(0xeb32d15f, CMP(X10, W18, SXTW, 4)) +T(0x717d7a5f, CMP(W18, 3934, LSL, 12)) +T(0x7153bcdf, CMP(W6, 1263, LSL, 12)) +T(0x716584ff, CMP(W7, 2401, LSL, 12)) +T(0xf15a64bf, CMP(X5, 1689, LSL, 12)) +T(0xf179805f, CMP(X2, 3680, LSL, 12)) +T(0xf12c6a7f, CMP(X19, 2842)) +T(0xeb4b65bf, CMP(X13, X11, LSR, 25)) +T(0xeb06373f, CMP(X25, X6, LSL, 13)) +T(0x5a89558e, CSNEG(W14, W12, W9, PL)) +T(0x5a8b16d7, CSNEG(W23, W22, W11, NE)) +T(0x5a92345a, CSNEG(W26, W2, W18, LO)) +T(0xda93d75c, CSNEG(X28, X26, X19, LE)) +T(0xda9234c2, CSNEG(X2, X6, X18, LO)) +T(0xda9465af, CSNEG(X15, X13, X20, VS)) +T(0xd503229f, CSDB()) +T(0x1a9f4099, CSEL(W25, W4, WZR, MI)) +T(0x1a8b3138, CSEL(W24, W9, W11, LO)) +T(0x1a8c3041, CSEL(W1, W2, W12, LO)) +T(0x9a9d60d8, CSEL(X24, X6, X29, VS)) +T(0x9a92e2c8, CSEL(X8, X22, X18, AL)) +T(0x9a92a195, CSEL(X21, X12, X18, GE)) +T(0x1a9fd7fa, CSET(W26, GT)) +T(0x1a9f47ec, CSET(W12, PL)) +T(0x1a9f87f0, CSET(W16, LS)) +T(0x9a9ff7ff, CSINC(XZR, XZR, XZR, NV)) +T(0x9a9f17f1, CSET(X17, EQ)) +T(0x9a9fb7ed, CSET(X13, GE)) +T(0x5a9f93e3, CSETM(W3, HI)) +T(0x5a9ff3f3, CSINV(W19, WZR, WZR, NV)) +T(0x5a9fa3f4, CSETM(W20, LT)) +T(0xda9f63e1, CSETM(X1, VC)) +T(0xda9f23ea, CSETM(X10, LO)) +T(0xda9f83ef, CSETM(X15, LS)) +T(0x1a9f14f1, CSINC(W17, W7, WZR, NE)) +T(0x1a93d72a, CSINC(W10, W25, W19, LE)) +T(0x1a87d57f, CSINC(WZR, W11, W7, LE)) +T(0x9a89d45e, CSINC(X30, X2, X9, LE)) +T(0x9a9ed5dc, CSINC(X28, X14, X30, LE)) +T(0x9a9746e8, CINC(X8, X23, PL)) +T(0x5a89f1de, CSINV(W30, W14, W9, NV)) +T(0x5a9a12ae, CSINV(W14, W21, W26, NE)) +T(0x5a9d728b, CSINV(W11, W20, W29, VC)) +T(0xda80e3b0, CSINV(X16, X29, X0, AL)) +T(0xda8102e3, CSINV(X3, X23, X1, EQ)) +T(0xda9692d8, CINV(X24, X22, HI)) +T(0x5a8417bc, CSNEG(W28, W29, W4, NE)) +T(0x5a86d5fb, CSNEG(W27, W15, W6, LE)) +T(0x5a8b0768, CSNEG(W8, W27, W11, EQ)) +T(0xda9145c6, CSNEG(X6, X14, X17, MI)) +T(0xda8da6b7, CSNEG(X23, X21, X13, GE)) +T(0xda9f65c2, CSNEG(X2, X14, XZR, VS)) +// T(0xd50875bc, DC(SYS 0, C7, C5, 5, X28)) +// T(0xd508722b, DC(SYS 0, C7, C2, 1, X11)) +// T(0xd5087c11, DC(SYS 0, C7, C12, 0, X17)) +T(0xd4a82a21, DCPS1(0x4151)) +T(0xd4ba5161, DCPS1(0xd28b)) +T(0xd4b8bae1, DCPS1(0xc5d7)) +T(0xd4b40a62, DCPS2(0xa053)) +T(0xd4b46722, DCPS2(0xa339)) +T(0xd4af6fa2, DCPS2(0x7b7d)) +T(0xd50333bf, DMB(BarrierOp::OSH)) +T(0xd5033dbf, DMB(BarrierOp::LD)) +T(0xd6bf03e0, DRPS()) +T(0xd503369f, DSB(BarrierOp::NSHST)) +T(0x4aa16b70, EON(W16, W27, W1, ASR, 26)) +T(0xcabea85b, EON(X27, X2, X30, ASR, 42)) +T(0xcaf8f8b5, EON(X21, X5, X24, ROR, 62)) +T(0xca6b0eec, EON(X12, X23, X11, LSR, 3)) +T(0x52127454, EOR(W20, W2, 0xffffcfff)) +T(0x52071ca2, EOR(W2, W5, 0xfe000001)) +T(0x52065dfd, EOR(W29, W15, 0xfc03ffff)) +T(0xd27443ce, EOR(X14, X30, 0x1ffff000)) +T(0xd2594c38, EOR(X24, X1, 0x7ffff8000000000)) +T(0x4aca4192, EOR(W18, W12, W10, ROR, 16)) +T(0x4a16409b, EOR(W27, W4, W22, LSL, 16)) +T(0x4a1b2c0e, EOR(W14, W0, W27, LSL, 11)) +T(0xca1512ba, EOR(X26, X21, X21, LSL, 4)) +T(0xcadca40f, EOR(X15, X0, X28, ROR, 41)) +T(0xca450f15, EOR(X21, X24, X5, LSR, 3)) +T(0xd69f03e0, ERET()) +T(0x138122a5, EXTR(W5, W21, W1, 8)) +T(0x13815c7e, EXTR(W30, W3, W1, 23)) +T(0x138b0722, EXTR(W2, W25, W11, 1)) +T(0x93dc0da7, EXTR(X7, X13, X28, 3)) +T(0x93c7929c, EXTR(X28, X20, X7, 36)) +T(0x93dd555c, EXTR(X28, X10, X29, 21)) +T(0xd50323df, HINT(30)) +T(0xd503265f, HINT(50)) +T(0xd50325bf, HINT(45)) +T(0xd456b700, HLT(0xb5b8)) +T(0xd45f5860, HLT(0xfac3)) +T(0xd44658a0, HLT(0x32c5)) +T(0xd4060fa2, HVC(0x307d)) +T(0xd41b5ae2, HVC(0xdad7)) +T(0xd40cec82, HVC(0x6764)) +// T(0xd50f74db, IC(SYS 7, C7, C4, 6, X27)) +// T(0xd50d76eb, IC(SYS 5, C7, C6, 7, X11)) +// T(0xd5087a7d, IC(SYS 0, C7, C10, 3, X29)) +T(0xd5033cdf, ISB((BarrierOp)12)) +T(0xd50339df, ISB((BarrierOp)9)) +T(0xd5033fdf, ISB()) +T(0x88dffded, LDAR(W13, X15)) +T(0x88dffe4a, LDAR(W10, X18)) +T(0x88dffcfe, LDAR(W30, X7)) +T(0xc8dffd7e, LDAR(X30, X11)) +T(0xc8dffdad, LDAR(X13, X13)) +T(0xc8dfff64, LDAR(X4, X27)) +T(0x08dffd0e, LDARB(W14, X8)) +T(0x08dffe0b, LDARB(W11, X16)) +T(0x08dffea3, LDARB(W3, X21)) +T(0x48dffe3d, LDARH(W29, X17)) +T(0x48dffc6f, LDARH(W15, X3)) +T(0x48dffd77, LDARH(W23, X11)) +T(0x887f85e3, LDAXP(W3, W1, X15)) +T(0x887ffbb0, LDAXP(W16, W30, X29)) +T(0x887fa8bb, LDAXP(W27, W10, X5)) +T(0xc87fd995, LDAXP(X21, X22, X12)) +T(0xc87fa4cd, LDAXP(X13, X9, X6)) +T(0xc87fab62, LDAXP(X2, X10, X27)) +T(0x885ffcad, LDAXR(W13, X5)) +T(0x885ffd32, LDAXR(W18, X9)) +T(0x885fffb8, LDAXR(W24, X29)) +T(0xc85fff47, LDAXR(X7, X26)) +T(0xc85ffeba, LDAXR(X26, X21)) +T(0xc85ffdd3, LDAXR(X19, X14)) +T(0x085ffe8a, LDAXRB(W10, X20)) +T(0x085ffcab, LDAXRB(W11, X5)) +T(0x085fffc4, LDAXRB(W4, X30)) +T(0x485ffe71, LDAXRH(W17, X19)) +T(0x485ffc80, LDAXRH(W0, X4)) +T(0x485fffe2, LDAXRH(W2, SP)) +T(0x287aba7d, LDNP(W29, W14, X19, -44)) +T(0x28501c01, LDNP(W1, W7, X0, 128)) +T(0x2844abfd, LDNP(W29, W10, SP, 36)) +T(0xa86e004b, LDNP(X11, X0, X2, -288)) +T(0xa8674a62, LDNP(X2, X18, X19, -400)) +T(0xa8725931, LDNP(X17, X22, X9, -224)) +T(0x28de404b, LDP(W11, W16, X2, POST_INDEXED, 240)) +T(0x28f72aed, LDP(W13, W10, X23, POST_INDEXED, -72)) +T(0x28d4aff5, LDP(W21, W11, SP, POST_INDEXED, 164)) +T(0xa8e14240, LDP(X0, X16, X18, POST_INDEXED, -496)) +T(0xa8ee6fd6, LDP(X22, X27, X30, POST_INDEXED, -288)) +T(0xa8c07927, LDP(X7, X30, X9, POST_INDEXED, 0)) +T(0x29de4596, LDP(W22, W17, X12, PRE_INDEXED, 240)) +T(0x29f8cee7, LDP(W7, W19, X23, PRE_INDEXED, -60)) +T(0xa9cd981b, LDP(X27, X6, X0, PRE_INDEXED, 216)) +T(0xa9f73e53, LDP(X19, X15, X18, PRE_INDEXED, -144)) +T(0xa9d669ae, LDP(X14, X26, X13, PRE_INDEXED, 352)) +T(0x297c5bc9, LDP(W9, W22, X30, -32)) +T(0x29564676, LDP(W22, W17, X19, 176)) +T(0x29723d75, LDP(W21, W15, X11, -112)) +T(0xa946c500, LDP(X0, X17, X8, 104)) +T(0xa97cbf1f, LDP(XZR, X15, X24, -56)) +T(0xa952210c, LDP(X12, X8, X8, 288)) +T(0x68f9e362, LDPSW(X2, X24, X27, POST_INDEXED, -52)) +T(0x68cff36c, LDPSW(X12, X28, X27, POST_INDEXED, 124)) +T(0x69e6a236, LDPSW(X22, X8, X17, PRE_INDEXED, -204)) +T(0x69fa7e8f, LDPSW(X15, XZR, X20, PRE_INDEXED, -48)) +T(0x69c0ecf8, LDPSW(X24, X27, X7, PRE_INDEXED, 4)) +T(0x697ebeb0, LDPSW(X16, X15, X21, -12)) +T(0x697f2aaf, LDPSW(X15, X10, X21, -8)) +T(0x69681917, LDPSW(X23, X6, X8, -192)) +T(0xb857042d, LDR(W13, X1, POST_INDEXED, -144)) +T(0xb85197cf, LDR(W15, X30, POST_INDEXED, -231)) +T(0xb84de5c5, LDR(W5, X14, POST_INDEXED, 222)) +T(0xf85e049a, LDR(X26, X4, POST_INDEXED, -32)) +T(0xf84bd5f3, LDR(X19, X15, POST_INDEXED, 189)) +T(0xb85e5c14, LDR(W20, X0, PRE_INDEXED, -27)) +T(0xb84f7f9d, LDR(W29, X28, PRE_INDEXED, 247)) +T(0xb85afc3e, LDR(W30, X1, PRE_INDEXED, -81)) +T(0xf85b7fc3, LDR(X3, X30, PRE_INDEXED, -73)) +T(0xf852cd3b, LDR(X27, X9, PRE_INDEXED, -212)) +T(0xf85c2d0f, LDR(X15, X8, PRE_INDEXED, -62)) +T(0xb940fb87, LDR(W7, X28, 248)) +T(0xb96d8f49, LDR(W9, X26, 11660)) +T(0xb95633e8, LDR(W8, SP, 5680)) +T(0xf95f6c29, LDR(X9, X1, 16088)) +T(0xf94a36b7, LDR(X23, X21, 5224)) +T(0xf96d8b38, LDR(X24, X25, 23312)) +T(0x18e56d56, LDR(W22, -217688)) +T(0x181c65d5, LDR(W21, 232632)) +T(0x185384ef, LDR(W15, 684188)) +T(0x58d694fb, LDR(X27, -339300)) +T(0x5874d1e9, LDR(X9, 956988)) +T(0x58030db3, LDR(X19, 25012)) +T(0xb861d9f7, LDR(W23, X15, W1, SXTW, 2)) +T(0xb864f8fa, LDR(W26, X7, X4, SXTX, 2)) +T(0xf861da0c, LDR(X12, X16, W1, SXTW, 3)) +T(0xf8687a2b, LDR(X11, X17, X8, LSL, 3)) +T(0x385a47e7, LDRB(W7, SP, POST_INDEXED, -92)) +T(0x3843e560, LDRB(W0, X11, POST_INDEXED, 62)) +T(0x3845244b, LDRB(W11, X2, POST_INDEXED, 82)) +T(0x38418de0, LDRB(W0, X15, PRE_INDEXED, 24)) +T(0x3851ac56, LDRB(W22, X2, PRE_INDEXED, -230)) +T(0x38498f45, LDRB(W5, X26, PRE_INDEXED, 152)) +T(0x396c81d3, LDRB(W19, X14, 2848)) +T(0x394088bd, LDRB(W29, X5, 34)) +T(0x3974ea54, LDRB(W20, X18, 3386)) +T(0x387b49b1, LDRB(W17, X13, W27, UXTW, 0)) +T(0x38706a97, LDRB(W23, X20, X16)) +T(0x38756b62, LDRB(W2, X27, X21, LSL, 0)) +T(0x38686841, LDRB(W1, X2, X8, LSL, 0)) +T(0x7856f77e, LDRH(W30, X27, POST_INDEXED, -145)) +T(0x785be40f, LDRH(W15, X0, POST_INDEXED, -66)) +T(0x784a043b, LDRH(W27, X1, POST_INDEXED, 160)) +T(0x784bbe81, LDRH(W1, X20, PRE_INDEXED, 187)) +T(0x7845ec86, LDRH(W6, X4, PRE_INDEXED, 94)) +T(0x78512d87, LDRH(W7, X12, PRE_INDEXED, -238)) +T(0x797ac1bc, LDRH(W28, X13, 7520)) +T(0x797091bc, LDRH(W28, X13, 6216)) +T(0x79538523, LDRH(W3, X9, 2498)) +T(0x78757a85, LDRH(W5, X20, X21, LSL, 1)) +T(0x7878f80a, LDRH(W10, X0, X24, SXTX, 1)) +T(0x38d04427, LDRSB(W7, X1, POST_INDEXED, -252)) +T(0x38c17465, LDRSB(W5, X3, POST_INDEXED, 23)) +T(0x38d1f616, LDRSB(W22, X16, POST_INDEXED, -225)) +T(0x3886e710, LDRSB(X16, X24, POST_INDEXED, 110)) +T(0x3894258d, LDRSB(X13, X12, POST_INDEXED, -190)) +T(0x3882254b, LDRSB(X11, X10, POST_INDEXED, 34)) +T(0x38d99eba, LDRSB(W26, X21, PRE_INDEXED, -103)) +T(0x38d21f0d, LDRSB(W13, X24, PRE_INDEXED, -223)) +T(0x38c75ff4, LDRSB(W20, SP, PRE_INDEXED, 117)) +T(0x388e3da0, LDRSB(X0, X13, PRE_INDEXED, 227)) +T(0x3886fff8, LDRSB(X24, SP, PRE_INDEXED, 111)) +T(0x3882fe8d, LDRSB(X13, X20, PRE_INDEXED, 47)) +T(0x39e989ce, LDRSB(W14, X14, 2658)) +T(0x39da8524, LDRSB(W4, X9, 1697)) +T(0x39e3909d, LDRSB(W29, X4, 2276)) +T(0x39ae7a3e, LDRSB(X30, X17, 2974)) +T(0x398b4e17, LDRSB(X23, X16, 723)) +T(0x398cb244, LDRSB(X4, X18, 812)) +T(0x38ede9b6, LDRSB(W22, X13, X13, SXTX)) +T(0x38ffe87a, LDRSB(W26, X3, XZR, SXTX)) +T(0x38fc698c, LDRSB(W12, X12, X28, LSL, 0)) +T(0x38e16b71, LDRSB(W17, X27, X1)) +T(0x38f368f0, LDRSB(W16, X7, X19)) +T(0x38bce899, LDRSB(X25, X4, X28, SXTX)) +T(0x38bf694a, LDRSB(X10, X10, XZR)) +T(0x38a869b4, LDRSB(X20, X13, X8, LSL, 0)) +T(0x38b86afb, LDRSB(X27, X23, X24, LSL, 0)) +T(0x78dc0784, LDRSH(W4, X28, POST_INDEXED, -64)) +T(0x78c5f7c7, LDRSH(W7, X30, POST_INDEXED, 95)) +T(0x78db3723, LDRSH(W3, X25, POST_INDEXED, -77)) +T(0x78810605, LDRSH(X5, X16, POST_INDEXED, 16)) +T(0x7884d7e3, LDRSH(X3, SP, POST_INDEXED, 77)) +T(0x7893e745, LDRSH(X5, X26, POST_INDEXED, -194)) +T(0x78da1d4f, LDRSH(W15, X10, PRE_INDEXED, -95)) +T(0x78c47c8b, LDRSH(W11, X4, PRE_INDEXED, 71)) +T(0x78c75e77, LDRSH(W23, X19, PRE_INDEXED, 117)) +T(0x7896fe3b, LDRSH(X27, X17, PRE_INDEXED, -145)) +T(0x78836e99, LDRSH(X25, X20, PRE_INDEXED, 54)) +T(0x7890dcc1, LDRSH(X1, X6, PRE_INDEXED, -243)) +T(0x79dd82a5, LDRSH(W5, X21, 3776)) +T(0x79e451c9, LDRSH(W9, X14, 4648)) +T(0x79f3be44, LDRSH(W4, X18, 6622)) +T(0x7981cf94, LDRSH(X20, X28, 230)) +T(0x79b5a85b, LDRSH(X27, X2, 6868)) +T(0x79ad99be, LDRSH(X30, X13, 5836)) +T(0x78abf997, LDRSH(X23, X12, X11, SXTX, 1)) +T(0x78b4f93d, LDRSH(X29, X9, X20, SXTX, 1)) +T(0x78b66a76, LDRSH(X22, X19, X22)) +T(0xb891c49f, LDRSW(XZR, X4, POST_INDEXED, -228)) +T(0xb88a86cd, LDRSW(X13, X22, POST_INDEXED, 168)) +T(0xb88844ee, LDRSW(X14, X7, POST_INDEXED, 132)) +T(0xb8824db0, LDRSW(X16, X13, PRE_INDEXED, 36)) +T(0xb8998d1e, LDRSW(X30, X8, PRE_INDEXED, -104)) +T(0xb8904e5a, LDRSW(X26, X18, PRE_INDEXED, -252)) +T(0xb9a69275, LDRSW(X21, X19, 9872)) +T(0xb99456ca, LDRSW(X10, X22, 5204)) +T(0xb99041d6, LDRSW(X22, X14, 4160)) +T(0x98849e3a, LDRSW(X26, -1010748)) +T(0x98ae0db5, LDRSW(X21, -671308)) +T(0x9845170c, LDRSW(X12, 565984)) +T(0xb8bc496b, LDRSW(X11, X11, W28, UXTW)) +T(0xb85fc933, LDTR(W19, X9, -4)) +T(0xb84e08ce, LDTR(W14, X6, 224)) +T(0xb842db08, LDTR(W8, X24, 45)) +T(0xf849dbac, LDTR(X12, X29, 157)) +T(0xf84aab89, LDTR(X9, X28, 170)) +T(0xf84bf83f, LDTR(XZR, X1, 191)) +T(0x385ffb66, LDTRB(W6, X27, -1)) +T(0x38455a34, LDTRB(W20, X17, 85)) +T(0x38433b32, LDTRB(W18, X25, 51)) +T(0x785ca9f3, LDTRH(W19, X15, -54)) +T(0x7854f9b5, LDTRH(W21, X13, -177)) +T(0x7856b8f4, LDTRH(W20, X7, -149)) +T(0x38cbea18, LDTRSB(W24, X16, 190)) +T(0x38ca88d0, LDTRSB(W16, X6, 168)) +T(0x38cc1bd8, LDTRSB(W24, X30, 193)) +T(0x389fa9a8, LDTRSB(X8, X13, -6)) +T(0x388628f0, LDTRSB(X16, X7, 98)) +T(0x3880199d, LDTRSB(X29, X12, 1)) +T(0x78d329fc, LDTRSH(W28, X15, -206)) +T(0x78d8fb34, LDTRSH(W20, X25, -113)) +T(0x7883c8e4, LDTRSH(X4, X7, 60)) +T(0x78974a26, LDTRSH(X6, X17, -140)) +T(0x7888ba87, LDTRSH(X7, X20, 139)) +T(0xb88b88ce, LDTRSW(X14, X6, 184)) +T(0xb88e6892, LDTRSW(X18, X4, 230)) +T(0xb88cc9b0, LDTRSW(X16, X13, 204)) +T(0xb85f601a, LDUR(W26, X0, -10)) +T(0xb844e151, LDUR(W17, X10, 78)) +T(0xb85f22d1, LDUR(W17, X22, -14)) +T(0xf8449218, LDUR(X24, X16, 73)) +T(0xf853b150, LDUR(X16, X10, -197)) +T(0xf8541206, LDUR(X6, X16, -191)) +T(0x384101cf, LDURB(W15, X14, 16)) +T(0x385b417b, LDURB(W27, X11, -76)) +T(0x385e01f8, LDURB(W24, X15, -32)) +T(0x785a21e0, LDURH(W0, X15, -94)) +T(0x7856f341, LDURH(W1, X26, -145)) +T(0x7856c3cd, LDURH(W13, X30, -148)) +T(0x38d5a116, LDURSB(W22, X8, -166)) +T(0x38db5091, LDURSB(W17, X4, -75)) +T(0x38c731f0, LDURSB(W16, X15, 115)) +T(0x389c6359, LDURSB(X25, X26, -58)) +T(0x389e321e, LDURSB(X30, X16, -29)) +T(0x389ab0e7, LDURSB(X7, X7, -85)) +T(0x78de7285, LDURSH(W5, X20, -25)) +T(0x78c14227, LDURSH(W7, X17, 20)) +T(0x78d6d094, LDURSH(W20, X4, -147)) +T(0x788ee161, LDURSH(X1, X11, 238)) +T(0x789951b6, LDURSH(X22, X13, -107)) +T(0x789ab083, LDURSH(X3, X4, -85)) +T(0xb89a4372, LDURSW(X18, X27, -92)) +T(0xb88e2029, LDURSW(X9, X1, 226)) +T(0xb8896116, LDURSW(X22, X8, 150)) +T(0x887f602f, LDXP(W15, W24, X1)) +T(0x887f27af, LDXP(W15, W9, X29)) +T(0x887f2b3f, LDXP(WZR, W10, X25)) +T(0xc87f17fe, LDXP(X30, X5, SP)) +T(0xc87f2e82, LDXP(X2, X11, X20)) +T(0xc87f3482, LDXP(X2, X13, X4)) +T(0x885f7cb5, LDXR(W21, X5)) +T(0x885f7d07, LDXR(W7, X8)) +T(0x885f7cb2, LDXR(W18, X5)) +T(0xc85f7e09, LDXR(X9, X16)) +T(0xc85f7ca0, LDXR(X0, X5)) +T(0xc85f7ea3, LDXR(X3, X21)) +T(0x85f7e1b, LDXRB(W27, X16)) +T(0x85f7f20, LDXRB(W0, X25)) +T(0x85f7c52, LDXRB(W18, X2)) +T(0x485f7c04, LDXRH(W4, X0)) +T(0x485f7f5a, LDXRH(W26, X26)) +T(0x485f7dad, LDXRH(W13, X13)) +T(0xd34f2f99, UBFIZ(X25, X28, 49, 12)) +T(0xd37011fb, UBFIZ(X27, X15, 16, 5)) +T(0xd37248f9, UBFIZ(X25, X7, 14, 19)) +T(0x1ac9220c, LSL(W12, W16, W9)) +T(0x1ad723b1, LSL(W17, W29, W23)) +T(0x1ad8222c, LSL(W12, W17, W24)) +T(0x9ada23a7, LSL(X7, X29, X26)) +T(0x9ad72280, LSL(X0, X20, X23)) +T(0x9aca212b, LSL(X11, X9, X10)) +T(0x1ace21f9, LSLV(W25, W15, W14)) +T(0x1ac8202e, LSLV(W14, W1, W8)) +T(0x1ac02127, LSLV(W7, W9, W0)) +T(0x9ad12327, LSLV(X7, X25, X17)) +T(0x9ad12167, LSLV(X7, X11, X17)) +T(0x9ac721e9, LSLV(X9, X15, X7)) +T(0x53157dee, LSR(W14, W15, 21)) +T(0x53117d59, LSR(W25, W10, 17)) +T(0xd37cff9a, LSR(X26, X28, 60)) +T(0xd36afc35, LSR(X21, X1, 42)) +T(0xd37eff6d, LSR(X13, X27, 62)) +T(0x1ac32537, LSR(W23, W9, W3)) +T(0x1adc268a, LSR(W10, W20, W28)) +T(0x1ad027df, LSR(WZR, W30, W16)) +T(0x9ac626b5, LSR(X21, X21, X6)) +T(0x9acb251d, LSR(X29, X8, X11)) +T(0x9ad42493, LSR(X19, X4, X20)) +T(0x1acf2548, LSRV(W8, W10, W15)) +T(0x1ac826ec, LSRV(W12, W23, W8)) +T(0x1ac12589, LSRV(W9, W12, W1)) +T(0x9ad22489, LSRV(X9, X4, X18)) +T(0x9add25e8, LSRV(X8, X15, X29)) +T(0x9ad825f6, LSRV(X22, X15, X24)) +T(0x1b185084, MADD(W4, W4, W24, W20)) +T(0x1b0422b8, MADD(W24, W21, W4, W8)) +T(0x1b0720e1, MADD(W1, W7, W7, W8)) +T(0x9b1d2216, MADD(X22, X16, X29, X8)) +T(0x9b140a27, MADD(X7, X17, X20, X2)) +T(0x9b152674, MADD(X20, X19, X21, X9)) +T(0x1b17fc9d, MNEG(W29, W4, W23)) +T(0x1b08fd74, MNEG(W20, W11, W8)) +T(0x1b1cfd9a, MNEG(W26, W12, W28)) +T(0x9b03fd73, MNEG(X19, X11, X3)) +T(0x9b0bffca, MNEG(X10, X30, X11)) +T(0x9b0bfcd5, MNEG(X21, X6, X11)) +// T(0x320693ff, MOV(MOV WSP, 2080406528)) +// T(0x320663ea, MOV(ORR W10, WZR, 0xfc07ffff)) +// T(0x322417f2, MOV(MOV W18, -268435453)) +// T(0xb22dbbf7, MOV(MOV X23, -1125917086973957)) +// T(0xb2611ff7, MOV(MOV X23, 547608330240)) +// T(0xb249f3f6, MOV(ORR X22, XZR, 0xff8fffffffffffff)) +// T(0x12bbdad5, MOV(MOV W21, 556400639)) +// T(0x128268c7, MOV(MOV W7, -4935)) +// T(0x12bc99eb, MOV(MOV W11, 456196095)) +// T(0x92b235cc, MOV(MOV X12, -2444099585)) +// T(0x92beced5, MOV(MOV X21, -4134928385)) +// T(0x92a00188, MOV(MOV X8, -786433)) +T(0x2a1b03f2, MOV(W18, W27)) +T(0x2a1603e5, MOV(W5, W22)) +T(0x2a0c03ea, MOV(W10, W12)) +T(0xaa1a03ec, MOV(X12, X26)) +T(0xaa1e03e4, MOV(X4, X30)) +T(0xaa1303f6, MOV(X22, X19)) +T(0x1100004d, ADD(W13, W2, 0)) +T(0x1100004e, ADD(W14, W2, 0)) +T(0x1100038f, ADD(W15, W28, 0)) +T(0x910001dd, ADD(X29, X14, 0)) +T(0x91000054, ADD(X20, X2, 0)) +T(0x910001d6, ADD(X22, X14, 0)) +// T(0x52911b84, MOV(MOV W4, 35036)) +// T(0x529956c5, MOV(MOV W5, 51894)) +// T(0x529b9816, MOV(MOV W22, 56512)) +// T(0xd2acc067, MOV(MOV X7, 1711472640)) +// T(0xd28fcc02, MOV(MOV X2, 32352)) +// T(0xd2dbbfce, MOV(MOV X14, 244082991431680)) +T(0x72883d49, MOVK(W9, 16874)) +T(0x72811bd7, MOVK(W23, 2270)) +T(0x72a0d0e1, MOVK(W1, {1671, MovImm16Shift::SHL_16})) +T(0xf2b37940, MOVK(X0, {39882, MovImm16Shift::SHL_16})) +T(0xf2bfb1bf, MOVK(XZR, {64909, MovImm16Shift::SHL_16})) +T(0xf2e780fd, MOVK(X29, {15367, MovImm16Shift::SHL_48})) +// T(0x128b63db, MOVN(MOV W27, -23327)) +// T(0x1298ee46, MOVN(MOV W6, -51059)) +// T(0x128454b9, MOVN(MOV W25, -8870)) +// T(0x9280ff93, MOVN(MOV X19, -2045)) +// T(0x92b2768b, MOVN(MOV X11, -2478047233)) +// T(0x92f56f4b, MOVN(MOV X11, 6090555546065174527)) +T(0x52b62758, MOVZ(W24, 0xB13A0000)) +T(0x52b14a9e, MOVZ(W30, 0x8A540000)) +T(0x52837eec, MOVZ(W12, 7159)) +T(0xd2b5562c, MOVZ(X12, 2863726592)) +T(0xd2bbe6f6, MOVZ(X22, 3744923648)) +T(0xd2c2e35b, MOVZ(X27, 25400436588544)) +// T(0xd533be2b, MRS(X11, S2_3_C11_C14_1)) +// T(0xd53029c4, MRS(X4, S2_0_C2_C9_6)) +// T(0xd5379580, MRS(X0, S2_7_C9_C5_4)) +// T(0xd50640df, MSR(S0_6_C4_C0_6, XZR)) +// T(0xd5034a9f, MSR(S0_3_C4_C10_4, XZR)) +// T(0xd5074d3f, MSR(S0_7_C4_C13_1, XZR)) +// T(0xd5182f8f, MSR(S3_0_C2_C15_4, X15)) +// T(0xd511a258, MSR(S2_1_C10_C2_2, X24)) +// T(0xd51cdea7, MSR(S3_4_C13_C14_5, X7)) +T(0x1b0f962c, MSUB(W12, W17, W15, W5)) +T(0x1b01e98d, MSUB(W13, W12, W1, W26)) +T(0x1b12c7dd, MSUB(W29, W30, W18, W17)) +T(0x9b088341, MSUB(X1, X26, X8, X0)) +T(0x9b19e742, MSUB(X2, X26, X25, X25)) +T(0x9b12c009, MSUB(X9, X0, X18, X16)) +T(0x1b007e8f, MUL(W15, W20, W0)) +T(0x1b087dad, MUL(W13, W13, W8)) +T(0x1b1b7ebc, MUL(W28, W21, W27)) +T(0x9b097ce8, MUL(X8, X7, X9)) +T(0x9b1f7e8f, MUL(X15, X20, XZR)) +T(0x9b107dc0, MUL(X0, X14, X16)) +T(0x2a3c27ec, MVN(W12, W28, LSL, 9)) +T(0xaa2bbbff, MVN(XZR, X11, LSL, 46)) +T(0xaa7abff4, MVN(X20, X26, LSR, 47)) +T(0xaa786beb, MVN(X11, X24, LSR, 26)) +T(0x4b9643e6, NEG(W6, W22, ASR, 16)) +T(0xcb8acffc, NEG(X28, X10, ASR, 51)) +T(0xcb5a97fc, NEG(X28, X26, LSR, 37)) +T(0x6b562be9, NEGS(W9, W22, LSR, 10)) +T(0x6b9177f3, NEGS(W19, W17, ASR, 29)) +T(0xeb9ca3eb, NEGS(X11, X28, ASR, 40)) +T(0xeb407beb, NEGS(X11, X0, LSR, 30)) +T(0xeb878be5, NEGS(X5, X7, ASR, 34)) +T(0x5a0f03e7, NGC(W7, W15)) +T(0x5a0103ed, NGC(W13, W1)) +T(0x5a0803e9, NGC(W9, W8)) +T(0xda1a03fa, NGC(X26, X26)) +T(0xda1503eb, NGC(X11, X21)) +T(0xda1a03f9, NGC(X25, X26)) +T(0x7a0203e2, NGCS(W2, W2)) +T(0x7a0003e0, NGCS(W0, W0)) +T(0x7a0a03f0, NGCS(W16, W10)) +T(0xfa1f03e1, NGCS(X1, XZR)) +T(0xfa1603f1, NGCS(X17, X22)) +T(0xfa1703f4, NGCS(X20, X23)) +T(0xd503201f, NOP()) +T(0xaae78e17, ORN(X23, X16, X7, ROR, 35)) +T(0xaa7990e9, ORN(X9, X7, X25, LSR, 36)) +T(0xaaefa800, ORN(X0, X0, X15, ROR, 42)) +T(0x32009ac2, ORR(W2, W22, 0x7f007f)) +T(0x32066167, ORR(W7, W11, 0xfc07ffff)) +T(0x32032ab2, ORR(W18, W21, 0xe00000ff)) +T(0xb25c9b18, ORR(X24, X24, 0xfffffff0000007ff)) +T(0xb205b7ce, ORR(X14, X30, 0xf9fff9fff9fff9ff)) +T(0xb24d4190, ORR(X16, X12, 0xfff800000000000f)) +T(0x2add28ac, ORR(W12, W5, W29, ROR, 10)) +T(0x2a556110, ORR(W16, W8, W21, LSR, 24)) +T(0xaa977e5e, ORR(X30, X18, X23, ASR, 31)) +T(0xaa949fd6, ORR(X22, X30, X20, ASR, 39)) +T(0xaa918fd6, ORR(X22, X30, X17, ASR, 35)) +// T(0xf98f5696, PRFM(22, [X20, 7848])) +// T(0xf9ae98c3, PRFM(PLDL2STRM, [X6, 23856])) +// T(0xf983faf6, PRFM(22, [X23, 2032])) +// T(0xd8062b53, PRFM(PSTL2STRM, 50536)) +// T(0xd88f84ae, PRFM(14, -921452)) +// T(0xd8b42918, PRFM(24, -621280)) +// T(0xf8b4fa1b, PRFM(27, [X16, X20, SXTX 3])) +// T(0xf894b04a, PRFUM(PLIL2KEEP, [X2, -181])) +// T(0xf88090f8, PRFUM(24, [X7, 9])) +// T(0xf881126c, PRFUM(PLIL3KEEP, [X19, 17])) +T(0xd503349f, PSSBB()) +T(0x5ac00290, RBIT(W16, W20)) +T(0x5ac000b4, RBIT(W20, W5)) +T(0x5ac0031c, RBIT(W28, W24)) +T(0xdac003ee, RBIT(X14, XZR)) +T(0xdac000bb, RBIT(X27, X5)) +T(0xdac0003a, RBIT(X26, X1)) +T(0xd65f0220, RET(X17)) +T(0xd65f0080, RET(X4)) +T(0xd65f0300, RET(X24)) +T(0x5ac00940, REV(W0, W10)) +T(0x5ac00931, REV(W17, W9)) +T(0x5ac00a6e, REV(W14, W19)) +T(0xdac00dfc, REV(X28, X15)) +T(0xdac00e46, REV(X6, X18)) +T(0xdac00fef, REV(X15, XZR)) +T(0x5ac0057c, REV16(W28, W11)) +T(0x5ac0042a, REV16(W10, W1)) +T(0x5ac005f8, REV16(W24, W15)) +T(0xdac00687, REV16(X7, X20)) +T(0xdac0046b, REV16(X11, X3)) +T(0xdac00774, REV16(X20, X27)) +T(0xdac009e5, REV32(X5, X15)) +T(0xdac00b37, REV32(X23, X25)) +T(0xdac0098b, REV32(X11, X12)) +T(0xdac00ccc, REV64(X12, X6)) +T(0xdac00d1c, REV64(X28, X8)) +T(0xdac00e07, REV64(X7, X16)) +T(0x138f39e1, ROR(W1, W15, 14)) +T(0x13836129, EXTR(W9, W9, W3, 24)) +T(0x1399195c, EXTR(W28, W10, W25, 6)) +T(0x93d42677, EXTR(X23, X19, X20, 9)) +T(0x93c7673d, EXTR(X29, X25, X7, 25)) +T(0x93d30b75, EXTR(X21, X27, X19, 2)) +T(0x1ad22e2c, ROR(W12, W17, W18)) +T(0x1ad32f22, ROR(W2, W25, W19)) +T(0x1ac92fb4, ROR(W20, W29, W9)) +T(0x9ad62c41, ROR(X1, X2, X22)) +T(0x9ac82ec8, ROR(X8, X22, X8)) +T(0x9ad02caf, ROR(X15, X5, X16)) +T(0x1ad72c7b, RORV(W27, W3, W23)) +T(0x1ac32e89, RORV(W9, W20, W3)) +T(0x1ad72f7f, RORV(WZR, W27, W23)) +T(0x9ad02d91, RORV(X17, X12, X16)) +T(0x9ac12c0f, RORV(X15, X0, X1)) +T(0x9ac82e05, RORV(X5, X16, X8)) +// T(0xd50330ff, SB(MSR S0_3_C3_C0_7, XZR)) +// T(0xd50330ff, SB(MSR S0_3_C3_C0_7, XZR)) +// T(0xd50330ff, SB(MSR S0_3_C3_C0_7, XZR)) +T(0x5a1103d2, SBC(W18, W30, W17)) +T(0x5a14037a, SBC(W26, W27, W20)) +T(0x5a1e01b6, SBC(W22, W13, W30)) +T(0xda07039a, SBC(X26, X28, X7)) +T(0xda000302, SBC(X2, X24, X0)) +T(0xda040328, SBC(X8, X25, X4)) +T(0x7a150381, SBCS(W1, W28, W21)) +T(0x7a0c00b4, SBCS(W20, W5, W12)) +T(0x7a0901ff, SBCS(WZR, W15, W9)) +T(0xfa1300cd, SBCS(X13, X6, X19)) +T(0xfa0803b2, SBCS(X18, X29, X8)) +T(0xfa0a02db, SBCS(X27, X22, X10)) +T(0x13071e06, SBFX(W6, W16, 7, 1)) +T(0x935dec9e, SBFX(X30, X4, 29, 31)) +T(0x93425b46, SBFX(X6, X26, 2, 21)) +T(0x937b1839, SBFIZ(X25, X1, 5, 7)) +T(0x934fc2e5, SBFX(X5, X23, 15, 34)) +T(0x937c9c6a, SBFIZ(X10, X3, 4, 40)) +T(0x9342c6d5, SBFX(X21, X22, 2, 48)) +T(0x937bdfaf, SBFIZ(X15, X29, 5, 56)) +T(0x934cc132, SBFX(X18, X9, 12, 37)) +T(0x93532a0d, SBFIZ(X13, X16, 45, 11)) +T(0x1ac40e5c, SDIV(W28, W18, W4)) +T(0x1ac90d95, SDIV(W21, W12, W9)) +T(0x1ad90da9, SDIV(W9, W13, W25)) +T(0x9ad70d33, SDIV(X19, X9, X23)) +T(0x9ad80e4f, SDIV(X15, X18, X24)) +T(0x9ada0fc1, SDIV(X1, X30, X26)) +T(0xd503209f, SEV()) +T(0xd50320bf, SEVL()) +T(0x9b263e23, SMADDL(X3, W17, W6, X15)) +T(0x9b3b6702, SMADDL(X2, W24, W27, X25)) +T(0x9b3365e9, SMADDL(X9, W15, W19, X25)) +T(0x9b36ff09, SMNEGL(X9, W24, W22)) +T(0x9b39fcb4, SMNEGL(X20, W5, W25)) +T(0x9b34ff4a, SMNEGL(X10, W26, W20)) +T(0x9b3cd6be, SMSUBL(X30, W21, W28, X21)) +T(0x9b38a754, SMSUBL(X20, W26, W24, X9)) +T(0x9b20986b, SMSUBL(X11, W3, W0, X6)) +T(0x9b527d97, SMULH(X23, X12, X18)) +T(0x9b4f7f85, SMULH(X5, X28, X15)) +T(0x9b437caf, SMULH(X15, X5, X3)) +T(0x9b247cb0, SMULL(X16, W5, W4)) +T(0x9b217e14, SMULL(X20, W16, W1)) +T(0x9b327d93, SMULL(X19, W12, W18)) +T(0xd503309f, SSBB()) +T(0x889ffcb9, STLR(W25, X5)) +T(0x889fff50, STLR(W16, X26)) +T(0x889fffd4, STLR(W20, X30)) +T(0xc89fff60, STLR(X0, X27)) +T(0xc89fff1b, STLR(X27, X24)) +T(0xc89fff6f, STLR(X15, X27)) +T(0x89ffd4e, STLRB(W14, X10)) +T(0x89ffc3a, STLRB(W26, X1)) +T(0x89fff47, STLRB(W7, X26)) +T(0x489ffd4e, STLRH(W14, X10)) +T(0x489fff75, STLRH(W21, X27)) +T(0x489ffe16, STLRH(W22, X16)) +T(0x8820bf9b, STLXP(W0, W27, W15, X28)) +T(0x8824811a, STLXP(W4, W26, W0, X8)) +T(0x8835c975, STLXP(W21, W21, W18, X11)) +T(0xc82d8ef0, STLXP(W13, X16, X3, X23)) +T(0xc8209aa0, STLXP(W0, X0, X6, X21)) +T(0xc83d8a2c, STLXP(W29, X12, X2, X17)) +T(0x881afc2b, STLXR(W26, W11, X1)) +T(0x881efe87, STLXR(W30, W7, X20)) +T(0x8807fcb4, STLXR(W7, W20, X5)) +T(0xc807fd09, STLXR(W7, X9, X8)) +T(0xc815ffef, STLXR(W21, X15, SP)) +T(0xc809ffb4, STLXR(W9, X20, X29)) +T(0x0814ff76, STLXRB(W20, W22, X27)) +T(0x0814fff8, STLXRB(W20, W24, SP)) +T(0x0800fcec, STLXRB(W0, W12, X7)) +T(0x4812fd16, STLXRH(W18, W22, X8)) +T(0x4805fc10, STLXRH(W5, W16, X0)) +T(0x4808fda8, STLXRH(W8, W8, X13)) +T(0x2835e639, STNP(W25, W25, X17, -84)) +T(0x2803a64e, STNP(W14, W9, X18, 28)) +T(0x282d688d, STNP(W13, W26, X4, -152)) +T(0xa80069bb, STNP(X27, X26, X13)) +T(0xa8211567, STNP(X7, X5, X11, -496)) +T(0xa83abaea, STNP(X10, X14, X23, -88)) +T(0x28977de9, STP(W9, WZR, X15, POST_INDEXED, 184)) +T(0x28ab5ae0, STP(W0, W22, X23, POST_INDEXED, -168)) +T(0xa8803598, STP(X24, X13, X12, POST_INDEXED, 0)) +T(0xa8a15609, STP(X9, X21, X16, POST_INDEXED, -496)) +T(0x29a80797, STP(W23, W1, X28, PRE_INDEXED, -192)) +T(0x29b84e42, STP(W2, W19, X18, PRE_INDEXED, -64)) +T(0x2987acc3, STP(W3, W11, X6, PRE_INDEXED, 60)) +T(0xa99a78fa, STP(X26, X30, X7, PRE_INDEXED, 416)) +T(0xa9abf070, STP(X16, X28, X3, PRE_INDEXED, -328)) +T(0xa9bb7b8d, STP(X13, X30, X28, PRE_INDEXED, -80)) +T(0x293a6611, STP(W17, W25, X16, -48)) +T(0x293bdc3e, STP(W30, W23, X1, -36)) +T(0x292791a2, STP(W2, W4, X13, -196)) +T(0xa922272d, STP(X13, X9, X25, -480)) +T(0xa9222d40, STP(X0, X11, X10, -480)) +T(0xa90017ca, STP(X10, X5, X30)) +T(0xb8168414, STR(W20, X0, POST_INDEXED, -152)) +T(0xb8090760, STR(W0, X27, POST_INDEXED, 144)) +T(0xb81457d6, STR(W22, X30, POST_INDEXED, -187)) +T(0xf80e8585, STR(X5, X12, POST_INDEXED, 232)) +T(0xf81907f9, STR(X25, SP, POST_INDEXED, -112)) +T(0xf806956a, STR(X10, X11, POST_INDEXED, 105)) +T(0xb809ceba, STR(W26, X21, PRE_INDEXED, 156)) +T(0xb8073f34, STR(W20, X25, PRE_INDEXED, 115)) +T(0xb8087f73, STR(W19, X27, PRE_INDEXED, 135)) +T(0xf81c4c08, STR(X8, X0, PRE_INDEXED, -60)) +T(0xf80fde06, STR(X6, X16, PRE_INDEXED, 253)) +T(0xf80a8c2d, STR(X13, X1, PRE_INDEXED, 168)) +T(0xb91ab6cb, STR(W11, X22, 6836)) +T(0xb9223f0c, STR(W12, X24, 8764)) +T(0xb902a76c, STR(W12, X27, 676)) +T(0xf9025f66, STR(X6, X27, 1208)) +T(0xf90ada92, STR(X18, X20, 5552)) +T(0xf92357b6, STR(X22, X29, 18088)) +T(0xb82d79d8, STR(W24, X14, X13, LSL, 2)) +T(0xb83efa44, STR(W4, X18, X30, SXTX, 2)) +T(0xf835e97d, STR(X29, X11, X21, SXTX)) +T(0xf82fdb13, STR(X19, X24, W15, SXTW, 3)) +T(0x380e7738, STRB(W24, X25, POST_INDEXED, 231)) +T(0x381147c4, STRB(W4, X30, POST_INDEXED, -236)) +T(0x381c563f, STRB(WZR, X17, POST_INDEXED, -59)) +T(0x38169e52, STRB(W18, X18, PRE_INDEXED, -151)) +T(0x380f2c10, STRB(W16, X0, PRE_INDEXED, 242)) +T(0x3810bf4d, STRB(W13, X26, PRE_INDEXED, -245)) +T(0x391137e7, STRB(W7, SP, 1101)) +T(0x39277391, STRB(W17, X28, 2524)) +T(0x390f6812, STRB(W18, X0, 986)) +T(0x383f4922, STRB(W2, X9, WZR, UXTW)) +T(0x38244a8b, STRB(W11, X20, W4, UXTW)) +T(0x382c6ab6, STRB(W22, X21, X12, LSL, 0)) +T(0x382d6957, STRB(W23, X10, X13, LSL, 0)) +T(0x38246a7d, STRB(W29, X19, X4, LSL, 0)) +T(0x7806b5fd, STRH(W29, X15, POST_INDEXED, 107)) +T(0x7801b51e, STRH(W30, X8, POST_INDEXED, 27)) +T(0x780f25eb, STRH(W11, X15, POST_INDEXED, 242)) +T(0x78080d42, STRH(W2, X10, PRE_INDEXED, 128)) +T(0x78149fca, STRH(W10, X30, PRE_INDEXED, -183)) +T(0x7815cd49, STRH(W9, X10, PRE_INDEXED, -164)) +T(0x790fcf9a, STRH(W26, X28, 2022)) +T(0x790bc41f, STRH(WZR, X0, 1506)) +T(0x792f6fb7, STRH(W23, X29, 6070)) +T(0x78207b81, STRH(W1, X28, X0, LSL, 1)) +T(0xb81f79bd, STTR(W29, X13, -9)) +T(0xb80cba88, STTR(W8, X20, 203)) +T(0xb80aa968, STTR(W8, X11, 170)) +T(0xf8036b2e, STTR(X14, X25, 54)) +T(0xf81bc87b, STTR(X27, X3, -68)) +T(0xf80c4969, STTR(X9, X11, 196)) +T(0x380eda7c, STTRB(W28, X19, 237)) +T(0x380eba25, STTRB(W5, X17, 235)) +T(0x38135bac, STTRB(W12, X29, -203)) +T(0x78021bdc, STTRH(W28, X30, 33)) +T(0x78070930, STTRH(W16, X9, 112)) +T(0x7802fa0f, STTRH(W15, X16, 47)) +T(0xb812733d, STUR(W29, X25, -217)) +T(0xb811c2d9, STUR(W25, X22, -228)) +T(0xb819d3f0, STUR(W16, SP, -99)) +T(0xf801828a, STUR(X10, X20, 24)) +T(0xf81b9302, STUR(X2, X24, -71)) +T(0xf802a27b, STUR(X27, X19, 42)) +T(0x3817e34b, STURB(W11, X26, -130)) +T(0x380db1f8, STURB(W24, X15, 219)) +T(0x381db266, STURB(W6, X19, -37)) +T(0x7800639c, STURH(W28, X28, 6)) +T(0x780b72a9, STURH(W9, X21, 183)) +T(0x7813b3d6, STURH(W22, X30, -197)) +T(0x883e27bb, STXP(W30, W27, W9, X29)) +T(0x883c089b, STXP(W28, W27, W2, X4)) +T(0x883f4a30, STXP(WZR, W16, W18, X17)) +T(0xc8332606, STXP(W19, X6, X9, X16)) +T(0xc82f7009, STXP(W15, X9, X28, X0)) +T(0xc8213ca3, STXP(W1, X3, X15, X5)) +T(0x88137e6d, STXR(W19, W13, X19)) +T(0x88117eeb, STXR(W17, W11, X23)) +T(0x88157c63, STXR(W21, W3, X3)) +T(0xc81b7fb4, STXR(W27, X20, X29)) +T(0xc8157e0f, STXR(W21, X15, X16)) +T(0xc8017e07, STXR(W1, X7, X16)) +T(0x081a7dc7, STXRB(W26, W7, X14)) +T(0x08187fd4, STXRB(W24, W20, X30)) +T(0x08147d80, STXRB(W20, W0, X12)) +T(0x48117d88, STXRH(W17, W8, X12)) +T(0x480f7eb4, STXRH(W15, W20, X21)) +T(0x480c7e17, STXRH(W12, W23, X16)) +T(0x4b274cbd, SUB(W29, W5, W7, UXTW, 3)) +T(0x4b2ab198, SUB(W24, W12, W10, SXTH, 4)) +T(0xcb2c4698, SUB(X24, X20, W12, UXTW, 1)) +T(0x51794359, SUB(W25, W26, 3664, LSL, 12)) +T(0x5133a211, SUB(W17, W16, 3304)) +T(0x510948af, SUB(W15, W5, 594)) +T(0xd1088b3e, SUB(X30, X25, 546)) +T(0xd10478ac, SUB(X12, X5, 286)) +T(0xd12e98b0, SUB(X16, X5, 2982)) +T(0x4b8b06d7, SUB(W23, W22, W11, ASR, 1)) +T(0xcb4adab1, SUB(X17, X21, X10, LSR, 54)) +T(0xcb9656de, SUB(X30, X22, X22, ASR, 21)) +T(0x6b3d43b0, SUBS(W16, W29, W29, UXTW)) +T(0x6b3d48a8, SUBS(W8, W5, W29, UXTW, 2)) +T(0x71151784, SUBS(W4, W28, 1349)) +T(0x711256f6, SUBS(W22, W23, 1173)) +T(0x7177bf09, SUBS(W9, W24, 3567, LSL, 12)) +T(0xf14780b4, SUBS(X20, X5, 480, LSL, 12)) +T(0xf148fefb, SUBS(X27, X23, 575, LSL, 12)) +T(0xf146e7f4, SUBS(X20, SP, 441, LSL, 12)) +T(0x6b1031f2, SUBS(W18, W15, W16, LSL, 12)) +T(0x6b8333ce, SUBS(W14, W30, W3, ASR, 12)) +T(0xeb53b67e, SUBS(X30, X19, X19, LSR, 45)) +T(0xeb0b1ecb, SUBS(X11, X22, X11, LSL, 7)) +T(0xeb89fbaa, SUBS(X10, X29, X9, ASR, 62)) +T(0xd4189fe1, SVC(0xc4ff)) +T(0xd4150361, SVC(0xa81b)) +T(0xd4076cc1, SVC(0x3b66)) +T(0x13001fd4, SXTB(W20, W30)) +T(0x13001f06, SXTB(W6, W24)) +T(0x13001d79, SXTB(W25, W11)) +T(0x93401dd3, SXTB(X19, W14)) +T(0x93401c21, SXTB(X1, W1)) +T(0x93401c3f, SXTB(XZR, W1)) +T(0x13003cdb, SXTH(W27, W6)) +T(0x13003efe, SXTH(W30, W23)) +T(0x13003e8a, SXTH(W10, W20)) +T(0x93403f2a, SXTH(X10, W25)) +T(0x93403dcf, SXTH(X15, W14)) +T(0x93403c86, SXTH(X6, W4)) +T(0x93407f3e, SXTW(X30, W25)) +T(0x93407ff0, SXTW(X16, WZR)) +T(0x93407c33, SXTW(X19, W1)) +// T(0xd50c191e, SYS(4, C1, C9, 0, X30)) +// T(0xd50b81cc, SYS(3, C8, C1, 6, X12)) +// T(0xd508c696, SYS(0, C12, C6, 4, X22)) +// T(0xd5295947, SYSL(X7, 1, C5, C9, 2)) +// T(0xd52e3309, SYSL(X9, 6, C3, C3, 0)) +// T(0xd52ed8e8, SYSL(X8, 6, C13, C8, 7)) +T(0x375080a2, TBNZ(W2, 10, 4116)) +T(0x370be7cf, TBNZ(W15, 1, 31992)) +T(0x3767c975, TBNZ(W21, 12, -1748)) +T(0x36f2fd0d, TBZ(W13, 30, 24480)) +T(0x360d605e, TBZ(W30, 1, -21496)) +T(0xb68a3a8a, TBZ(X10, 49, 18256)) +// T(0xd50a891b, TLBI(SYS 2, C8, C9, 0, X27)) +// T(0xd50e84aa, TLBI(SYS 6, C8, C4, 5, X10)) +// T(0xd50b8326, TLBI(SYS 3, C8, C3, 1, X6)) +T(0x720291df, TST(W14, 0xc007c007)) +T(0x7200475f, TST(W26, 0x3ffff)) +T(0x7202e85f, TST(W2, 0xdddddddd)) +T(0xf20550ff, TST(X7, 0xf800fffff800ffff)) +T(0xf27cee1f, TST(X16, 0xfffffffffffffff0)) +T(0xf25ec0ff, TST(X7, 0xfffffffc0007ffff)) +T(0x6ac3053f, TST(W9, W3, ROR, 1)) +T(0xea492dbf, TST(X13, X9, LSR, 11)) +T(0xea14741f, TST(X0, X20, LSL, 29)) +T(0xeacab8df, TST(X6, X10, ROR, 46)) +T(0x53163c68, UBFIZ(W8, W3, 10, 16)) +T(0xd341ffc7, LSR(X7, X30, 1)) +T(0xd3488e5d, UBFX(X29, X18, 8, 28)) +T(0xd350a352, UBFX(X18, X26, 16, 25)) +T(0x531e2975, UBFIZ(W21, W11, 2, 11)) +T(0xd35cd8fe, UBFX(X30, X7, 28, 27)) +T(0xd34a1ac5, UBFIZ(X5, X22, 54, 7)) +T(0xd349058e, UBFIZ(X14, X12, 55, 2)) +T(0xd34fcc95, UBFX(X21, X4, 15, 37)) +T(0xd36f46a6, UBFIZ(X6, X21, 17, 18)) +T(0xd34d7391, UBFX(X17, X28, 13, 16)) +T(0x0000d975, UDF(55669)) +T(0x00000de0, UDF(3552)) +T(0x0000743c, UDF(29756)) +T(0x1adf0ae2, UDIV(W2, W23, WZR)) +T(0x1ad60938, UDIV(W24, W9, W22)) +T(0x1acc0a9a, UDIV(W26, W20, W12)) +T(0x9ad20927, UDIV(X7, X9, X18)) +T(0x9adc08da, UDIV(X26, X6, X28)) +T(0x9ace08ea, UDIV(X10, X7, X14)) +T(0x9ba85eac, UMADDL(X12, W21, W8, X23)) +T(0x9baf6c1b, UMADDL(X27, W0, W15, X27)) +T(0x9baa0e23, UMADDL(X3, W17, W10, X3)) +T(0x9ba2ff0b, UMNEGL(X11, W24, W2)) +T(0x9bb6fe3f, UMNEGL(XZR, W17, W22)) +T(0x9bb7fe5d, UMNEGL(X29, W18, W23)) +T(0x9bb7bfa4, UMSUBL(X4, W29, W23, X15)) +T(0x9bbb81ba, UMSUBL(X26, W13, W27, X0)) +T(0x9bb38c6d, UMSUBL(X13, W3, W19, X3)) +T(0x9bdb7c70, UMULH(X16, X3, X27)) +T(0x9bc47f0f, UMULH(X15, X24, X4)) +T(0x9bcf7c4b, UMULH(X11, X2, X15)) +T(0x9ba77ddd, UMULL(X29, W14, W7)) +T(0x9bad7e73, UMULL(X19, W19, W13)) +T(0x9ba27fd0, UMULL(X16, W30, W2)) +T(0x53001db9, UXTB(W25, W13)) +T(0x53001cd1, UXTB(W17, W6)) +T(0x53001e24, UXTB(W4, W17)) +T(0x53003ed1, UXTH(W17, W22)) +T(0x53003de4, UXTH(W4, W15)) +T(0x53003ce2, UXTH(W2, W7)) +T(0xd503205f, WFE()) +T(0xd503207f, WFI()) +T(0xd503203f, YIELD()) diff --git a/tests/rand_int.hpp b/tests/rand_int.hpp new file mode 100644 index 00000000..90afc6b3 --- /dev/null +++ b/tests/rand_int.hpp @@ -0,0 +1,20 @@ +// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime +// SPDX-License-Identifier: MIT + +#pragma once + +#include +#include + +template +T RandInt(T min, T max) +{ + static_assert(std::is_integral_v, "T must be an integral type."); + static_assert(!std::is_same_v && !std::is_same_v, + "Using char with uniform_int_distribution is undefined behavior."); + + static std::random_device rd; + static std::mt19937 mt(rd()); + std::uniform_int_distribution rand(min, max); + return rand(mt); +}