From 64fa804dd422574b8437964c99daeeb324e807a6 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Sat, 16 May 2020 12:40:12 -0400
Subject: [PATCH] A32: Implement ASIMD VBIC (register)

---
 src/frontend/A32/decoder/asimd.inc            |  2 +-
 .../A32/translate/impl/asimd_three_same.cpp   | 20 +++++++++++++++++++
 .../A32/translate/impl/translate_arm.h        |  1 +
 3 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc
index d6bf31b5..f0e69841 100644
--- a/src/frontend/A32/decoder/asimd.inc
+++ b/src/frontend/A32/decoder/asimd.inc
@@ -3,7 +3,7 @@
 //INST(asimd_VQADD,           "VQADD",                    "1111001U0-CC--------0000---1----") // ASIMD
 //INST(asimd_VRHADD,          "VRHADD",                   "1111001U0-CC--------0001---0----") // ASIMD
 INST(asimd_VAND_reg,        "VAND (register)",          "111100100D00nnnndddd0001NQM1mmmm") // ASIMD
-//INST(asimd_VBIC_reg,        "VBIC (register)",          "111100100-01--------0001---1----") // ASIMD
+INST(asimd_VBIC_reg,        "VBIC (register)",          "111100100D01nnnndddd0001NQM1mmmm") // ASIMD
 //INST(asimd_VORR_reg,        "VORR (register)",          "111100100-10--------0001---1----") // ASIMD
 //INST(asimd_VORN_reg,        "VORN (register)",          "111100100-11--------0001---1----") // ASIMD
 //INST(asimd_VEOR_reg,        "VEOR (register)",          "111100110-00--------0001---1----") // ASIMD
diff --git a/src/frontend/A32/translate/impl/asimd_three_same.cpp b/src/frontend/A32/translate/impl/asimd_three_same.cpp
index d54b6c69..996ccbda 100644
--- a/src/frontend/A32/translate/impl/asimd_three_same.cpp
+++ b/src/frontend/A32/translate/impl/asimd_three_same.cpp
@@ -32,4 +32,24 @@ bool ArmTranslatorVisitor::asimd_VAND_reg(bool D, size_t Vn, size_t Vd, bool N,
     return true;
 }
 
+bool ArmTranslatorVisitor::asimd_VBIC_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
+    if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
+        return UndefinedInstruction();
+    }
+
+    const auto d = ToExtReg(Vd, D);
+    const auto m = ToExtReg(Vm, M);
+    const auto n = ToExtReg(Vn, N);
+    const size_t regs = Q ? 2 : 1;
+
+    for (size_t i = 0; i < regs; i++) {
+        const IR::U32U64 reg_m = ir.GetExtendedRegister(m + i);
+        const IR::U32U64 reg_n = ir.GetExtendedRegister(n + i);
+        const IR::U32U64 result = ir.And(reg_n, ir.Not(reg_m));
+        ir.SetExtendedRegister(d + i, result);
+    }
+
+    return true;
+}
+
 } // namespace Dynarmic::A32
diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h
index db70e370..4619d5b7 100644
--- a/src/frontend/A32/translate/impl/translate_arm.h
+++ b/src/frontend/A32/translate/impl/translate_arm.h
@@ -431,6 +431,7 @@ struct ArmTranslatorVisitor final {
 
     // Advanced SIMD three register variants
     bool asimd_VAND_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
+    bool asimd_VBIC_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
 
     // Advanced SIMD load/store structures
     bool v8_VLD_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t sz, size_t align, Reg m);