From 6ad1bce5e0826b8d9b1e4500b4f605991e2f142d Mon Sep 17 00:00:00 2001 From: Lioncash Date: Thu, 15 Mar 2018 16:59:48 -0400 Subject: [PATCH] A64: Implement REV16 (vector) --- src/frontend/A64/decoder/a64.inc | 2 +- .../impl/simd_scalar_two_register_misc.cpp | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 6eb38953..17264de9 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -566,7 +566,7 @@ INST(INS_elt, "INS (element)", "01101 // Data Processing - FP and SIMD - SIMD Two-register misc //INST(REV64_asimd, "REV64", "0Q001110zz100000000010nnnnnddddd") -//INST(REV16_asimd, "REV16 (vector)", "0Q001110zz100000000110nnnnnddddd") +INST(REV16_asimd, "REV16 (vector)", "0Q001110zz100000000110nnnnnddddd") //INST(SADDLP, "SADDLP", "0Q001110zz100000001010nnnnnddddd") //INST(SUQADD_2, "SUQADD", "0Q001110zz100000001110nnnnnddddd") //INST(CLS_asimd, "CLS (vector)", "0Q001110zz100000010010nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp index dab547f7..23cd7315 100644 --- a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp +++ b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp @@ -8,6 +8,22 @@ namespace Dynarmic::A64 { +bool TranslatorVisitor::REV16_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) { + if (size != 0) { + return UnallocatedEncoding(); + } + + const size_t datasize = Q ? 128 : 64; + constexpr size_t esize = 16; + + const IR::U128 data = V(datasize, Vn); + const IR::U128 result = ir.VectorOr(ir.VectorLogicalShiftRight(esize, data, 8), + ir.VectorLogicalShiftLeft(esize, data, 8)); + + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) { const auto esize = sz ? 64 : 32;