diff --git a/src/frontend/A32/decoder/vfp.inc b/src/frontend/A32/decoder/vfp.inc
index c1407ded..e37fad25 100644
--- a/src/frontend/A32/decoder/vfp.inc
+++ b/src/frontend/A32/decoder/vfp.inc
@@ -13,7 +13,7 @@ INST(vfp_VFNMA,            "VFNMA",                   "cccc11101D01nnnndddd101zN
 INST(vfp_VFMA,             "VFMA",                    "cccc11101D10nnnndddd101zN0M0mmmm") // VFPv4
 INST(vfp_VFMS,             "VFMS",                    "cccc11101D10nnnndddd101zN1M0mmmm") // VFPv4
 //INST(vfp_VSEL,             "VSEL",                    "111111100Dccnnnndddd101zN0M0mmmm") // VFPv5
-//INST(vfp_VMAXNM,           "VMAXNNM",                 "111111101D00nnnndddd101zN0M0mmmm") // VFPv5
+INST(vfp_VMAXNM,           "VMAXNNM",                 "111111101D00nnnndddd101zN0M0mmmm") // VFPv5
 //INST(vfp_VMINNM,           "VMINNM",                  "111111101D00nnnndddd101zN1M0mmmm") // VFPv5
 
 // Other floating-point data-processing instructions
diff --git a/src/frontend/A32/disassembler/disassembler_arm.cpp b/src/frontend/A32/disassembler/disassembler_arm.cpp
index 2c74a346..d5fa63f0 100644
--- a/src/frontend/A32/disassembler/disassembler_arm.cpp
+++ b/src/frontend/A32/disassembler/disassembler_arm.cpp
@@ -1274,6 +1274,10 @@ public:
         return fmt::format("vfma{}.{} {}, {}, {}", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M));
     }
 
+    std::string vfp_VMAXNM(bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
+        return fmt::format("vmaxnm.{} {}, {}, {}", sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vn, N), FPRegStr(sz, Vm, M));
+    }
+
     std::string vfp_VMOV_imm(Cond cond, bool D, Imm<4> imm4H, size_t Vd, bool sz, Imm<4> imm4L) {
         const auto imm8 = concatenate(imm4H, imm4L);
 
diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h
index b3053aa6..8cc2c355 100644
--- a/src/frontend/A32/translate/impl/translate_arm.h
+++ b/src/frontend/A32/translate/impl/translate_arm.h
@@ -392,6 +392,7 @@ struct ArmTranslatorVisitor final {
     bool vfp_VFNMA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
     bool vfp_VFMA(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
     bool vfp_VFMS(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
+    bool vfp_VMAXNM(bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
 
     // Floating-point move instructions
     bool vfp_VMOV_imm(Cond cond, bool D, Imm<4> imm4H, size_t Vd, bool sz, Imm<4> imm4L);
diff --git a/src/frontend/A32/translate/impl/vfp.cpp b/src/frontend/A32/translate/impl/vfp.cpp
index 3af21683..eb538e72 100644
--- a/src/frontend/A32/translate/impl/vfp.cpp
+++ b/src/frontend/A32/translate/impl/vfp.cpp
@@ -336,6 +336,21 @@ bool ArmTranslatorVisitor::vfp_VFMS(Cond cond, bool D, size_t Vn, size_t Vd, boo
     });
 }
 
+// VMAXNM.F64 <Dd>, <Dn>, <Dm>
+// VMAXNM.F32 <Sd>, <Sn>, <Sm>
+bool ArmTranslatorVisitor::vfp_VMAXNM(bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
+    const auto d = ToExtReg(sz, Vd, D);
+    const auto n = ToExtReg(sz, Vn, N);
+    const auto m = ToExtReg(sz, Vm, M);
+
+    return EmitVfpVectorOperation(sz, d, n, m, [this](ExtReg d, ExtReg n, ExtReg m) {
+        const auto reg_n = ir.GetExtendedRegister(n);
+        const auto reg_m = ir.GetExtendedRegister(m);
+        const auto result = ir.FPMaxNumeric(reg_n, reg_m, true);
+        ir.SetExtendedRegister(d, result);
+    });
+}
+
 // VMOV<c>.32 <Dd[0]>, <Rt>
 bool ArmTranslatorVisitor::vfp_VMOV_u32_f64(Cond cond, size_t Vd, Reg t, bool D) {
     if (t == Reg::PC) {