From 6f59c2cd8e5ce8d128ed7b199be9d47724686cbc Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sat, 20 Jun 2020 15:07:06 +0100 Subject: [PATCH] A32: Implement ASIMD VRECPE --- .../x64/emit_x64_vector_floating_point.cpp | 17 ++++++------ src/frontend/A32/decoder/asimd.inc | 2 +- .../translate/impl/asimd_two_regs_misc.cpp | 27 +++++++++++++++++++ .../A32/translate/impl/translate_arm.h | 1 + src/frontend/ir/ir_emitter.cpp | 8 +++--- src/frontend/ir/ir_emitter.h | 2 +- src/frontend/ir/opcodes.inc | 6 ++--- tests/A32/fuzz_arm.cpp | 2 +- 8 files changed, 47 insertions(+), 18 deletions(-) diff --git a/src/backend/x64/emit_x64_vector_floating_point.cpp b/src/backend/x64/emit_x64_vector_floating_point.cpp index b0478635..154e12cc 100644 --- a/src/backend/x64/emit_x64_vector_floating_point.cpp +++ b/src/backend/x64/emit_x64_vector_floating_point.cpp @@ -378,11 +378,12 @@ void EmitThreeOpVectorOperation(BlockOfCode& code, EmitContext& ctx, IR::Inst* i ctx.reg_alloc.DefineValue(inst, result); } -template +template void EmitTwoOpFallback(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Lambda lambda) { const auto fn = static_cast*>(lambda); auto args = ctx.reg_alloc.GetArgumentInfo(inst); + const bool fpcr_controlled = fcarg == FpcrControlledArgument::Absent || args[1].GetImmediateU1(); const Xbyak::Xmm arg1 = ctx.reg_alloc.UseXmm(args[0]); const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm(); ctx.reg_alloc.EndOfAllocScope(); @@ -392,7 +393,7 @@ void EmitTwoOpFallback(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Lamb code.sub(rsp, stack_space + ABI_SHADOW_SPACE); code.lea(code.ABI_PARAM1, ptr[rsp + ABI_SHADOW_SPACE + 0 * 16]); code.lea(code.ABI_PARAM2, ptr[rsp + ABI_SHADOW_SPACE + 1 * 16]); - code.mov(code.ABI_PARAM3.cvt32(), ctx.FPCR().Value()); + code.mov(code.ABI_PARAM3.cvt32(), ctx.FPCR(fpcr_controlled).Value()); code.lea(code.ABI_PARAM4, code.ptr[code.r15 + code.GetJitStateInfo().offsetof_fpsr_exc]); code.movaps(xword[code.ABI_PARAM2], arg1); @@ -1144,7 +1145,7 @@ void EmitX64::EmitFPVectorPairedAddLower64(EmitContext& ctx, IR::Inst* inst) { template static void EmitRecipEstimate(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { - EmitTwoOpFallback(code, ctx, inst, [](VectorArray& result, const VectorArray& operand, FP::FPCR fpcr, FP::FPSR& fpsr) { + EmitTwoOpFallback(code, ctx, inst, [](VectorArray& result, const VectorArray& operand, FP::FPCR fpcr, FP::FPSR& fpsr) { for (size_t i = 0; i < result.size(); i++) { result[i] = FP::FPRecipEstimate(operand[i], fpcr, fpsr); } @@ -1188,12 +1189,12 @@ static void EmitRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in MaybeStandardFPSCRValue(code, ctx, fpcr_controlled, [&]{ code.movaps(result, GetVectorOf(code)); FCODE(vfnmadd231p)(result, operand1, operand2); - }); - FCODE(vcmpunordp)(tmp, result, result); - code.vptest(tmp, tmp); - code.jnz(fallback, code.T_NEAR); - code.L(end); + FCODE(vcmpunordp)(tmp, result, result); + code.vptest(tmp, tmp); + code.jnz(fallback, code.T_NEAR); + code.L(end); + }); code.SwitchToFarCode(); code.L(fallback); diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 6671581f..458e8979 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -103,7 +103,7 @@ INST(asimd_VSWP, "VSWP", "111100111D110010dddd000 //INST(asimd_VQMOVN, "VQMOVN", "111100111-11--10----00101x-0----") // ASIMD //INST(asimd_VSHLL_max, "VSHLL_max", "111100111-11--10----001100-0----") // ASIMD //INST(asimd_VCVT_half, "VCVT (half-precision)", "111100111-11--10----011x00-0----") // ASIMD -//INST(asimd_VRECPE, "VRECPE", "111100111-11--11----010x0x-0----") // ASIMD +INST(asimd_VRECPE, "VRECPE", "111100111D11zz11dddd010F0QM0mmmm") // ASIMD //INST(asimd_VRSQRTE, "VRSQRTE", "111100111-11--11----010x1x-0----") // ASIMD //INST(asimd_VCVT_integer, "VCVT (integer)", "111100111-11--11----011xxx-0----") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp index d06ab5a2..870ed77f 100644 --- a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp +++ b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp @@ -352,4 +352,31 @@ bool ArmTranslatorVisitor::asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t return true; } + +bool ArmTranslatorVisitor::asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) { + if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + return UndefinedInstruction(); + } + + if (sz == 0b00 || sz == 0b11) { + return UndefinedInstruction(); + } + + if (!F && sz == 0b01) { + // TODO: Implement 16-bit VectorUnsignedRecipEstimate + return UndefinedInstruction(); + } + + const size_t esize = 8U << sz; + + const auto d = ToVector(Q, Vd, D); + const auto m = ToVector(Q, Vm, M); + const auto reg_m = ir.GetVector(m); + const auto result = F ? ir.FPVectorRecipEstimate(esize, reg_m, false) + : ir.VectorUnsignedRecipEstimate(reg_m); + + ir.SetVector(d, result); + return true; +} + } // namespace Dynarmic::A32 diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index ca916b32..af6c6a12 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -499,6 +499,7 @@ struct ArmTranslatorVisitor final { bool asimd_VABS(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); bool asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); bool asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm); + bool asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); // Advanced SIMD load/store structures bool v8_VST_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t sz, size_t align, Reg m); diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp index 35e66a8f..e3fd1807 100644 --- a/src/frontend/ir/ir_emitter.cpp +++ b/src/frontend/ir/ir_emitter.cpp @@ -2440,14 +2440,14 @@ U128 IREmitter::FPVectorPairedAddLower(size_t esize, const U128& a, const U128& UNREACHABLE(); } -U128 IREmitter::FPVectorRecipEstimate(size_t esize, const U128& a) { +U128 IREmitter::FPVectorRecipEstimate(size_t esize, const U128& a, bool fpcr_controlled) { switch (esize) { case 16: - return Inst(Opcode::FPVectorRecipEstimate16, a); + return Inst(Opcode::FPVectorRecipEstimate16, a, Imm1(fpcr_controlled)); case 32: - return Inst(Opcode::FPVectorRecipEstimate32, a); + return Inst(Opcode::FPVectorRecipEstimate32, a, Imm1(fpcr_controlled)); case 64: - return Inst(Opcode::FPVectorRecipEstimate64, a); + return Inst(Opcode::FPVectorRecipEstimate64, a, Imm1(fpcr_controlled)); } UNREACHABLE(); } diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h index 6852295f..3b0052bc 100644 --- a/src/frontend/ir/ir_emitter.h +++ b/src/frontend/ir/ir_emitter.h @@ -360,7 +360,7 @@ public: U128 FPVectorNeg(size_t esize, const U128& a); U128 FPVectorPairedAdd(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); U128 FPVectorPairedAddLower(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); - U128 FPVectorRecipEstimate(size_t esize, const U128& a); + U128 FPVectorRecipEstimate(size_t esize, const U128& a, bool fpcr_controlled = true); U128 FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); U128 FPVectorRoundInt(size_t esize, const U128& operand, FP::RoundingMode rounding, bool exact); U128 FPVectorRSqrtEstimate(size_t esize, const U128& a); diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc index 655d624c..3b7cdd0d 100644 --- a/src/frontend/ir/opcodes.inc +++ b/src/frontend/ir/opcodes.inc @@ -613,9 +613,9 @@ OPCODE(FPVectorPairedAdd32, U128, U128 OPCODE(FPVectorPairedAdd64, U128, U128, U128, U1 ) OPCODE(FPVectorPairedAddLower32, U128, U128, U128, U1 ) OPCODE(FPVectorPairedAddLower64, U128, U128, U128, U1 ) -OPCODE(FPVectorRecipEstimate16, U128, U128 ) -OPCODE(FPVectorRecipEstimate32, U128, U128 ) -OPCODE(FPVectorRecipEstimate64, U128, U128 ) +OPCODE(FPVectorRecipEstimate16, U128, U128, U1 ) +OPCODE(FPVectorRecipEstimate32, U128, U128, U1 ) +OPCODE(FPVectorRecipEstimate64, U128, U128, U1 ) OPCODE(FPVectorRecipStepFused16, U128, U128, U128, U1 ) OPCODE(FPVectorRecipStepFused32, U128, U128, U128, U1 ) OPCODE(FPVectorRecipStepFused64, U128, U128, U128, U1 ) diff --git a/tests/A32/fuzz_arm.cpp b/tests/A32/fuzz_arm.cpp index 60998fa9..ab706300 100644 --- a/tests/A32/fuzz_arm.cpp +++ b/tests/A32/fuzz_arm.cpp @@ -111,7 +111,7 @@ u32 GenRandomInst(u32 pc, bool is_last_inst) { // FPSCR is inaccurate "vfp_VMRS", // Unimplemented in Unicorn - "asimd_VPADD_float", + "asimd_VPADD_float", "asimd_VRECPE", // Incorrect Unicorn implementations "asimd_VRECPS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP. };