From 715db8381f9e3d711a92817eac6d5b9857654114 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sat, 20 Jun 2020 20:08:11 +0100 Subject: [PATCH] A32: Implement ASIMD VMUL (scalar) --- src/CMakeLists.txt | 1 + src/frontend/A32/decoder/asimd.h | 13 +++++++ src/frontend/A32/decoder/asimd.inc | 3 +- .../translate/impl/asimd_two_regs_scalar.cpp | 38 +++++++++++++++++++ .../A32/translate/impl/translate_arm.h | 3 ++ 5 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 src/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 15e2d083..f03642d0 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -128,6 +128,7 @@ if ("A32" IN_LIST DYNARMIC_FRONTENDS) frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp frontend/A32/translate/impl/asimd_three_same.cpp frontend/A32/translate/impl/asimd_two_regs_misc.cpp + frontend/A32/translate/impl/asimd_two_regs_scalar.cpp frontend/A32/translate/impl/asimd_two_regs_shift.cpp frontend/A32/translate/impl/barrier.cpp frontend/A32/translate/impl/branch.cpp diff --git a/src/frontend/A32/decoder/asimd.h b/src/frontend/A32/decoder/asimd.h index 61a26e51..ce9726cd 100644 --- a/src/frontend/A32/decoder/asimd.h +++ b/src/frontend/A32/decoder/asimd.h @@ -40,10 +40,23 @@ std::vector> GetASIMDDecodeTable() { const std::set comes_first{ "VBIC, VMOV, VMVN, VORR (immediate)" }; + const std::set comes_last{ + "VMLA (scalar)", + "VMLAL (scalar)", + "VQDMLAL/VQDMLSL", + "VMUL (scalar)", + "VMULL (scalar)", + "VQDMULL", + "VQDMULH", + "VQRDMULH", + }; std::stable_partition(table.begin(), table.end(), [&](const auto& matcher) { return comes_first.count(matcher.GetName()) > 0; }); + std::stable_partition(table.begin(), table.end(), [&](const auto& matcher) { + return comes_last.count(matcher.GetName()) == 0; + }); return table; } diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 47c8f503..e9007d96 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -50,10 +50,11 @@ INST(asimd_VRECPS, "VRECPS", "111100100D0znnnndddd111 INST(asimd_VRSQRTS, "VRSQRTS", "111100100D1znnnndddd1111NQM1mmmm") // ASIMD // Two registers and a scalar +INST(arm_UDF, "UNALLOCATED", "1111001-1-11-------------1-0----") // ASIMD //INST(asimd_VMLA_scalar, "VMLA (scalar)", "1111001U1-BB--------0x0x-1-0----") // ASIMD //INST(asimd_VMLAL_scalar, "VMLAL (scalar)", "1111001U1-BB--------0x10-1-0----") // ASIMD //INST(asimd_VQDMLAL, "VQDMLAL/VQDMLSL", "111100101-BB--------0x11-1-0----") // ASIMD -//INST(asimd_VMUL_scalar, "VMUL (scalar)", "1111001U1-BB--------100x-1-0----") // ASIMD +INST(asimd_VMUL_scalar, "VMUL (scalar)", "1111001Q1Dzznnnndddd100FN1M0mmmm") // ASIMD //INST(asimd_VMULL_scalar, "VMULL (scalar)", "1111001U1-BB--------1010-1-0----") // ASIMD //INST(asimd_VQDMULL, "VQDMULL", "111100101-BB--------1011-1-0----") // ASIMD //INST(asimd_VQDMULH, "VQDMULH", "1111001U1-BB--------1100-1-0----") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp new file mode 100644 index 00000000..1a276fee --- /dev/null +++ b/src/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp @@ -0,0 +1,38 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2020 MerryMage + * SPDX-License-Identifier: 0BSD + */ + +#include "common/assert.h" +#include "common/bit_util.h" + +#include "frontend/A32/translate/impl/translate_arm.h" + +namespace Dynarmic::A32 { + +bool ArmTranslatorVisitor::asimd_VMUL_scalar(bool Q, bool D, size_t sz, size_t Vn, size_t Vd, bool F, bool N, bool M, size_t Vm) { + ASSERT_MSG(sz != 0b11, "Decode error"); + if (sz == 0b00 || (F && sz == 0b01)) { + return UndefinedInstruction(); + } + if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn))) { + return UndefinedInstruction(); + } + + const auto d = ToVector(Q, Vd, D); + const auto n = ToVector(Q, Vn, N); + const size_t esize = 8u << sz; + + const auto m = ExtReg::Q0 + ((Vm >> 1) & (esize == 16 ? 0b11 : 0b111)); + const auto index = concatenate(Imm<1>{Common::Bit<0>(Vm)}, Imm<1>{M}, Imm<1>{Common::Bit<3>(Vm)}).ZeroExtend() >> (esize == 16 ? 0 : 1); + const auto scalar = ir.VectorGetElement(esize, ir.GetVector(m), index); + + const auto reg_n = ir.GetVector(n); + const auto reg_m = ir.VectorBroadcast(esize, scalar); + const auto result = F ? ir.FPVectorMul(esize, reg_n, reg_m, false) : ir.VectorMultiply(esize, reg_n, reg_m); + + ir.SetVector(d, result); + return true; +} + +} // namespace Dynarmic::A32 diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index 040a4c51..9d2f3c7e 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -475,6 +475,9 @@ struct ArmTranslatorVisitor final { bool asimd_VRECPS(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VRSQRTS(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); + // Advanced SIMD two registers and a scalar + bool asimd_VMUL_scalar(bool Q, bool D, size_t sz, size_t Vn, size_t Vd, bool F, bool N, bool M, size_t Vm); + // Two registers and a shift amount bool asimd_SHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm); bool asimd_SRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);